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NDR (AArch64): Fix ismmx value assignment

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Cacodemon345
2025-09-14 11:11:26 +00:00
parent 1488097c7b
commit ffed72f823
2 changed files with 6 additions and 4 deletions
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7
src/codegen_new/codegen_backend_arm64_ops.c
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@@ -226,11 +226,11 @@
# define IMM_LOGICAL(imm) ((imm) << 10)
# define BIT_TBxZ(bit) ((((bit) &0x1f) << 19) | (((bit) &0x20) ? (1 << 31) : 0))
# define BIT_TBxZ(bit) ((((bit) & 0x1f) << 19) | (((bit) & 0x20) ? (1 << 31) : 0))
# define OFFSET14(offset) (((offset >> 2) << 5) & 0x0007ffe0)
# define OFFSET19(offset) (((offset >> 2) << 5) & 0x00ffffe0)
# define OFFSET20(offset) (((offset & 3) << 29) | ((((offset) &0x1fffff) >> 2) << 5))
# define OFFSET20(offset) (((offset & 3) << 29) | ((((offset) & 0x1fffff) >> 2) << 5))
# define OFFSET26(offset) ((offset >> 2) & 0x03ffffff)
# define OFFSET12_B(offset) (offset << 10)
@@ -1227,7 +1227,8 @@ host_arm64_SQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
codegen_addlong(block, OPCODE_SQXTN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}
void host_arm64_SQXTUN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
void
host_arm64_SQXTUN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SQXTUN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}

3
src/codegen_new/codegen_backend_arm64_uops.c
View File

@@ -801,7 +801,8 @@ codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.tag[0] - (uintptr_t) &cpu_state);
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.tag[4] - (uintptr_t) &cpu_state);
host_arm64_STR_IMM_W(block, REG_WZR, REG_CPUSTATE, (uintptr_t) &cpu_state.TOP - (uintptr_t) &cpu_state);
host_arm64_STRB_IMM(block, REG_WZR, REG_CPUSTATE, (uintptr_t) &cpu_state.ismmx - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 1);
host_arm64_STRB_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.ismmx - (uintptr_t) &cpu_state);
return 0;
}