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422 Commits

Author SHA1 Message Date
tiseno100
233ec2ddf3 ACC 2168 improvements 2020-09-29 12:42:40 +03:00
tiseno100
dd914429d8 Added the Phoenix 486 Jumper Readout port 
A must have for Phoenix 486 machines
 2020-09-29 12:07:03 +03:00
Miran Grča
fffb0bb0f8 Merge pull request #1009 from richardg867/master 
PCI bridge support
 2020-09-23 06:04:08 +02:00
RichardG867
eb79cb1782 PCI/AGP bridge support, part 3 2020-09-20 19:13:09 -03:00
RichardG867
f459c676c4 PCI/AGP bridge support, part 2: now with VIA 2020-09-19 01:29:35 -03:00
RichardG867
3314bd4035 PCI/AGP bridge support, part 1 2020-09-19 00:56:12 -03:00
tiseno100
99b60d6422 Delete mcr.c 
There's no need for that anymore.
 2020-09-17 18:57:52 +03:00
tiseno100
280e69fb0c Revert changes. Keep the humane methods of initialization on the Intel 82335. 
The issue with the ADI was caused by the incorrect lock status on early initialization.
 2020-09-16 17:59:33 +03:00
tiseno100
8464883e22 Brute set configuration on the Intel 82335 
Fixes the ADI 386SX freezing while booting an OS when shadowing is on.
 2020-09-16 17:52:09 +03:00
tiseno100
e5de57cffb Removed Port 92h off the Intel 82335 
The chipset doesn't seem to use it.
 2020-09-14 13:24:34 +03:00
tiseno100
a364b10a51 Disabled logging once again -_- 2020-09-14 13:20:19 +03:00
tiseno100
270b585854 Fixed some shadow issues on the Intel 82335 
The lock register determines also if Shadowing is RW or RO.
 2020-09-14 13:18:29 +03:00
tiseno100
1dd64678f7 Cap definition names 2020-09-13 16:23:09 +03:00
tiseno100
07cd6e0994 A tiny change on the commentary 2020-09-12 15:02:52 +03:00
tiseno100
5f3c976fbe Some final touches on the Intel 82335 
Most I could potentially implement are now complete
- Added some commentary
- switched some complex algorithms into definitions for the sake of the code being clean
- Implemented the ROM size determination register just for some Shadow RAM sanity
 2020-09-12 15:01:20 +03:00
tiseno100
00c70a83b7 Added the Base Memory set register on the Intel 82335 
Enables/Disables the top 128KB of base system memory.
 2020-09-11 13:19:02 +03:00
Miran Grča
92ff0d7d39 Merge pull request #996 from richardg867/master 
ALi M6117 SoC implementation
 2020-09-11 01:56:54 +02:00
tiseno100
f582d4b432 Disabled logging again 2020-09-11 00:08:57 +03:00
tiseno100
2e7781505a Added more 82335 parts 
Registers are treated with an array instead of separate values.
Minor Shadowing changes and also implemented the chipset lock mechanism fixing the ADI soft reset issue properly.
 2020-09-10 23:56:51 +03:00
tiseno100
54c569e5be System ROM shadowing doesn't depend from the selected register. It actually depends on the Video RAM 
Also seems like the System ROM is RO. RW causes it to hang
 2020-09-10 19:55:11 +03:00
tiseno100
7a075e35e3 Disable logging 2020-09-10 19:50:53 +03:00
tiseno100
b36f3be457 Fixed soft reset failures of the ADI 386SX 2020-09-10 19:48:18 +03:00
tiseno100
0993643327 Delete the old Intel 82335 code 2020-09-10 19:47:41 +03:00
tiseno100
0e24c8883d Full Intel 82335 rewrite 
Fixes black screen when you shadow video RAM. More checks may be required to get MR 82335 to work properly.
 2020-09-10 15:48:43 +03:00
RichardG867
5b016edb2a Add non-working AMI M6117 machine 2020-09-08 22:54:30 -03:00
RichardG867
8d44f2e329 Remove unused M6117 SMRAM function 2020-09-08 22:10:35 -03:00
RichardG867
4ca4ab76ae Merge branch 'master' of https://github.com/86Box/86Box 2020-09-08 21:44:28 -03:00
RichardG867
777a6d02e0 Indentation cleanups on STPC 2020-09-08 21:44:10 -03:00
RichardG867
a8c813cb4b Initial implementation of ALi M6117D 2020-09-08 21:43:54 -03:00
OBattler
2569bcbf43 Added a sanity check on write to PIIX4(E) DDMA base PCI registers. 2020-09-08 03:42:42 +02:00
tiseno100
20cd01aaca Added the US Technologies 386 motherboard. 
Late 386 motherboard using the Award 4.50G BIOS.
 2020-08-19 23:51:40 +03:00
tiseno100
2915080f02 Some rework on the write procedure of the ALi M1489 2020-08-11 10:36:04 +03:00
tiseno100
415a4c4f58 Mass ALi work 
It includes the M1489 which the rewritten M1429. Also a machine for the new 931APM SIO
 2020-08-10 12:20:29 +03:00
OBattler
949e145be3 Rewrite of AT keyboard controller polling. 2020-08-04 04:01:54 +02:00
RichardG867
e1b07f2fee Change special 440BX VPC behavior to is_vpc 2020-07-25 12:28:13 -03:00
RichardG867
e8f2fb0915 Isolate 440BX special behavior to devbranch 2020-07-24 15:02:59 -03:00
RichardG867
763b61c469 Add special behavior for a reserved 440BX bus speed bit for the Virtual PC 2007 machine 2020-07-24 15:00:58 -03:00
RichardG867
9efdf74b51 Merge branch 'master' of https://github.com/86Box/86Box 2020-07-24 13:48:29 -03:00
OBattler
751e5962d7 Fixed the bus speed register on the 440BX. 2020-07-24 17:06:43 +02:00
RichardG867
a4cf2c7859 Fix STPC serial unlocking behavior, add some more comments to the code 2020-07-20 15:24:51 -03:00
RichardG867
31ca983604 Fix STPC UART port check 2020-07-20 15:07:54 -03:00
tiseno100
6bef7affd7 Chips & Technologies 486 emulation 
Some extremely basic 486 chipset. Used by very few motherboards.
 2020-07-19 13:46:01 +03:00
tiseno100
0fec9779ea Minor changes on the VIA 486's. 2020-07-18 14:24:08 +03:00
tiseno100
1701dc5a4a VIA 486 bringup 2020-07-17 14:18:54 +03:00
OBattler
d2a80b3f2b Some SCAMP fixes (of bugs revealed by GCC when compiling 64-bit 86Box). 2020-07-15 05:11:23 +02:00
RichardG867
9eb4577101 Merge branch 'master' of https://github.com/86Box/86Box 2020-07-14 22:25:11 -03:00
RichardG867
a1e273b13b STPC serial and parallel support 2020-07-14 22:24:22 -03:00
OBattler
c24a24c1cb Finished the Headland rework, now EMS works on both machines as it should, as does shadowing. 2020-07-14 03:47:37 +02:00
OBattler
d248039995 Finished the headland fixes, now EMS works again. 2020-07-12 03:54:28 +02:00
OBattler
8020f8e763 Some Headland chipset fixes. 2020-07-12 02:07:27 +02:00