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e0ea2b1f693a50919166ba30dd611eb8e8b08478
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121 Commits

Author SHA1 Message Date
OBattler
e0ea2b1f69 Fixed the STPC chipset PCI Vendor and Device ID's. 2020-07-11 00:56:45 +02:00
OBattler
0d2e69142d Fixed an IDE log line and fixed a bug in the implementation of the STPC chipsets caused by an erratum in the STPC Atlas programming manual (corrected in the other STPC chipsets' programming manuals). 2020-07-11 00:42:38 +02:00
OBattler
7ebe8f5018 Vastly improved the STPC PCI IDE controller emulation. 2020-07-10 04:23:10 +02:00
OBattler
f0633753fc Fixed STPC PCI IRQ steering again. 2020-07-10 03:14:15 +02:00
OBattler
fec5160bf4 Fixed STPC PCI IRQ steering and silenced the massive Voodoo warning. 2020-07-10 03:10:07 +02:00
OBattler
72c1c36ec6 OPTi 5x7 no longer does excess logging, running of timers on the recompiler is now done on every fourth AT KBC port 61h read instead of every 3F4h read, added some safety precautions to io.c to handle the cases where a handler removes itself, implmented the STPC ELCR and refresh control, and fixed the messed up register reading in the PC87307 and PC87309 implementations. 2020-07-10 02:05:49 +02:00
RichardG867
c23a9c984c Merge branch 'master' of https://github.com/86Box/86Box 2020-07-09 16:50:28 -03:00
RichardG867
37c5edacd0 STPC: Implement bus master IDE 2020-07-09 16:50:19 -03:00
OBattler
3a9c4cece2 Merge branch 'master' of https://github.com/86Box/86Box 2020-07-09 19:28:58 +02:00
OBattler
5a862e9551 Fixed 440GX ID without AGP and the FDC now causes the CPU to run the timers on MSR read when the recompiler is used. 2020-07-09 19:28:47 +02:00
Miran Grča
1186e7826f Merge pull request #914 from richardg867/master 
STPC PCI IRQ steering
 2020-07-09 17:55:46 +02:00
RichardG867
5304db348f STPC: disable PCI IRQs on reset 2020-07-08 18:25:35 -03:00
RichardG867
4ab5e7c5af STPC: implement PCI IRQ steering, leave blank space for ELCR registers 2020-07-08 18:21:06 -03:00
RichardG867
07fba1ce11 STPC: change hex values to upper case 2020-07-08 17:54:05 -03:00
nerd73
8be211c69a Merge branch 'master' into opti291 2020-07-08 02:00:46 -06:00
nerd73
263c48a49b Implement F0000-FFFFF shadowing on the OPTi 291 
The datasheet only gave a small reference to it in passing. Port 92 is also implemented as it is also present on the 291.
 2020-07-08 01:41:18 -06:00
OBattler
f696dc69ad Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine. 2020-07-08 04:24:25 +02:00
RichardG867
a1f267da72 Fix PCI IDs again 2020-07-07 17:07:08 -03:00
RichardG867
d8e3e44f59 Fix STPC PCI IDs again 2020-07-07 17:00:40 -03:00
RichardG867
1b637fbb77 Merge branch 'master' of https://github.com/86Box/86Box 2020-07-07 15:57:58 -03:00
OBattler
39a46797d2 Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur. 2020-07-07 20:43:28 +02:00
RichardG867
5e18163b2e Fix STPC CPU identification 
Let port 22h/23h registers >= 0xc0 fall through to the Cyrix port 22h/23h code in cpu.c
 2020-07-07 15:38:34 -03:00
RichardG867
f7e7359d2f Merge branch 'master' of https://github.com/86Box/86Box 2020-07-07 13:26:49 -03:00
RichardG867
5b0e29d0ff STPC improvements 2020-07-07 13:25:17 -03:00
tiseno100
91d7dd149a Commented the OPTi 283 logging code back 2020-07-07 16:40:07 +03:00
tiseno100
2137c4ea85 Fixed a minor mistake 2020-07-07 16:38:10 +03:00
tiseno100
ebe7f1cdf3 Rewrote the OPTi 283 shadowing 
Now it'll pass a check to see if we are write protecting or have write enabled.
 2020-07-07 16:36:44 +03:00
RichardG867
710796a180 Add ITOX STAR, a STPC Client machine with hardware monitoring and AMIBIOS 6 2020-07-06 21:12:09 -03:00
RichardG867
1ed6143f02 Implement STPC IDE 
Note that only the AR-B1479 has two IDE channels available on the board.
 2020-07-06 20:24:24 -03:00
RichardG867
c1dd844747 Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/machine/machine_table.c
#	src/win/Makefile.mingw
 2020-07-06 18:47:50 -03:00
RichardG867
11114c97d2 Initial implementation of STPC chipsets and machines 2020-07-06 18:45:34 -03:00
nerd73
2b06dbc10b Merge branch 'opti291' of https://github.com/nerd73/86Box into opti291 2020-07-03 03:09:48 -06:00
nerd73
ff000b53cc actually make it work this time 2020-07-03 03:09:09 -06:00
nerd73
6a9fa51d78 fix header 2020-07-03 00:24:48 -06:00
nerd73
5b260dbfd4 Add a 386SX Award v4.20 machine 
As well as a basic implementation of the OPTi 291 chipset that it uses.
 2020-07-03 00:18:16 -06:00
tiseno100
525a6f0278 Added the RYC Leopard LX 
An interesting kind of 386DXish/486 kind of board. Uses the IBM 486SLC(only!) which is commonly found in PS/2 & PS/1 286 & 386 computers as an "upgrade" chip
 2020-07-02 22:10:36 +03:00
Miran Grča
56098700d1 Merge pull request #882 from nerd73/pythonfix 
Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
 2020-06-30 15:56:29 +02:00
OBattler
81d178e9f6 Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip. 2020-06-30 15:37:07 +02:00
nerd73
546f0a83e7 Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset 2020-06-29 22:06:27 -06:00
OBattler
13e8d9c923 Fixed Shadow RAM handling for all OPTi 486 chipsets. 2020-06-30 03:24:06 +02:00
OBattler
9402f98a3b Rewrote the OPTi 82C495 emulation, added the OPTi 82C493, did some changes to the 82C8xx, and updated Makefile.local. 2020-06-30 00:34:49 +02:00
OBattler
a4301708da Added the OPTi 802G device (the 802G and 895 are register-identical), and added port 23h to the OPTi 8xx'es. 2020-06-29 18:44:20 +02:00
OBattler
4a8aa601b6 Fixed (and improved) the OPTi 895 chipset implementation. 2020-06-29 18:13:14 +02:00
tiseno100
388825377c Implemented the OPTi 895 
Similar the OPTi 495 & 802G. It's a 486 ISA/VLB chipset used by many known boards. One being the PB450.
 2020-06-29 16:26:18 +03:00
OBattler
5c1f947122 The VLSI VL82C480 chipset now has Port 92h, fixes the IBM PS/1 model 2133. 2020-06-29 14:33:12 +02:00
OBattler
014552f235 Fixes to SiS 496/497 and W83787F. 2020-06-29 04:32:30 +02:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
RichardG867
aea5461255 Implement DRB locking for VIA Apollo chipsets 2020-06-26 22:05:32 -03:00
RichardG867
2553dbce8f Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD 2020-06-26 21:03:46 -03:00
RichardG867
93b909fe59 Merge branch 'master' of https://github.com/86Box/86Box 2020-06-26 18:05:57 -03:00