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155 Commits

Author SHA1 Message Date
Cacodemon345
5e0dd65738 Add color/chroma-keying to S3 Trio64V+ and Trio64V2/DX 
Clean up some TODOs in Voodoo 3/Banshee code
 2025-08-19 23:56:51 +06:00
Cacodemon345
60d9ceb7a8 Use "chroma-keying" as the description for now 2025-08-19 20:41:31 +06:00
Cacodemon345
cdbb628625 Implement color keying for S3 ViRGE 2025-08-19 18:07:38 +06:00
Cacodemon345
69853ed832 Fix 15/16-bpp mode on S3 ViRGEs (pre-GX2 and non-VX) 2025-08-18 16:29:48 +06:00
TC1995
1a5b4671e8 XGA/SVGA mode changes of the day (July 22nd, 2025) 
1. If the VGA mapping is for a 0xA0000 map for a length of 0x10000, then disable XGA mode (this is independent of the XGA extended mode aperture mode 1 which is XGA's own 0xA0000 mapping).
2. Remove text mode ctrl-alt-del hack.
3. Fixed cursor x coordinate in the Trio32 using 15bpp/16bpp modes.
 2025-07-22 20:45:54 +02:00
Daniel Gurney
aef9d1ed94 Revert "Merge branch 'bugfixes' into master" 
This reverts commit 8250b57325, reversing
changes made to 6c643d05b8.
 2025-07-01 03:04:14 +03:00
starfrost
8250b57325 Merge branch 'bugfixes' into master 2025-07-01 00:28:27 +01:00
win2kgamer
212401bed6 Ensure the S3 ViRGE type is correctly assigned including when using an onboard ViRGE 2025-06-22 21:29:46 -05:00
starfrost013
adb8b388a8 v_disp -> vdisp_latch; get rid of even more unused shit 2025-06-21 00:55:39 +01:00
starfrost013
dd7f3d0aae ma -> memaddr 
ma_latch -> memaddr_latch
maback -> memaddr_backup
ca -> cursoraddr
sc -> scanline
oldsc -> scanline_old
 2025-06-10 22:53:45 +01:00
TC1995
cdb01de6d4 Apply it to the virge too. 2025-04-22 21:33:21 +02:00
Jasmine Iwanek
bb155ea9ef Cleanups in vid_s3_virge.c 2025-03-10 05:41:27 -04:00
Cacodemon345
92d69475f4 Only retain the newer IRQ updating code 2025-03-05 02:18:01 +06:00
Cacodemon345
73576bb61e Revert "S3 ViRGE: Make IRQs happen in main thread" 
This reverts commit fae26729f1.
 2025-03-05 02:18:01 +06:00
Cacodemon345
e24c9d5163 S3 ViRGE: Use a significantly faster version of the ROP code 
DirectDraw tests now run significantly faster, and Direct3D tests also now run smoothly.
 2025-03-03 23:22:24 +06:00
Cacodemon345
fae26729f1 S3 ViRGE: Make IRQs happen in main thread 
FIFO is also no longer immediately woken up upon writes
 2025-03-03 22:03:52 +06:00
Jasmine Iwanek
d5d1d5c449 More cleanups to device structs 2025-02-08 01:28:25 -05:00
Jasmine Iwanek
5b894c32e6 Macro Cleaning 2025-02-08 01:28:24 -05:00
Jasmine Iwanek
81b8038bc5 Clean up .available & .poll 2025-02-01 03:38:52 -05:00
TC1995
8f51ca82b0 ViRGE changes of the day (December 22nd, 2024) 
1. Proper pixel clock implemented on GX2 and up chips. Fixes speed on various stuff (including games for Windows).
2. Cleanup.
 2024-12-22 19:21:32 +01:00
TC1995
dd5c5f4a07 More ViRGE fixes (August 29th, 2024) 
Apparently the extended sequencer registers (>= 0x20) are required to have sane values on the STREAMS engine on GX2 and probably other chips in the ViRGE range.
 2024-08-29 00:51:28 +02:00
TC1995
47ee1c4ead Some fixes to the Streams engine of the ViRGE/Trio3D 
Make sure the ViRGE GX2 and up (including the Trio3D/2X) use the secondary stream only per what was found in the past.
 2024-08-27 22:17:52 +02:00
Miran Grča
d67d86d266 Merge pull request #4723 from MaxwellS04/mirocrystal_3d 
Add miroCRYSTAL 3D video card
 2024-08-26 06:38:22 +02:00
OBattler
ba859d7351 S3: Fixed CRTC to PCI BAR mapping, fixes #4745. 2024-08-26 04:36:23 +02:00
OBattler
f9e457f3e8 Give the AP440FX the original ViRGE instead, fixes #4740. 2024-08-22 04:59:51 +02:00
MaxwellS04
eabfc12290 Merge branch '86Box:master' into mirocrystal_3d 2024-08-21 07:22:01 +07:00
OBattler
71ff5c8c63 ViRGE: Fixed some warnings that only appear when compiling a debug binary. 2024-08-21 01:33:54 +02:00
TC1995
aebaabb6b8 ViRGE changes of the day (August 20th, 2024) 
1. ROM updated to 1.03.
2. Re-apply more fixes that were missed during the restructuring to be on par with PCem's speed.
3. Implemented Command DMA bus mastering required by Diamond Stealth 3D specific drivers (especially the GX2-based 4000).
4. Some indentation fixes.
 2024-08-20 15:45:56 +02:00
OBattler
dc8d237126 S3 ViRGE: Force bit 2 of CRTC register 33h to be set when read, fixes Windows 95 GX2 lock-ups. 2024-08-17 19:46:29 +02:00
OBattler
366ebea651 S3 ViRGE fixes by TC995 and switched threads on Windows builds back to Win32 threads since the C++ threads were breaking the ViRGE blitting in some cases (eg. CD Gamer on 24 bpp). 2024-08-17 01:22:06 +02:00
MaxwellS04
a02b4e52c3 Fixed configuration 2024-08-17 00:53:02 +07:00
MaxwellS04
24e2c65c40 Fixed a compile-breaking mistake 2024-08-16 20:44:51 +07:00
MaxwellS04
ab71f9d3e2 Added the miroCRYSTAL 3D, based on a S3 ViRGE. 2024-08-16 20:36:26 +07:00
OBattler
88741b021e S3 ViRGE: Some minor memory mask fixes. 2024-08-16 05:58:24 +02:00
OBattler
537e6f76de S3 ViRGE: Replace code with re-cleaned-up PCem code with our changes manually re-applied, also revert hardware cursor offset checks, which fixes black bars in games. 2024-08-16 05:43:55 +02:00
TC1995
a0d662e9c5 S3 changes (and TVP3026) of the day (August 15th, 2024) 
1. TVP3026: disable lut mapping on 24bpp modes (mainly the S3 Vision968 drivers which use the TVP3026 ramdac).
2. S3 Vision968 (MiroVideo 40SV Ergo): Corrected 1280x1024 24bpp resolution.
3. ViRGE class: limit the FIFO entries in the bitblt regs to less than 16 entries and make the Image Transfers FIFO writes wraparound to 1 and reads to 0 (to allow at least a read to a write in the thread without hanging the entire emulator). Fixes Win3.1 PBRUSH colors while keeping performance on par with PCem.
 2024-08-15 23:04:48 +02:00
OBattler
08fc20bcc5 S3 Virge: Bring the threading completely up to par with PCem. 2024-08-14 22:47:06 +02:00
TC1995
a7b7b1af67 Attempt at fixing the threading of the ViRGE. 2024-08-14 20:33:32 +02:00
TC1995
70c622aecd S3 ViRGE class: Rethreading for future investigation. 2024-08-14 19:24:55 +02:00
OBattler
e377e58881 Assorted fixes and Dev branched the Matrox G100 and the PCL printer. 2024-07-26 00:39:11 +02:00
TC1995
b91a0d1a14 Initial implementation of the timed FIFO on the ViRGE 
See above.
 2024-07-25 21:40:37 +02:00
OBattler
a369bc2d05 Reimplement S3 ViRGE reset and move PCI TRC CPU reset to outside the recompiled block, fixes #2903. 2024-06-12 20:46:27 +02:00
TC1995
eff32906c5 Fix onboard flag for actual onboard ViRGE BIOSes. 
So that ViRGE cards can work again without black screening.
 2024-05-30 16:35:32 +02:00
TC1995
0897eea7df Plus a compile fix. 2024-05-30 00:43:00 +02:00
TC1995
11d7afd578 Video changes part 3 (minor though) 
1. Added an on-board S3 ViRGE DX (375) video card to the Intel AP440FX socket 8-based machine alongside its on-board CS4236B audio.
2. Sanity check for on-board S3 ViRGE devices.
 2024-05-30 00:13:29 +02:00
Cacodemon345
a0ef980a2c S3 ViRGE/GX2: Fix frozen display when stream processors are enabled 2024-02-25 14:33:17 +06:00
TC1995
c00e854fce Fix compile. 
See above.
 2024-02-24 21:52:06 +01:00
TC1995
21230f933e Temporary solution to a 24bpp issue and hblank. 
So that 24bpp color is not discolored anymore as well as hblank bugs being nulled.
 2024-02-24 21:50:01 +01:00
Cacodemon345
b49cd0baf4 S3 ViRGE: Buffer flips no longer trigger recalctimings 2024-02-24 02:51:42 +06:00
Cacodemon345
181ffbcffb S3 ViRGE: a bit of cleanup 2024-02-23 20:47:27 +06:00