1175 lines
30 KiB
C
1175 lines
30 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the STMicroelectronics STPC series of SoCs.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/smram.h>
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#include <86box/io.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/device.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/usb.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/serial.h>
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#include <86box/lpt.h>
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#include <86box/chipset.h>
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#define STPC_CONSUMER2 0x104a020b
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#define STPC_ATLAS 0x104a0210
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#define STPC_ELITE 0x104a021a
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#define STPC_CLIENT 0x100e55cc
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typedef struct stpc_t {
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uint8_t nb_slot;
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uint8_t sb_slot;
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uint8_t ide_slot;
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uint8_t usb_slot;
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uint32_t local;
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/* Main registers (port 22h/23h) */
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uint8_t reg_offset;
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uint8_t regs[256];
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/* Host bus interface */
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uint16_t host_base;
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uint8_t host_offset;
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uint8_t usb_irq_state;
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uint8_t host_regs[256];
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/* Local bus */
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uint16_t localbus_base;
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uint8_t localbus_offset;
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uint8_t pad0;
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uint8_t localbus_regs[256];
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/* PCI devices */
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uint8_t pci_conf[4][256];
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smram_t *smram;
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usb_t *usb;
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sff8038i_t *bm[2];
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} stpc_t;
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typedef struct stpc_serial_t {
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serial_t *uart[2];
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} stpc_serial_t;
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typedef struct stpc_lpt_t {
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uint8_t unlocked;
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uint8_t offset;
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uint8_t reg1;
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uint8_t reg4;
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} stpc_lpt_t;
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#ifdef ENABLE_STPC_LOG
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int stpc_do_log = ENABLE_STPC_LOG;
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static void
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stpc_log(const char *fmt, ...)
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{
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va_list ap;
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if (stpc_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define stpc_log(fmt, ...)
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#endif
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static void
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stpc_recalcmapping(stpc_t *dev)
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{
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uint32_t base;
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uint32_t size;
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int state;
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shadowbios = 0;
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shadowbios_write = 0;
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for (uint8_t reg = 0; reg <= 3; reg++) {
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for (uint8_t bitpair = 0; bitpair <= ((reg == 3) ? 0 : 3); bitpair++) {
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if (reg == 3) {
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size = 0x10000;
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base = 0xf0000;
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} else {
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size = 0x4000;
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base = 0xc0000 + (size * ((reg * 4) + bitpair));
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}
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stpc_log("STPC: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
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state = 0;
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if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
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stpc_log(" w on");
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state |= MEM_WRITE_INTERNAL;
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if (base >= 0xe0000)
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shadowbios_write |= 1;
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} else {
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stpc_log(" w off");
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state |= MEM_WRITE_EXTANY;
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}
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if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
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stpc_log("; r on\n");
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state |= MEM_READ_INTERNAL;
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if (base >= 0xe0000)
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shadowbios |= 1;
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} else {
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stpc_log("; r off\n");
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state |= MEM_READ_EXTANY;
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}
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mem_set_mem_state(base, size, state);
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}
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}
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flushmmucache_nopc();
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}
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static void
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stpc_host_write(uint16_t addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: host_write(%04X, %02X)\n", addr, val);
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if (addr == dev->host_base)
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dev->host_offset = val;
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else if (addr == (dev->host_base + 4))
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dev->host_regs[dev->host_offset] = val;
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}
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static uint8_t
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stpc_host_read(uint16_t addr, void *priv)
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{
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const stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (addr == dev->host_base)
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ret = dev->host_offset;
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else if (addr == (dev->host_base + 4))
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ret = dev->host_regs[dev->host_offset];
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else
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ret = 0xff;
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stpc_log("STPC: host_read(%04X) = %02X\n", addr, ret);
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return ret;
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}
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static void
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stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: localbus_write(%04X, %02X)\n", addr, val);
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if (addr == dev->localbus_base)
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dev->localbus_offset = val;
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else if (addr == (dev->localbus_base + 4))
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dev->localbus_regs[addr] = val;
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}
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static uint8_t
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stpc_localbus_read(uint16_t addr, void *priv)
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{
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const stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (addr == dev->localbus_base)
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ret = dev->localbus_offset;
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else if (addr == (dev->localbus_base + 4))
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ret = dev->localbus_regs[dev->localbus_offset];
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else
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ret = 0xff;
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stpc_log("STPC: localbus_read(%04X) = %02X\n", addr, ret);
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return ret;
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}
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static void
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stpc_nb_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: nb_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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case 0x51:
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case 0x53:
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case 0x54:
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return;
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case 0x05:
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val &= 0x01;
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break;
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case 0x50:
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val &= 0x1f;
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break;
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case 0x52:
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val &= 0x70;
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break;
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default:
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break;
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}
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dev->pci_conf[0][addr] = val;
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}
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static uint8_t
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stpc_nb_read(int func, int addr, void *priv)
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{
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const stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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else
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ret = dev->pci_conf[0][addr];
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stpc_log("STPC: nb_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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static void
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stpc_ide_handlers(stpc_t *dev, int bus)
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{
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uint16_t main;
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uint16_t side;
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if (bus & 0x01) {
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ide_pri_disable();
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if (dev->pci_conf[2][0x09] & 0x01) {
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main = (dev->pci_conf[2][0x11] << 8) | (dev->pci_conf[2][0x10] & 0xf8);
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side = ((dev->pci_conf[2][0x15] << 8) | (dev->pci_conf[2][0x14] & 0xfc)) + 2;
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} else {
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main = 0x1f0;
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side = 0x3f6;
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}
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ide_set_base(0, main);
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ide_set_side(0, side);
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stpc_log("STPC: IDE primary main %04X side %04X enable ", main, side);
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if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x04)) {
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stpc_log("1\n");
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ide_pri_enable();
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} else {
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stpc_log("0\n");
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}
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}
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if (bus & 0x02) {
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ide_sec_disable();
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if (dev->pci_conf[2][0x09] & 0x04) {
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main = (dev->pci_conf[2][0x19] << 8) | (dev->pci_conf[2][0x18] & 0xf8);
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side = ((dev->pci_conf[2][0x1d] << 8) | (dev->pci_conf[2][0x1c] & 0xfc)) + 2;
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} else {
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main = 0x170;
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side = 0x376;
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}
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ide_set_base(1, main);
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ide_set_side(1, side);
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stpc_log("STPC: IDE secondary main %04X side %04X enable ", main, side);
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if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x08)) {
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stpc_log("1\n");
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ide_sec_enable();
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} else {
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stpc_log("0\n");
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}
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}
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}
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static void
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stpc_ide_bm_handlers(stpc_t *dev)
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{
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uint16_t base = (dev->pci_conf[2][0x20] & 0xf0) | (dev->pci_conf[2][0x21] << 8);
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sff_bus_master_handler(dev->bm[0], dev->pci_conf[2][0x04] & 1, base);
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sff_bus_master_handler(dev->bm[1], dev->pci_conf[2][0x04] & 1, base + 8);
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}
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static void
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stpc_ide_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: ide_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x04:
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dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0xbe) | (val & 0x41);
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stpc_ide_handlers(dev, 0x03);
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stpc_ide_bm_handlers(dev);
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break;
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case 0x05:
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dev->pci_conf[2][addr] = val & 0x01;
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break;
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case 0x07:
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dev->pci_conf[2][addr] &= ~(val & 0x70);
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break;
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case 0x09:
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dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0x8a) | (val & 0x05);
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stpc_ide_handlers(dev, 0x03);
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break;
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case 0x10:
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dev->pci_conf[2][addr] = (val & 0xf8) | 1;
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stpc_ide_handlers(dev, 0x01);
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break;
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case 0x11:
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dev->pci_conf[2][addr] = val;
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stpc_ide_handlers(dev, 0x01);
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break;
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case 0x14:
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dev->pci_conf[2][addr] = (val & 0xfc) | 1;
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stpc_ide_handlers(dev, 0x01);
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break;
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case 0x15:
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dev->pci_conf[2][addr] = val;
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stpc_ide_handlers(dev, 0x01);
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break;
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case 0x18:
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dev->pci_conf[2][addr] = (val & 0xf8) | 1;
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stpc_ide_handlers(dev, 0x02);
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break;
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case 0x19:
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dev->pci_conf[2][addr] = val;
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stpc_ide_handlers(dev, 0x02);
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break;
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case 0x1c:
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dev->pci_conf[2][addr] = (val & 0xfc) | 1;
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stpc_ide_handlers(dev, 0x02);
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break;
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case 0x1d:
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dev->pci_conf[2][addr] = val;
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stpc_ide_handlers(dev, 0x02);
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break;
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case 0x20:
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dev->pci_conf[2][0x20] = (val & 0xf0) | 1;
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stpc_ide_bm_handlers(dev);
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break;
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case 0x21:
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dev->pci_conf[2][0x21] = val;
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stpc_ide_bm_handlers(dev);
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break;
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case 0x3c:
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dev->pci_conf[2][addr] = val;
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break;
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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dev->pci_conf[2][addr] = val;
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break;
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case 0x48:
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dev->pci_conf[2][addr] = (val & 0x8c) & ~(val & 0x03);
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stpc_ide_handlers(dev, 0x03);
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if (val & 0x02) {
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sff_bus_master_set_irq(0x01, dev->bm[0]);
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sff_bus_master_set_irq(0x01, dev->bm[1]);
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}
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if (val & 0x01) {
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sff_bus_master_set_irq(0x00, dev->bm[0]);
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sff_bus_master_set_irq(0x00, dev->bm[1]);
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}
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break;
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default:
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break;
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}
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}
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static uint8_t
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stpc_ide_read(int func, int addr, void *priv)
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{
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const stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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else {
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ret = dev->pci_conf[2][addr];
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if (addr == 0x48) {
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ret &= 0xfc;
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ret |= !!(dev->bm[0]->status & 0x04);
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ret |= (!!(dev->bm[1]->status & 0x04)) << 1;
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}
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}
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stpc_log("STPC: ide_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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|
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static void
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stpc_isab_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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if ((func == 1) && (dev->local != STPC_ATLAS)) {
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stpc_ide_write(0, addr, val, priv);
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return;
|
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}
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|
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stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
|
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|
|
switch (addr) {
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case 0x00:
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x04:
|
|
case 0x06:
|
|
case 0x07:
|
|
case 0x08:
|
|
case 0x09:
|
|
case 0x0a:
|
|
case 0x0b:
|
|
case 0x0e:
|
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return;
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|
|
|
case 0x05:
|
|
val &= 0x01;
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break;
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default:
|
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break;
|
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}
|
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|
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dev->pci_conf[1][addr] = val;
|
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}
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|
|
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static uint8_t
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stpc_isab_read(int func, int addr, void *priv)
|
|
{
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const stpc_t *dev = (stpc_t *) priv;
|
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uint8_t ret;
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|
|
|
if ((func == 1) && (dev->local != STPC_ATLAS))
|
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ret = stpc_ide_read(0, addr, priv);
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else if (func > 0)
|
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ret = 0xff;
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else
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ret = dev->pci_conf[1][addr];
|
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|
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stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
|
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}
|
|
|
|
static void
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stpc_usb_write(int func, int addr, uint8_t val, void *priv)
|
|
{
|
|
stpc_t *dev = (stpc_t *) priv;
|
|
|
|
stpc_log("STPC: usb_write(%d, %02X, %02X)\n", func, addr, val);
|
|
|
|
if (func > 0)
|
|
return;
|
|
|
|
switch (addr) {
|
|
case 0x00:
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x04:
|
|
case 0x06:
|
|
case 0x07:
|
|
case 0x08:
|
|
case 0x09:
|
|
case 0x0a:
|
|
case 0x0b:
|
|
case 0x0e:
|
|
case 0x10:
|
|
return;
|
|
|
|
case 0x05:
|
|
val &= 0x01;
|
|
break;
|
|
|
|
case 0x11:
|
|
dev->pci_conf[3][addr] = val & 0xf0;
|
|
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
|
|
break;
|
|
|
|
case 0x12:
|
|
case 0x13:
|
|
dev->pci_conf[3][addr] = val;
|
|
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
dev->pci_conf[3][addr] = val;
|
|
}
|
|
|
|
static uint8_t
|
|
stpc_usb_read(int func, int addr, void *priv)
|
|
{
|
|
const stpc_t *dev = (stpc_t *) priv;
|
|
uint8_t ret;
|
|
|
|
if (func > 0)
|
|
ret = 0xff;
|
|
else
|
|
ret = dev->pci_conf[3][addr];
|
|
|
|
stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
stpc_remap_host(stpc_t *dev, uint16_t host_base)
|
|
{
|
|
stpc_log("STPC: Remapping host bus from %04X to %04X\n", dev->host_base, host_base);
|
|
|
|
io_removehandler(dev->host_base, 5,
|
|
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
|
|
if (host_base) {
|
|
io_sethandler(host_base, 5,
|
|
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
|
|
}
|
|
dev->host_base = host_base;
|
|
}
|
|
|
|
static void
|
|
stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
|
|
{
|
|
stpc_log("STPC: Remapping local bus from %04X to %04X\n", dev->localbus_base, localbus_base);
|
|
|
|
io_removehandler(dev->localbus_base, 5,
|
|
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
|
|
if (localbus_base) {
|
|
io_sethandler(localbus_base, 5,
|
|
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
|
|
}
|
|
dev->localbus_base = localbus_base;
|
|
}
|
|
|
|
static uint8_t
|
|
stpc_serial_handlers(uint8_t val)
|
|
{
|
|
const stpc_serial_t *dev = device_get_priv(&stpc_serial_device);
|
|
|
|
if (!dev) {
|
|
stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
|
|
return 0;
|
|
}
|
|
|
|
uint16_t uart0_io = 0x3f8;
|
|
uint16_t uart1_io = 0x3f8;
|
|
uint8_t uart0_irq = 4;
|
|
uint8_t uart1_irq = 3;
|
|
|
|
if (val & 0x10)
|
|
uart1_io &= 0xfeff;
|
|
if (val & 0x20)
|
|
uart1_io &= 0xffef;
|
|
if (val & 0x40)
|
|
uart0_io &= 0xfeff;
|
|
if (val & 0x80)
|
|
uart0_io &= 0xffef;
|
|
|
|
if (uart0_io == uart1_io) {
|
|
/* Apply defaults if both UARTs are set to the same address. */
|
|
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
|
|
uart0_io = 0x3f8;
|
|
uart1_io = 0x2f8;
|
|
}
|
|
|
|
if (!(uart0_io & 0x100)) {
|
|
/* The address for UART0 establishes the IRQs for both ports. */
|
|
uart0_irq = 3;
|
|
uart1_irq = 4;
|
|
}
|
|
|
|
stpc_log("STPC: Remapping UART0 to %04X %d and UART1 to %04X %d (raw %02X)\n", uart0_io, uart0_irq, uart1_io, uart1_irq, val);
|
|
|
|
serial_remove(dev->uart[0]);
|
|
serial_setup(dev->uart[0], uart0_io, uart0_irq);
|
|
serial_remove(dev->uart[1]);
|
|
serial_setup(dev->uart[1], uart1_io, uart1_irq);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
|
|
{
|
|
stpc_t *dev = (stpc_t *) priv;
|
|
|
|
stpc_log("STPC: reg_write(%04X, %02X)\n", addr, val);
|
|
|
|
if (addr == 0x22) {
|
|
dev->reg_offset = val;
|
|
} else {
|
|
stpc_log("STPC: regs[%02X] = %02X\n", dev->reg_offset, val);
|
|
|
|
switch (dev->reg_offset) {
|
|
case 0x12:
|
|
if (dev->regs[0x10] == 0x07)
|
|
stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
|
|
else if (dev->regs[0x10] == 0x06)
|
|
stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
|
|
break;
|
|
|
|
case 0x13:
|
|
if (dev->regs[0x10] == 0x07)
|
|
stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
|
|
else if (dev->regs[0x10] == 0x06)
|
|
stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
|
|
break;
|
|
|
|
case 0x21:
|
|
val &= 0xfe;
|
|
break;
|
|
|
|
case 0x22:
|
|
val &= 0x7f;
|
|
break;
|
|
|
|
case 0x25:
|
|
case 0x26:
|
|
case 0x27:
|
|
case 0x28:
|
|
if (dev->reg_offset == 0x28) {
|
|
val &= 0xe3;
|
|
smram_state_change(dev->smram, 0, !!(val & 0x80));
|
|
}
|
|
dev->regs[dev->reg_offset] = val;
|
|
stpc_recalcmapping(dev);
|
|
break;
|
|
|
|
case 0x29:
|
|
val &= 0x0f;
|
|
break;
|
|
|
|
case 0x36:
|
|
val &= 0x3f;
|
|
break;
|
|
|
|
case 0x52:
|
|
case 0x53:
|
|
case 0x54:
|
|
case 0x55:
|
|
stpc_log("STPC: Set IRQ routing: INT %c -> %d\n", 0x41 + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : -1);
|
|
val &= 0x8f;
|
|
pci_set_irq_routing(PCI_INTA + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : PCI_IRQ_DISABLED);
|
|
break;
|
|
|
|
case 0x56:
|
|
case 0x57:
|
|
pic_elcr_write(dev->reg_offset, val, (dev->reg_offset & 1) ? &pic2 : &pic);
|
|
if (dev->reg_offset == 0x57)
|
|
refresh_at_enable = (val & 0x01);
|
|
break;
|
|
|
|
case 0x59:
|
|
val &= 0xf1;
|
|
stpc_serial_handlers(val);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
dev->regs[dev->reg_offset] = val;
|
|
}
|
|
}
|
|
|
|
static uint8_t
|
|
stpc_reg_read(uint16_t addr, void *priv)
|
|
{
|
|
const stpc_t *dev = (stpc_t *) priv;
|
|
uint8_t ret;
|
|
|
|
if (addr == 0x22)
|
|
ret = dev->reg_offset;
|
|
else if (dev->reg_offset >= 0xc0)
|
|
return 0xff; /* let the CPU code handle Cyrix CPU registers */
|
|
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
|
|
/* ELCR registers. */
|
|
ret = pic_elcr_read(dev->reg_offset, (dev->reg_offset & 1) ? &pic2 : &pic);
|
|
if (dev->reg_offset == 0x57)
|
|
ret |= (dev->regs[dev->reg_offset] & 0x01);
|
|
} else
|
|
ret = dev->regs[dev->reg_offset];
|
|
|
|
stpc_log("STPC: reg_read(%04X) = %02X\n", dev->reg_offset, ret);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
stpc_reset(void *priv)
|
|
{
|
|
stpc_t *dev = (stpc_t *) priv;
|
|
|
|
stpc_log("STPC: reset()\n");
|
|
|
|
memset(dev->regs, 0, sizeof(dev->regs));
|
|
dev->regs[0x7b] = 0xff;
|
|
if (device_get_priv(&stpc_lpt_device))
|
|
dev->regs[0x4c] |= 0x80; /* LPT strap */
|
|
if (stpc_serial_handlers(0x00))
|
|
dev->regs[0x4c] |= 0x03; /* UART straps */
|
|
}
|
|
|
|
static void
|
|
stpc_setup(stpc_t *dev)
|
|
{
|
|
stpc_log("STPC: setup()\n");
|
|
|
|
/* Main register interface */
|
|
io_sethandler(0x22, 2,
|
|
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
|
|
|
|
/* Northbridge */
|
|
if (dev->local & STPC_CLIENT) {
|
|
dev->pci_conf[0][0x00] = 0x0e;
|
|
dev->pci_conf[0][0x01] = 0x10;
|
|
dev->pci_conf[0][0x02] = 0x64;
|
|
dev->pci_conf[0][0x03] = 0x05;
|
|
} else {
|
|
dev->pci_conf[0][0x00] = 0x4a;
|
|
dev->pci_conf[0][0x01] = 0x10;
|
|
dev->pci_conf[0][0x02] = 0x0a;
|
|
dev->pci_conf[0][0x03] = 0x02;
|
|
}
|
|
|
|
dev->pci_conf[0][0x04] = 0x07;
|
|
|
|
dev->pci_conf[0][0x06] = 0x80;
|
|
dev->pci_conf[0][0x07] = 0x02;
|
|
|
|
dev->pci_conf[0][0x0b] = 0x06;
|
|
|
|
/* ISA Bridge */
|
|
dev->pci_conf[1][0x00] = dev->local >> 16;
|
|
dev->pci_conf[1][0x01] = dev->local >> 24;
|
|
dev->pci_conf[1][0x02] = dev->local;
|
|
dev->pci_conf[1][0x03] = dev->local >> 8;
|
|
|
|
dev->pci_conf[1][0x04] = 0x0f;
|
|
|
|
dev->pci_conf[1][0x06] = 0x80;
|
|
dev->pci_conf[1][0x07] = 0x02;
|
|
|
|
dev->pci_conf[1][0x0a] = 0x01;
|
|
dev->pci_conf[1][0x0b] = 0x06;
|
|
|
|
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
|
|
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
|
|
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
|
|
dev->pci_conf[1][0x0e] = /*0x40*/ 0x80;
|
|
|
|
/* IDE */
|
|
dev->pci_conf[2][0x00] = dev->local >> 16;
|
|
dev->pci_conf[2][0x01] = dev->local >> 24;
|
|
|
|
if (dev->local == STPC_ATLAS) {
|
|
dev->pci_conf[2][0x02] = 0x28;
|
|
dev->pci_conf[2][0x03] = 0x02;
|
|
} else {
|
|
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
|
|
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
|
|
}
|
|
|
|
dev->pci_conf[2][0x06] = 0x80;
|
|
dev->pci_conf[2][0x07] = 0x02;
|
|
|
|
dev->pci_conf[2][0x09] = 0x8a;
|
|
dev->pci_conf[2][0x0a] = 0x01;
|
|
dev->pci_conf[2][0x0b] = 0x01;
|
|
|
|
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
|
|
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
|
|
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
|
|
dev->pci_conf[2][0x0e] = /*0x40*/ 0x80;
|
|
|
|
dev->pci_conf[2][0x10] = 0x01;
|
|
dev->pci_conf[2][0x14] = 0x01;
|
|
dev->pci_conf[2][0x18] = 0x01;
|
|
dev->pci_conf[2][0x1c] = 0x01;
|
|
dev->pci_conf[2][0x20] = 0x01;
|
|
|
|
dev->pci_conf[2][0x40] = 0x60;
|
|
dev->pci_conf[2][0x41] = 0x97;
|
|
dev->pci_conf[2][0x42] = 0x60;
|
|
dev->pci_conf[2][0x43] = 0x97;
|
|
dev->pci_conf[2][0x44] = 0x60;
|
|
dev->pci_conf[2][0x45] = 0x97;
|
|
dev->pci_conf[2][0x46] = 0x60;
|
|
dev->pci_conf[2][0x47] = 0x97;
|
|
|
|
/* USB */
|
|
if (dev->usb) {
|
|
dev->pci_conf[3][0x00] = dev->local >> 16;
|
|
dev->pci_conf[3][0x01] = dev->local >> 24;
|
|
dev->pci_conf[3][0x02] = 0x30;
|
|
dev->pci_conf[3][0x03] = 0x02;
|
|
|
|
dev->pci_conf[3][0x06] = 0x80;
|
|
dev->pci_conf[3][0x07] = 0x02;
|
|
|
|
dev->pci_conf[3][0x09] = 0x10;
|
|
dev->pci_conf[3][0x0a] = 0x03;
|
|
dev->pci_conf[3][0x0b] = 0x0c;
|
|
|
|
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
|
|
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
|
|
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
|
|
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
|
|
}
|
|
|
|
/* PCI setup */
|
|
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
|
|
}
|
|
|
|
static void
|
|
stpc_close(void *priv)
|
|
{
|
|
stpc_t *dev = (stpc_t *) priv;
|
|
|
|
stpc_log("STPC: close()\n");
|
|
|
|
smram_del(dev->smram);
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
stpc_init(const device_t *info)
|
|
{
|
|
stpc_log("STPC: init()\n");
|
|
|
|
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
|
|
memset(dev, 0, sizeof(stpc_t));
|
|
|
|
dev->local = info->local;
|
|
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev, &dev->nb_slot);
|
|
pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev, &dev->sb_slot);
|
|
if (dev->local == STPC_ATLAS) {
|
|
pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, stpc_ide_read, stpc_ide_write, dev, &dev->ide_slot);
|
|
|
|
dev->usb = device_add(&usb_device);
|
|
pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, stpc_usb_read, stpc_usb_write, dev, &dev->usb_slot);
|
|
}
|
|
|
|
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
|
|
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
|
|
|
|
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
|
|
|
|
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
|
|
|
|
stpc_setup(dev);
|
|
stpc_reset(dev);
|
|
|
|
dev->smram = smram_add();
|
|
|
|
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x00020000, 0, 1);
|
|
|
|
device_add(&port_92_pci_device);
|
|
|
|
pic_elcr_io_handler(0);
|
|
refresh_at_enable = 0;
|
|
|
|
return dev;
|
|
}
|
|
|
|
static void
|
|
stpc_serial_close(void *priv)
|
|
{
|
|
stpc_serial_t *dev = (stpc_serial_t *) priv;
|
|
|
|
stpc_log("STPC: serial_close()\n");
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
stpc_serial_init(UNUSED(const device_t *info))
|
|
{
|
|
stpc_log("STPC: serial_init()\n");
|
|
|
|
stpc_serial_t *dev = (stpc_serial_t *) malloc(sizeof(stpc_serial_t));
|
|
memset(dev, 0, sizeof(stpc_serial_t));
|
|
|
|
dev->uart[0] = device_add_inst(&ns16550_device, 1);
|
|
dev->uart[1] = device_add_inst(&ns16550_device, 2);
|
|
|
|
/* Initialization is performed by stpc_reset */
|
|
|
|
return dev;
|
|
}
|
|
|
|
static void
|
|
stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
|
|
{
|
|
uint8_t old_addr = (dev->reg1 & 0x03);
|
|
uint8_t new_addr = (val & 0x03);
|
|
|
|
switch (old_addr) {
|
|
case 0x1:
|
|
lpt3_remove();
|
|
break;
|
|
|
|
case 0x2:
|
|
lpt1_remove();
|
|
break;
|
|
|
|
case 0x3:
|
|
lpt2_remove();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (new_addr) {
|
|
case 0x1:
|
|
stpc_log("STPC: Remapping parallel port to LPT3\n");
|
|
lpt3_init(0x3bc);
|
|
break;
|
|
|
|
case 0x2:
|
|
stpc_log("STPC: Remapping parallel port to LPT1\n");
|
|
lpt1_init(0x378);
|
|
break;
|
|
|
|
case 0x3:
|
|
stpc_log("STPC: Remapping parallel port to LPT2\n");
|
|
lpt2_init(0x278);
|
|
break;
|
|
|
|
default:
|
|
stpc_log("STPC: Disabling parallel port\n");
|
|
break;
|
|
}
|
|
|
|
dev->reg1 = (val & 0x08);
|
|
dev->reg1 |= new_addr;
|
|
dev->reg1 |= 0x84; /* reserved bits that default to 1; hardwired? */
|
|
}
|
|
|
|
static void
|
|
stpc_lpt_write(uint16_t addr, uint8_t val, void *priv)
|
|
{
|
|
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
|
|
|
|
if (dev->unlocked < 2) {
|
|
/* Cheat a little bit: in reality, any write to any
|
|
I/O port is supposed to reset the unlock counter. */
|
|
if ((addr == 0x3f0) && (val == 0x55))
|
|
dev->unlocked++;
|
|
else
|
|
dev->unlocked = 0;
|
|
} else if (addr == 0x3f0) {
|
|
if (val == 0xaa)
|
|
dev->unlocked = 0;
|
|
else
|
|
dev->offset = val;
|
|
} else if (dev->offset == 1) {
|
|
/* dev->reg1 is set by stpc_lpt_handlers */
|
|
stpc_lpt_handlers(dev, val);
|
|
} else if (dev->offset == 4) {
|
|
dev->reg4 = (val & 0x03);
|
|
}
|
|
}
|
|
|
|
static void
|
|
stpc_lpt_reset(void *priv)
|
|
{
|
|
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
|
|
|
|
stpc_log("STPC: lpt_reset()\n");
|
|
|
|
dev->unlocked = 0;
|
|
dev->offset = 0x00;
|
|
dev->reg1 = 0x9f;
|
|
dev->reg4 = 0x00;
|
|
stpc_lpt_handlers(dev, dev->reg1);
|
|
}
|
|
|
|
static void
|
|
stpc_lpt_close(void *priv)
|
|
{
|
|
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
|
|
|
|
stpc_log("STPC: lpt_close()\n");
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
stpc_lpt_init(UNUSED(const device_t *info))
|
|
{
|
|
stpc_log("STPC: lpt_init()\n");
|
|
|
|
stpc_lpt_t *dev = (stpc_lpt_t *) malloc(sizeof(stpc_lpt_t));
|
|
memset(dev, 0, sizeof(stpc_lpt_t));
|
|
|
|
stpc_lpt_reset(dev);
|
|
|
|
io_sethandler(0x3f0, 2,
|
|
NULL, NULL, NULL, stpc_lpt_write, NULL, NULL, dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
/* STPC SoCs */
|
|
const device_t stpc_client_device = {
|
|
.name = "STPC Client",
|
|
.internal_name = "stpc_client",
|
|
.flags = DEVICE_PCI,
|
|
.local = STPC_CLIENT,
|
|
.init = stpc_init,
|
|
.close = stpc_close,
|
|
.reset = stpc_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t stpc_consumer2_device = {
|
|
.name = "STPC Consumer-II",
|
|
.internal_name = "stpc_consumer2",
|
|
.flags = DEVICE_PCI,
|
|
.local = STPC_CONSUMER2,
|
|
.init = stpc_init,
|
|
.close = stpc_close,
|
|
.reset = stpc_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t stpc_elite_device = {
|
|
.name = "STPC Elite",
|
|
.internal_name = "stpc_elite",
|
|
.flags = DEVICE_PCI,
|
|
.local = STPC_ELITE,
|
|
.init = stpc_init,
|
|
.close = stpc_close,
|
|
.reset = stpc_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t stpc_atlas_device = {
|
|
.name = "STPC Atlas",
|
|
.internal_name = "stpc_atlas",
|
|
.flags = DEVICE_PCI,
|
|
.local = STPC_ATLAS,
|
|
.init = stpc_init,
|
|
.close = stpc_close,
|
|
.reset = stpc_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
/* Auxiliary devices */
|
|
const device_t stpc_serial_device = {
|
|
.name = "STPC Serial UARTs",
|
|
.internal_name = "stpc_serial",
|
|
.flags = 0,
|
|
.local = 0,
|
|
.init = stpc_serial_init,
|
|
.close = stpc_serial_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t stpc_lpt_device = {
|
|
.name = "STPC Parallel Port",
|
|
.internal_name = "stpc_lpt",
|
|
.flags = 0,
|
|
.local = 0,
|
|
.init = stpc_lpt_init,
|
|
.close = stpc_lpt_close,
|
|
.reset = stpc_lpt_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|