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f831d3dd7c3962b43ca990f71436a262154b91e4
86Box/src/chipset
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OBattler f696dc69ad Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine.
2020-07-08 04:24:25 +02:00
..
acc2168.c
Revert "Merge branch 'master' of https://github.com/86Box/86Box"
2020-06-07 15:52:45 -03:00
ali1429.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
amd640.c
Implemented the AMD 640 chipset
2020-06-22 11:09:11 +03:00
cs8230.c
Ported the latest cs8230 patch from greatpsycho.
2020-06-17 23:47:37 +02:00
headland.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
i82335.c
Use the correct UNIX encoding on the i82335
2020-06-23 17:20:22 +03:00
intel_4x0.c
Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there.
2020-06-29 01:10:20 +02:00
intel_420ex.c
Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD
2020-06-26 21:03:46 -03:00
intel_piix.c
Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine.
2020-07-08 04:24:25 +02:00
intel_sio.c
Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged).
2020-06-15 17:08:42 +02:00
mcr.c
Moved the two (unused) Intel 386 chipset files to chipset/.
2020-06-13 10:27:07 +02:00
neat.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
opti5x7.c
Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur.
2020-07-07 20:43:28 +02:00
opti283.c
Commented the OPTi 283 logging code back
2020-07-07 16:40:07 +03:00
opti291.c
Merge branch 'opti291' of https://github.com/nerd73/86Box into opti291
2020-07-03 03:09:48 -06:00
opti495.c
Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur.
2020-07-07 20:43:28 +02:00
opti895.c
Fixed Shadow RAM handling for all OPTi 486 chipsets.
2020-06-30 03:24:06 +02:00
scamp.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
scat.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c50x.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c310.c
More reorganization and finally merged the two makefiles.
2020-06-13 12:32:09 +02:00
sis_85c471.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c496.c
Fixes to SiS 496/497 and W83787F.
2020-06-29 04:32:30 +02:00
stpc.c
Fix PCI IDs again
2020-07-07 17:07:08 -03:00
via_apollo.c
Implement DRB locking for VIA Apollo chipsets
2020-06-26 22:05:32 -03:00
via_vpx.c
Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD
2020-06-26 21:03:46 -03:00
via_vt82c586b.c
A slight reorganization of the source tree and fixed a warning in disk/mo.c.
2020-06-13 10:17:57 +02:00
via_vt82c596b.c
A slight reorganization of the source tree and fixed a warning in disk/mo.c.
2020-06-13 10:17:57 +02:00
vl82c480.c
Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip.
2020-06-30 15:37:07 +02:00
wd76c10.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00