315 lines
9.4 KiB
C
315 lines
9.4 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C283 chipset.
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*
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*
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Tiseno100.
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/plat_fallthrough.h>
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#include <86box/plat_unused.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_OPTI283_LOG
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int opti283_do_log = ENABLE_OPTI283_LOG;
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static void
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opti283_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti283_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define opti283_log(fmt, ...)
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#endif
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typedef struct mem_remapping_t {
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uint32_t phys;
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uint32_t virt;
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} mem_remapping_t;
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typedef struct opti283_t {
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uint8_t index;
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uint8_t shadow_high;
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uint8_t regs[256];
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mem_remapping_t mem_remappings[2];
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mem_mapping_t mem_mappings[2];
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} opti283_t;
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static uint8_t
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opti283_read_remapped_ram(uint32_t addr, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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return mem_read_ram((addr - dev->virt) + dev->phys, priv);
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}
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static uint16_t
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opti283_read_remapped_ramw(uint32_t addr, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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return mem_read_ramw((addr - dev->virt) + dev->phys, priv);
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}
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static uint32_t
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opti283_read_remapped_raml(uint32_t addr, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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return mem_read_raml((addr - dev->virt) + dev->phys, priv);
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}
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static void
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opti283_write_remapped_ram(uint32_t addr, uint8_t val, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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mem_write_ram((addr - dev->virt) + dev->phys, val, priv);
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}
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static void
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opti283_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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mem_write_ramw((addr - dev->virt) + dev->phys, val, priv);
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}
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static void
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opti283_write_remapped_raml(uint32_t addr, uint32_t val, void *priv)
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{
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const mem_remapping_t *dev = (mem_remapping_t *) priv;
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mem_write_raml((addr - dev->virt) + dev->phys, val, priv);
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}
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static void
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opti283_shadow_recalc(opti283_t *dev)
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{
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uint32_t base;
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uint32_t rbase;
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uint8_t sh_enable;
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uint8_t sh_mode;
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uint8_t rom;
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uint8_t sh_copy;
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shadowbios = shadowbios_write = 0;
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dev->shadow_high = 0;
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opti283_log("OPTI 283: %02X %02X %02X %02X\n", dev->regs[0x11], dev->regs[0x12], dev->regs[0x13], dev->regs[0x14]);
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if (dev->regs[0x11] & 0x80) {
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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opti283_log("OPTI 283: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n");
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shadowbios_write = 1;
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} else {
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shadowbios = 1;
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if (dev->regs[0x14] & 0x80) {
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mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_INTERNAL\n");
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shadowbios_write = 1;
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} else {
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mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_DISABLED\n");
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}
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mem_set_mem_state_both(0xf1000, 0x0f000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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opti283_log("OPTI 283: F1000-FFFFF READ_INTERNAL, WRITE_DISABLED\n");
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}
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sh_copy = dev->regs[0x11] & 0x08;
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for (uint8_t i = 0; i < 12; i++) {
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base = 0xc0000 + (i << 14);
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if (i >= 4)
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sh_enable = dev->regs[0x12] & (1 << (i - 4));
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else
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sh_enable = dev->regs[0x13] & (1 << (i + 4));
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sh_mode = dev->regs[0x11] & (1 << (i >> 2));
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rom = dev->regs[0x11] & (1 << ((i >> 2) + 4));
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opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4)));
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if (sh_enable && rom) {
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if (base >= 0x000e0000)
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shadowbios |= 1;
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if (base >= 0x000d0000)
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dev->shadow_high |= 1;
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if (sh_mode) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
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} else {
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if (base >= 0x000e0000)
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shadowbios_write |= 1;
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if (sh_copy) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff);
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}
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}
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} else {
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if (base >= 0xe0000) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED);
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opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff);
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED);
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opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
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}
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}
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}
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rbase = ((uint32_t) (dev->regs[0x13] & 0x0f)) << 20;
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if (rbase > 0) {
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dev->mem_remappings[0].virt = rbase;
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mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000);
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if (!dev->shadow_high) {
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rbase += 0x00020000;
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dev->mem_remappings[1].virt = rbase;
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mem_mapping_set_addr(&dev->mem_mappings[1], rbase, 0x00020000);
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} else
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mem_mapping_disable(&dev->mem_mappings[1]);
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} else {
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mem_mapping_disable(&dev->mem_mappings[0]);
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mem_mapping_disable(&dev->mem_mappings[1]);
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}
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flushmmucache_nopc();
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}
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static void
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opti283_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti283_t *dev = (opti283_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x24:
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opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);
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switch (dev->index) {
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case 0x10:
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dev->regs[dev->index] = val;
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break;
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case 0x14:
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reset_on_hlt = !!(val & 0x40);
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fallthrough;
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case 0x11:
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case 0x12:
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case 0x13:
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dev->regs[dev->index] = val;
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opti283_shadow_recalc(dev);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static uint8_t
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opti283_read(uint16_t addr, void *priv)
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{
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const opti283_t *dev = (opti283_t *) priv;
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uint8_t ret = 0xff;
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if (addr == 0x24)
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ret = dev->regs[dev->index];
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return ret;
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}
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static void
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opti283_close(void *priv)
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{
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opti283_t *dev = (opti283_t *) priv;
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free(dev);
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}
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static void *
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opti283_init(UNUSED(const device_t *info))
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{
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opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
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memset(dev, 0x00, sizeof(opti283_t));
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io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
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dev->regs[0x10] = 0x3f;
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dev->regs[0x11] = 0xf0;
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dev->mem_remappings[0].phys = 0x000a0000;
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dev->mem_remappings[1].phys = 0x000d0000;
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mem_mapping_add(&dev->mem_mappings[0], 0, 0x00020000,
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opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml,
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opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml,
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&ram[dev->mem_remappings[0].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[0]);
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mem_mapping_disable(&dev->mem_mappings[0]);
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mem_mapping_add(&dev->mem_mappings[1], 0, 0x00020000,
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opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml,
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opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml,
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&ram[dev->mem_remappings[1].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[1]);
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mem_mapping_disable(&dev->mem_mappings[1]);
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opti283_shadow_recalc(dev);
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return dev;
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}
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const device_t opti283_device = {
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.name = "OPTi 82C283",
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.internal_name = "opti283",
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.flags = 0,
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.local = 0,
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.init = opti283_init,
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.close = opti283_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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