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Applied upstream patches (adds IBM PS/2 M70.)

Browse Source 
Fixed two small bugs.
Moved the MRTHOR back to mainline.
Fixed a bug in the Tosh 1000.
This commit is contained in:
waltje
2018-03-13 00:34:07 -05:00
parent 18634284a6
commit 916f210d46
27 changed files with 1666 additions and 1075 deletions
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23
src/cpu/cpu.c
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@@ -8,7 +8,7 @@
*
* CPU type handler.
*
* Version: @(#)cpu.c 1.0.2 2018/03/04
* Version: @(#)cpu.c 1.0.3 2018/03/12
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* leilei,
@@ -131,7 +131,7 @@ int cpuspeed;
uint64_t cpu_CR4_mask;
int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
int cpu_prefetch_cycles, cpu_prefetch_width;
int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
int cpu_waitstates;
int cpu_cache_int_enabled, cpu_cache_ext_enabled;
int cpu_pci_speed;
@@ -260,6 +260,11 @@ void cpu_set()
isa_cycles = cpu_s->atclk_div;
if (cpu_s->rspeed <= 8000000)
cpu_rom_prefetch_cycles = cpu_mem_prefetch_cycles;
else
cpu_rom_prefetch_cycles = cpu_s->rspeed / 1000000;
if (cpu_s->pci_speed)
{
pci_nonburst_time = 4*cpu_s->rspeed / cpu_s->pci_speed;
@@ -2221,9 +2226,12 @@ void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f)
void cpu_update_waitstates()
{
cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective];
cpu_prefetch_width = cpu_16bitbus ? 2 : 4;
if (is486)
cpu_prefetch_width = 16;
else
cpu_prefetch_width = cpu_16bitbus ? 2 : 4;
if (cpu_cache_int_enabled)
{
/* Disable prefetch emulation */
@@ -2256,4 +2264,9 @@ void cpu_update_waitstates()
cpu_cycles_write = cpu_s->mem_write_cycles;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles;
}
if (is486)
cpu_prefetch_cycles *= 4;
cpu_mem_prefetch_cycles = cpu_prefetch_cycles;
if (cpu_s->rspeed <= 8000000)
cpu_rom_prefetch_cycles = cpu_mem_prefetch_cycles;
}

4
src/cpu/cpu.h
View File

@@ -8,7 +8,7 @@
*
* CPU type handler.
*
* Version: @(#)cpu.h 1.0.4 2018/03/09
* Version: @(#)cpu.h 1.0.5 2018/03/12
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* leilei,
@@ -400,7 +400,7 @@ extern x86seg _oldds;
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width;
extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
extern int cpu_waitstates;
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
extern int cpu_pci_speed;

1706
src/dma.c
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File diff suppressed because it is too large Load Diff

35
src/dma.h
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@@ -8,7 +8,7 @@
*
* Definitions for the Intel DMA controller.
*
* Version: @(#)dma.h 1.0.1 2018/02/14
* Version: @(#)dma.h 1.0.2 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -45,31 +45,24 @@
#define DMA_VERIFY 0x20000
typedef struct DMA {
uint32_t ab[4],
ac[4];
uint16_t cb[4];
int cc[4];
typedef struct {
uint32_t ab, ac;
uint16_t cb;
int cc;
int wp;
uint8_t m,
mode[4];
uint8_t page[4];
uint8_t stat,
stat_rq;
uint8_t m, mode;
uint8_t page;
uint8_t stat, stat_rq;
uint8_t command;
uint8_t request;
int size;
int xfr_command,
xfr_channel;
int byte_ptr;
int is_ps2;
uint8_t arb_level[4];
uint8_t ps2_mode[4];
} DMA;
uint8_t ps2_mode;
uint8_t arb_level;
uint16_t io_addr;
} dma_t;
extern DMA dma, dma16;
extern dma_t dma[8];
extern void dma_init(void);

7
src/floppy/fdc.c
View File

@@ -9,7 +9,7 @@
* Implementation of the NEC uPD-765 and compatible floppy disk
* controller.
*
* Version: @(#)fdc.c 1.0.2 2018/03/04
* Version: @(#)fdc.c 1.0.3 2018/03/12
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -707,6 +707,8 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc_log("Write FDC %04X %02X\n", addr, val);
cycles -= ISA_CYCLES(8);
switch (addr&7) {
case 0:
return;
@@ -1164,6 +1166,9 @@ fdc_read(uint16_t addr, void *priv)
fdc_t *fdc = (fdc_t *) priv;
uint8_t ret;
int drive;
cycles -= ISA_CYCLES(8);
switch (addr&7) {
case 0: /* STA */
ret = 0xff;

13
src/floppy/fdd.c
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@@ -8,7 +8,7 @@
*
* Implementation of the floppy drive emulation.
*
* Version: @(#)fdd.c 1.0.2 2018/03/08
* Version: @(#)fdd.c 1.0.3 2018/03/12
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -541,16 +541,7 @@ double fdd_real_period(int drive)
return (32.0 * dusec);
}
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
if (romset == ROM_MRTHOR)
{
return (ddbp * dusec) / 4.0;
}
else
#endif
{
return (ddbp * dusec);
}
return (ddbp * dusec);
}
void fdd_poll(int drive)

25
src/keyboard_at.c
View File

@@ -8,7 +8,7 @@
*
* Intel 8042 (AT keyboard controller) emulation.
*
* Version: @(#)keyboard_at.c 1.0.3 2018/03/09
* Version: @(#)keyboard_at.c 1.0.4 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -108,7 +108,7 @@ typedef struct {
uint8_t status;
uint8_t mem[0x100];
uint8_t out;
int out_new;
int out_new, out_delayed;
uint8_t secr_phase;
uint8_t mem_addr;
@@ -662,7 +662,7 @@ kbd_poll(void *priv)
kbdlog("ATkbd: want keyboard data\n");
if (kbd->mem[0] & 0x01)
picint(2);
kbd->out = kbd->out_new;
kbd->out = kbd->out_new & 0xff;
kbd->out_new = -1;
kbd->status |= STAT_OFULL;
kbd->status &= ~STAT_IFULL;
@@ -673,12 +673,21 @@ kbd_poll(void *priv)
if (kbd->out_new == -1 && !(kbd->status & STAT_OFULL) &&
key_ctrl_queue_start != key_ctrl_queue_end) {
kbd->out_new = key_ctrl_queue[key_ctrl_queue_start];
kbd->out_new = key_ctrl_queue[key_ctrl_queue_start] | 0x200;
key_ctrl_queue_start = (key_ctrl_queue_start + 1) & 0xf;
} else if (!(kbd->status & STAT_OFULL) && kbd->out_new == -1 &&
kbd->out_delayed != -1) {
kbd->out_new = kbd->out_delayed;
kbd->out_delayed = -1;
} else if (!(kbd->status & STAT_OFULL) && kbd->out_new == -1 &&
!(kbd->mem[0] & 0x10) && kbd->out_delayed != -1) {
kbd->out_new = kbd->out_delayed;
kbd->out_delayed = -1;
} else if (!(kbd->status & STAT_OFULL) && kbd->out_new == -1/* && !(kbd->mem[0] & 0x20)*/ &&
(mouse_queue_start != mouse_queue_end)) {
kbd->out_new = mouse_queue[mouse_queue_start] | 0x100;
mouse_queue_start = (mouse_queue_start + 1) & 0xf;
kbd->out_new = key_ctrl_queue[key_ctrl_queue_start];
} else if (!(kbd->status&STAT_OFULL) && kbd->out_new == -1 &&
!(kbd->mem[0]&0x10) && (key_queue_start != key_queue_end)) {
kbd->out_new = key_queue[key_queue_start];
@@ -692,6 +701,11 @@ kbd_adddata(uint8_t val)
{
key_ctrl_queue[key_ctrl_queue_end] = val;
key_ctrl_queue_end = (key_ctrl_queue_end + 1) & 0xf;
if (!(CurrentKbd->out_new & 0x300)) {
CurrentKbd->out_delayed = CurrentKbd->out_new;
CurrentKbd->out_new = -1;
}
}
@@ -962,7 +976,8 @@ kbd_cmd_write(atkbd_t *kbd, uint8_t val)
kbd->wantirq = 0;
/* PS/2 type 2 keyboard controllers always force the XLAT bit to 0. */
if ((kbd->flags & KBC_TYPE_MASK) == KBC_TYPE_PS2_2) {
if (((kbd->flags & KBC_VEN_MASK) == KBC_VEN_AMI) ||
((kbd->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1)) {
val &= ~CCB_TRANSLATE;
kbd->mem[0] &= ~CCB_TRANSLATE;
}

371
src/machine/m_ps2_mca.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of MCA-based PS/2 machines.
*
* Version: @(#)m_ps2_mca.c 1.0.1 2018/02/14
* Version: @(#)m_ps2_mca.c 1.0.2 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -72,26 +72,116 @@ static struct
uint8_t setup;
uint8_t sys_ctrl_port_a;
uint8_t subaddr_lo, subaddr_hi;
uint8_t memory_bank[8];
uint8_t io_id;
mem_mapping_t shadow_mapping;
mem_mapping_t expansion_mapping;
mem_mapping_t cache_mapping;
uint8_t (*planar_read)(uint16_t port);
void (*planar_write)(uint16_t port, uint8_t val);
uint8_t mem_regs[3];
uint32_t split_addr, split_size;
uint8_t mem_pos_regs[8];
uint8_t mem_2mb_pos_regs[8];
int pending_cache_miss;
} ps2;
/*The model 70 type 3/4 BIOS performs cache testing. Since we don't have any
proper cache emulation, it's faked a bit here.
Port E2 is used for cache diagnostics. Bit 7 seems to be set on a cache miss,
toggling bit 2 seems to clear this. The BIOS performs at least the following
tests :
- Disable RAM, access low 64kb (386) / 8kb (486), execute code from cache to
access low memory and verify that there are no cache misses.
- Write to low memory using DMA, read low memory and verify that all accesses
cause cache misses.
- Read low memory, verify that first access is cache miss. Read again and
verify that second access is cache hit.
These tests are also performed on the 486 model 70, despite there being no
external cache on this system. Port E2 seems to control the internal cache on
these systems. Presumably this port is connected to KEN#/FLUSH# on the 486.
This behaviour is required to pass the timer interrupt test on the 486 version
- the BIOS uses a fixed length loop that will terminate too early on a 486/25
if it executes from internal cache.
To handle this, 86Box uses some basic heuristics :
- If cache is enabled but RAM is disabled, accesses to low memory go directly
to cache memory.
- Reads to cache addresses not 'valid' will set the cache miss flag, and mark
that line as valid.
- Cache flushes will clear the valid array.
- DMA via the undocumented PS/2 command 0xb will clear the valid array.
- Disabling the cache will clear the valid array.
- Disabling the cache will also mark shadowed ROM areas as using ROM timings.
This works around the timing loop mentioned above.
*/
static uint8_t ps2_cache[65536];
static int ps2_cache_valid[65536/8];
static uint8_t ps2_read_cache_ram(uint32_t addr, void *priv)
{
// pclog("ps2_read_cache_ram: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
if (!ps2_cache_valid[addr >> 3])
{
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
}
else
ps2.pending_cache_miss = 0;
return ps2_cache[addr];
}
static uint16_t ps2_read_cache_ramw(uint32_t addr, void *priv)
{
// pclog("ps2_read_cache_ramw: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
if (!ps2_cache_valid[addr >> 3])
{
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
}
else
ps2.pending_cache_miss = 0;
return *(uint16_t *)&ps2_cache[addr];
}
static uint32_t ps2_read_cache_raml(uint32_t addr, void *priv)
{
// pclog("ps2_read_cache_raml: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
if (!ps2_cache_valid[addr >> 3])
{
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
}
else
ps2.pending_cache_miss = 0;
return *(uint32_t *)&ps2_cache[addr];
}
static void ps2_write_cache_ram(uint32_t addr, uint8_t val, void *priv)
{
// pclog("ps2_write_cache_ram: addr=%08x val=%02x %04x:%04x %i\n", addr, val, CS,cpu_state.pc, ins);
ps2_cache[addr] = val;
}
void ps2_cache_clean(void)
{
memset(ps2_cache_valid, 0, sizeof(ps2_cache_valid));
}
static uint8_t ps2_read_shadow_ram(uint32_t addr, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
@@ -177,6 +267,30 @@ static uint8_t model_55sx_read(uint16_t port)
return 0xff;
}
static uint8_t model_70_type3_read(uint16_t port)
{
switch (port)
{
case 0x100:
return 0xff;
case 0x101:
return 0xf9;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
}
return 0xff;
}
static uint8_t model_80_read(uint16_t port)
{
switch (port)
@@ -334,6 +448,56 @@ static void model_55sx_write(uint16_t port, uint8_t val)
}
}
static void model_70_type3_write(uint16_t port, uint8_t val)
{
switch (port)
{
case 0x100:
break;
case 0x101:
break;
case 0x102:
lpt1_remove();
serial_remove(1);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps2.option[0] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
}
}
static void model_80_write(uint16_t port, uint8_t val)
{
switch (port)
@@ -775,6 +939,169 @@ static void mem_encoding_write(uint16_t addr, uint8_t val, void *p)
mem_encoding_update();
}
static uint8_t mem_encoding_read_cached(uint16_t addr, void *p)
{
switch (addr)
{
case 0xe0:
return ps2.mem_regs[0];
case 0xe1:
return ps2.mem_regs[1];
case 0xe2:
return ps2.mem_regs[2];
}
return 0xff;
}
static void mem_encoding_write_cached(uint16_t addr, uint8_t val, void *p)
{
uint8_t old;
switch (addr)
{
case 0xe0:
ps2.mem_regs[0] = val;
break;
case 0xe1:
ps2.mem_regs[1] = val;
break;
case 0xe2:
old = ps2.mem_regs[2];
ps2.mem_regs[2] = (ps2.mem_regs[2] & 0x80) | (val & ~0x88);
if (val & 2)
{
// pclog("Clear latch - %i\n", ps2.pending_cache_miss);
if (ps2.pending_cache_miss)
ps2.mem_regs[2] |= 0x80;
else
ps2.mem_regs[2] &= ~0x80;
ps2.pending_cache_miss = 0;
}
if ((val & 0x21) == 0x20 && (old & 0x21) != 0x20)
ps2.pending_cache_miss = 1;
if ((val & 0x21) == 0x01 && (old & 0x21) != 0x01)
ps2_cache_clean();
if (val & 0x01)
ram_mid_mapping.flags |= MEM_MAPPING_ROM;
else
ram_mid_mapping.flags &= ~MEM_MAPPING_ROM;
break;
}
// pclog("mem_encoding_write: addr=%02x val=%02x %04x:%04x %02x %02x\n", addr, val, CS,cpu_state.pc, ps2.mem_regs[1],ps2.mem_regs[2]);
mem_encoding_update();
if ((ps2.mem_regs[1] & 0x10) && (ps2.mem_regs[2] & 0x21) == 0x20)
{
mem_mapping_disable(&ram_low_mapping);
mem_mapping_enable(&ps2.cache_mapping);
flushmmucache();
}
else
{
mem_mapping_disable(&ps2.cache_mapping);
mem_mapping_enable(&ram_low_mapping);
flushmmucache();
}
}
static void ps2_mca_board_model_70_type34_init(int is_type4)
{
ps2_mca_board_common_init();
mem_remap_top_256k();
ps2.split_addr = mem_size * 1024;
mca_init(4);
ps2.planar_read = model_70_type3_read;
ps2.planar_write = model_70_type3_write;
device_add(&ps2_nvr_device);
io_sethandler(0x00e0, 0x0003, mem_encoding_read_cached, NULL, NULL, mem_encoding_write_cached, NULL, NULL, NULL);
ps2.mem_regs[1] = 2;
switch (mem_size/1024)
{
case 2:
ps2.option[1] = 0xa6;
ps2.option[2] = 0x01;
break;
case 4:
ps2.option[1] = 0xaa;
ps2.option[2] = 0x01;
break;
case 6:
ps2.option[1] = 0xca;
ps2.option[2] = 0x01;
break;
case 8:
default:
ps2.option[1] = 0xca;
ps2.option[2] = 0x02;
break;
}
if (is_type4)
ps2.option[2] |= 0x04; /*486 CPU*/
mem_mapping_add(&ps2.cache_mapping,
0,
is_type4 ? (8 * 1024) : (64 * 1024),
ps2_read_cache_ram,
ps2_read_cache_ramw,
ps2_read_cache_raml,
ps2_write_cache_ram,
NULL,
NULL,
ps2_cache,
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.cache_mapping);
if (mem_size > 8192)
{
/* Only 8 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x700000);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 10:
ps2.mem_pos_regs[4] = 0xfe;
break;
case 12:
ps2.mem_pos_regs[4] = 0xfa;
break;
case 14:
ps2.mem_pos_regs[4] = 0xea;
break;
case 16:
ps2.mem_pos_regs[4] = 0xaa;
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x800000,
(mem_size - 8192)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x800000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
device_add(&ps1vga_device);
}
static void ps2_mca_board_model_80_type2_init(int is486)
{
ps2_mca_board_common_init();
@@ -915,6 +1242,23 @@ machine_ps2_model_55sx_init(machine_t *model)
}
void
machine_ps2_model_70_type3_init(machine_t *model)
{
machine_ps2_common_init(model);
ps2_mca_board_model_70_type34_init(0);
}
void
machine_ps2_model_70_type4_init(machine_t *model)
{
machine_ps2_common_init(model);
ps2_mca_board_model_70_type34_init(1);
}
void
machine_ps2_model_80_init(machine_t *model)
{
@@ -922,14 +1266,3 @@ machine_ps2_model_80_init(machine_t *model)
ps2_mca_board_model_80_type2_init(0);
}
#ifdef WALTJE
void
machine_ps2_model_80_486_init(machine_t *model)
{
machine_ps2_common_init(model);
ps2_mca_board_model_80_type2_init(1);
}
#endif

6
src/machine/m_xt_t1000.c
View File

@@ -51,7 +51,7 @@
* NOTE: Still need to figure out a way to load/save ConfigSys and
* HardRAM stuff. Needs to be linked in to the NVR code.
*
* Version: @(#)m_xt_t1000.c 1.0.2 2018/03/11
* Version: @(#)m_xt_t1000.c 1.0.3 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -192,8 +192,8 @@ tc8521_time_set(uint8_t *regs, struct tm *tm)
regs[TC8521_WEEKDAY] = tm->tm_wday;
regs[TC8521_DAY1] = (tm->tm_mday % 10);
regs[TC8521_DAY10] = (tm->tm_mday / 10);
regs[TC8521_MONTH1] = ((tm->tm_mon + 1) / 10);
regs[TC8521_MONTH10] = ((tm->tm_mon + 1) % 10);
regs[TC8521_MONTH1] = ((tm->tm_mon + 1) % 10);
regs[TC8521_MONTH10] = ((tm->tm_mon + 1) / 10);
regs[TC8521_YEAR1] = ((tm->tm_year - 80) % 10);
regs[TC8521_YEAR10] = (((tm->tm_year - 80) % 100) / 10);
}

9
src/machine/machine.h
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.h 1.0.8 2018/03/11
* Version: @(#)machine.h 1.0.9 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -137,6 +137,9 @@ enum {
#endif
ROM_IBMPS1_2133,
ROM_IBMPS2_M70_TYPE3,
ROM_IBMPS2_M70_TYPE4,
ROM_R418, /* Rise Computer R418/SiS 496/497/Award/SMC FDC37C665 */
ROM_REVENGE, /* Intel Premiere/PCI I/430LX/AMI/SMC FDC37C665 */
@@ -153,9 +156,7 @@ enum {
ROM_PRESIDENT, /* President Award 430FX PCI/430FX/Award/Unknown SIO */
ROM_THOR, /* Intel Advanced_ATX/430FX/AMI/NS PC87306 */
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
ROM_MRTHOR, /* Intel Advanced_ATX/430FX/MR.BIOS/NS PC87306 */
#endif
ROM_ACERM3A, /* Acer M3A/430HX/Acer/SMC FDC37C932FR */
ROM_ACERV35N, /* Acer V35N/430HX/Acer/SMC FDC37C932FR */
@@ -320,6 +321,8 @@ extern void machine_ps1_m2133_init(machine_t *);
extern void machine_ps2_m30_286_init(machine_t *);
extern void machine_ps2_model_50_init(machine_t *);
extern void machine_ps2_model_55sx_init(machine_t *);
extern void machine_ps2_model_70_type3_init(machine_t *);
extern void machine_ps2_model_70_type4_init(machine_t *);
extern void machine_ps2_model_80_init(machine_t *);
extern void machine_amstrad_init(machine_t *);

14
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.7 2018/03/11
* Version: @(#)machine_table.c 1.0.8 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -65,12 +65,12 @@ machine_t machines[] = {
{ "[8088] Schneider EuroPC", ROM_EUROPC, "europc", L"schneider/europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 16, machine_europc_init, NULL, NULL },
{ "[8088] Tandy 1000", ROM_TANDY, "tandy", L"tandy/tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 128, 640, 128, 0, machine_tandy1k_init, tandy1k_get_device, NULL },
{ "[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", L"tandy/tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 256, 640, 128, 0, machine_tandy1k_init, tandy1k_hx_get_device, NULL },
{ "[8088] Toshiba 1000", ROM_T1000, "t1000", L"toshiba/t1000", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 0, machine_xt_t1000_init, t1000_get_device, NULL },
{ "[8088] Toshiba 1000", ROM_T1000, "t1000", L"toshiba/t1000", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 0, machine_xt_t1000_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", L"vtech/ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 512, 512, 256, 0, machine_xt_laserxt_init, NULL, NULL },
#endif
{ "[8088] Xi8088", ROM_XI8088, "xi8088", L"generic/xi8088", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_PS2, 64, 1024, 128, 128, machine_xt_xi8088_init, xi8088_get_device, nvr_at_close },
{ "[8088] Xi8088", ROM_XI8088, "xi8088", L"generic/xi8088", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA /*| MACDHINE_AT*/ | MACHINE_PS2, 64, 1024, 128, 128, machine_xt_xi8088_init, NULL, nvr_at_close },
{ "[8086] Amstrad PC1512", ROM_PC1512, "pc1512", L"amstrad/pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, machine_amstrad_init, NULL, nvr_at_close },
{ "[8086] Amstrad PC1640", ROM_PC1640, "pc1640", L"amstrad/pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, machine_amstrad_init, NULL, nvr_at_close },
{ "[8086] Amstrad PC2086", ROM_PC2086, "pc2086", L"amstrad/pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, machine_amstrad_init, NULL, nvr_at_close },
@@ -78,7 +78,7 @@ machine_t machines[] = {
{ "[8086] Amstrad PC20(0)", ROM_PC200, "pc200", L"amstrad/pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, machine_amstrad_init, NULL, nvr_at_close },
{ "[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", L"olivetti/olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL, NULL },
{ "[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", L"tandy/tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, machine_tandy1k_init, NULL, NULL },
{ "[8086] Toshiba 1200", ROM_T1200, "t1200", L"toshiba/t1200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 0, machine_xt_t1200_init, t1200_get_device, NULL },
{ "[8086] Toshiba 1200", ROM_T1200, "t1200", L"toshiba/t1200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 0, machine_xt_t1200_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8086] VTech Laser XT3", ROM_LXT3, "lxt3", L"vtech/lxt3", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 512, 256, 0, machine_xt_laserxt_init, NULL, NULL },
#endif
@@ -120,6 +120,7 @@ machine_t machines[] = {
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portableiii386", L"compaq/deskpro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, machine_at_compaq_init, NULL, nvr_at_close },
#endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibmps2_m70_type3", L"ibm/ibmps2_m70_3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL, nvr_at_close },
{ "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibmps2_m80", L"ibm/ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 12, 1, 64, machine_ps2_model_80_init, NULL, nvr_at_close },
{ "[486 ISA] AMI 486 clone", ROM_AMI486, "ami486", L"generic/ami/ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, nvr_at_close },
@@ -127,6 +128,7 @@ machine_t machines[] = {
{ "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award486", L"generic/award/award495", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_init, NULL, nvr_at_close },
{ "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", L"dtk/dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_dtk486_init, NULL, nvr_at_close },
{ "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", L"ibm/ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 128, machine_ps1_m2133_init, NULL, nvr_at_close },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibmps2_m70_type4", L"ibm/ibmps2_m70_4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 64, 2, 63, machine_ps2_model_70_type4_init, NULL, nvr_at_close },
{ "[486 PCI] Rise Computer R418", ROM_R418, "r418", L"rise/r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_r418_init, NULL, nvr_at_close },
@@ -146,9 +148,7 @@ machine_t machines[] = {
{ "[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT, "president", L"president/president", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, machine_at_president_init, NULL, nvr_at_close },
{ "[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", L"intel/thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, nvr_at_close },
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
{ "[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", L"intel/mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, nvr_at_close },
#endif
{ "[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", L"acer/acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerm3a_init, NULL, nvr_at_close },
{ "[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", L"acer/acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerv35n_init, NULL, nvr_at_close },
@@ -169,9 +169,7 @@ machine_t machines[] = {
{ "[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT, "president", L"president/president", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, machine_at_president_init, NULL, nvr_at_close },
{ "[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", L"intel/thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, nvr_at_close },
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
{ "[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", L"intel/mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, nvr_at_close },
#endif
{ "[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", L"acer/acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerm3a_init, NULL, nvr_at_close },
{ "[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", L"acer/acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerv35n_init, NULL, nvr_at_close },

4
src/mca.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the MCA bus handlers.
*
* Version: @(#)mca.h 1.0.1 2018/02/14
* Version: @(#)mca.h 1.0.2 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -46,5 +46,7 @@ extern void mca_set_index(int index);
extern uint8_t mca_read(uint16_t port);
extern void mca_write(uint16_t port, uint8_t val);
extern void ps2_cache_clean(void);
#endif /*EMU_MCA_H*/

46
src/mem.c
View File

@@ -8,7 +8,7 @@
*
* Memory handling and MMU.
*
* Version: @(#)mem.c 1.0.3 2018/03/05
* Version: @(#)mem.c 1.0.4 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -423,15 +423,13 @@ uint8_t *getpccache(uint32_t a)
}
a&=rammask;
if (isram[a>>16])
{
if ((a >> 16) != 0xF || shadowbios)
addreadlookup(a2, a);
return &ram[(uintptr_t)(a & 0xFFFFF000) - (uintptr_t)(a2 & ~0xFFF)];
}
if (_mem_exec[a >> 14])
{
if (_mem_mapping_r[a >> 14]->flags & MEM_MAPPING_ROM)
cpu_prefetch_cycles = cpu_rom_prefetch_cycles;
else
cpu_prefetch_cycles = cpu_mem_prefetch_cycles;
return &_mem_exec[a >> 14][(uintptr_t)(a & 0x3000) - (uintptr_t)(a2 & ~0xFFF)];
}
@@ -1316,24 +1314,24 @@ void mem_add_bios()
{
if (AT || (romset == ROM_XI8088 && xi8088_bios_128kb()))
{
mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
}
mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[0], (AT && cpu_16bitbus) ? 0xfe0000 : 0xfffe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, 0, 0);
mem_mapping_add(&bios_high_mapping[1], (AT && cpu_16bitbus) ? 0xfe4000 : 0xfffe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[2], (AT && cpu_16bitbus) ? 0xfe8000 : 0xfffe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[3], (AT && cpu_16bitbus) ? 0xfec000 : 0xfffec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[4], (AT && cpu_16bitbus) ? 0xff0000 : 0xffff0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[5], (AT && cpu_16bitbus) ? 0xff4000 : 0xffff4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[6], (AT && cpu_16bitbus) ? 0xff8000 : 0xffff8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[7], (AT && cpu_16bitbus) ? 0xffc000 : 0xffffc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[0], (AT && cpu_16bitbus) ? 0xfe0000 : 0xfffe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[1], (AT && cpu_16bitbus) ? 0xfe4000 : 0xfffe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[2], (AT && cpu_16bitbus) ? 0xfe8000 : 0xfffe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[3], (AT && cpu_16bitbus) ? 0xfec000 : 0xfffec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[4], (AT && cpu_16bitbus) ? 0xff0000 : 0xffff0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[5], (AT && cpu_16bitbus) ? 0xff4000 : 0xffff4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[6], (AT && cpu_16bitbus) ? 0xff8000 : 0xffff8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), MEM_MAPPING_ROM, 0);
mem_mapping_add(&bios_high_mapping[7], (AT && cpu_16bitbus) ? 0xffc000 : 0xffffc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), MEM_MAPPING_ROM, 0);
}
int mem_a20_key = 0, mem_a20_alt = 0;

4
src/mem.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the memory interface.
*
* Version: @(#)mem.h 1.0.1 2018/02/14
* Version: @(#)mem.h 1.0.2 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -101,6 +101,8 @@ typedef struct mem_mapping_t
#define MEM_MAPPING_EXTERNAL 1
/*Only present on internal bus (RAM)*/
#define MEM_MAPPING_INTERNAL 2
/*Executing from ROM may involve additional wait states*/
#define MEM_MAPPING_ROM 4
extern uint8_t *ram,*rom;
extern uint8_t romext[32768];

6
src/nvr.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the generic NVRAM/CMOS driver.
*
* Version: @(#)nvr.h 1.0.2 2018/03/11
* Version: @(#)nvr.h 1.0.3 2018/03/12
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
@@ -59,8 +59,8 @@
/* Define a generic RTC/NVRAM device. */
typedef struct _nvr_ {
uint8_t regs[NVR_MAXSIZE]; /* these are the registers */
wchar_t *fn;
/* pathname of image file */
wchar_t *fn; /* pathname of image file */
uint16_t size; /* device configuration */
int8_t irq;
int8_t upd_stat, /* FIXME: move to private struct */

18
src/nvr_ps2.c
View File

@@ -8,7 +8,7 @@
*
* Handling of the PS/2 series CMOS devices.
*
* Version: @(#)nvr_ps2.c 1.0.3 2018/03/10
* Version: @(#)nvr_ps2.c 1.0.4 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -113,6 +113,14 @@ ps2_nvr_init(device_t *info)
ps2_nvr_read,NULL,NULL, ps2_nvr_write,NULL,NULL, nvr);
switch (romset) {
case ROM_IBMPS2_M70_TYPE3:
f = nvr_fopen(L"ibmps2_m70_type3_sec.nvr", L"rb");
break;
case ROM_IBMPS2_M70_TYPE4:
f = nvr_fopen(L"ibmps2_m70_type4_sec.nvr", L"rb");
break;
case ROM_IBMPS2_M80:
f = nvr_fopen(L"ibmps2_m80_sec.nvr", L"rb");
break;
@@ -135,6 +143,14 @@ ps2_nvr_close(void *priv)
FILE *f = NULL;
switch (romset) {
case ROM_IBMPS2_M70_TYPE3:
f = nvr_fopen(L"ibmps2_m70_type3_sec.nvr", L"wb");
break;
case ROM_IBMPS2_M70_TYPE4:
f = nvr_fopen(L"ibmps2_m70_type4_sec.nvr", L"wb");
break;
case ROM_IBMPS2_M80:
f = nvr_fopen(L"ibmps2_m80_sec.nvr", L"wb");
break;

6
src/rom.c
View File

@@ -12,7 +12,7 @@
* - pc2386 video BIOS is underdumped (16k instead of 24k)
* - c386sx16 BIOS fails checksum
*
* Version: @(#)rom.c 1.0.7 2018/03/09
* Version: @(#)rom.c 1.0.8 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -260,7 +260,7 @@ rom_init(rom_t *rom, wchar_t *fn, uint32_t addr, int sz, int mask, int off, uint
addr, sz,
rom_read, rom_readw, rom_readl,
mem_write_null, mem_write_nullw, mem_write_nulll,
rom->rom, flags, rom);
rom->rom, flags | MEM_MAPPING_ROM, rom);
return(0);
}
@@ -287,7 +287,7 @@ rom_init_interleaved(rom_t *rom, wchar_t *fnl, wchar_t *fnh, uint32_t addr, int
addr, sz,
rom_read, rom_readw, rom_readl,
mem_write_null, mem_write_nullw, mem_write_nulll,
rom->rom, flags, rom);
rom->rom, flags | MEM_MAPPING_ROM, rom);
return(0);
}

81
src/scsi/scsi_ncr53c810.c
View File

@@ -10,7 +10,7 @@
* NCR and later Symbios and LSI. This controller was designed
* for the PCI bus.
*
* Version: @(#)scsi_ncr53c810.c 1.0.3 2018/03/08
* Version: @(#)scsi_ncr53c810.c 1.0.4 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -675,12 +675,13 @@ ncr53c810_add_msg_byte(ncr53c810_t *dev, uint8_t data)
}
static void
static int
ncr53c810_do_command(ncr53c810_t *dev, uint8_t id)
{
scsi_device_t *sd;
uint8_t buf[12];
double period;
int64_t p;
memset(buf, 0, 12);
DMAPageRead(dev->dnad, buf, MIN(12, dev->dbc));
@@ -695,9 +696,9 @@ ncr53c810_do_command(ncr53c810_t *dev, uint8_t id)
if (((id == 0xff) || !scsi_device_present(id, dev->current_lun))) {
ncr53c810_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: Bad Selection\n", id, dev->current_lun, buf[0]);
ncr53c810_bad_selection(dev, id);
return;
return(0);
}
dev->current = (ncr53c810_request*)malloc(sizeof(ncr53c810_request));
dev->current->tag = id;
@@ -722,21 +723,27 @@ ncr53c810_do_command(ncr53c810_t *dev, uint8_t id)
if ((sd->Phase == SCSI_PHASE_DATA_IN) && (sd->BufferLength > 0)) {
ncr53c810_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: PHASE_DI\n", id, dev->current_lun, buf[0]);
ncr53c810_set_phase(dev, PHASE_DI);
dev->timer_period = scsi_device_get_callback(dev->current->tag, dev->current_lun);
if (dev->timer_period <= 0LL) {
period = ((double) sd->BufferLength) * 0.2 * ((double) TIMER_USEC); /* Fast SCSI: 10000000 bytes per second */
dev->timer_period = (int64_t) period;
}
p = scsi_device_get_callback(dev->current->tag, dev->current_lun);
if (p <= 0LL) {
period = ((double) sd->BufferLength) * 0.1 * ((double) TIMER_USEC); /* Fast SCSI: 10000000 bytes per second */
dev->timer_period += (int64_t) period;
} else
dev->timer_period += p;
return(1);
} else if ((sd->Phase == SCSI_PHASE_DATA_OUT) && (sd->BufferLength > 0)) {
ncr53c810_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: PHASE_DO\n", id, dev->current_lun, buf[0]);
ncr53c810_set_phase(dev, PHASE_DO);
dev->timer_period = scsi_device_get_callback(dev->current->tag, dev->current_lun);
if (dev->timer_period <= 0LL) {
period = ((double) sd->BufferLength) * 0.2 * ((double) TIMER_USEC); /* Fast SCSI: 10000000 bytes per second */
dev->timer_period = (int64_t) period;
}
} else
ncr53c810_command_complete(dev, sd->Status);
p = scsi_device_get_callback(dev->current->tag, dev->current_lun);
if (p <= 0LL) {
period = ((double) sd->BufferLength) * 0.1 * ((double) TIMER_USEC); /* Fast SCSI: 10000000 bytes per second */
dev->timer_period += (int64_t) period;
} else
dev->timer_period += p;
return(1);
} else {
ncr53c810_command_complete(dev, sd->Status);
return(0);
}
}
@@ -952,7 +959,7 @@ static void
ncr53c810_process_script(ncr53c810_t *dev)
{
uint32_t insn, addr, id, buf[2], dest;
int opcode, insn_processed = 0, reg, operator, cond, jmp, n, i;
int opcode, insn_processed = 0, reg, operator, cond, jmp, n, i, c;
int32_t offset;
uint8_t op0, op1, data8, mask, data[7], *pp;
@@ -964,7 +971,11 @@ again:
/* If we receive an empty opcode increment the DSP by 4 bytes
instead of 8 and execute the next opcode at that location */
dev->dsp += 4;
goto again;
dev->timer_period += (10LL * TIMER_USEC);
if (insn_processed < 100)
goto again;
else
return;
}
addr = read_dword(dev, dev->dsp + 4);
ncr53c810_log("SCRIPTS dsp=%08x opcode %08x arg %08x\n", dev->dsp, insn, addr);
@@ -976,9 +987,8 @@ again:
case 0: /* Block move. */
ncr53c810_log("00: Block move\n");
if (dev->sist1 & NCR_SIST1_STO) {
ncr53c810_log("Delayed select timeout\n");
ncr53c810_log("Delayed select timeout\n");
dev->sstop = 1;
dev->timer_period = dev->timer_enabled = 0;
break;
}
ncr53c810_log("Block Move DBC=%d\n", dev->dbc);
@@ -1023,9 +1033,18 @@ again:
break;
case PHASE_CMD:
ncr53c810_log("Command Phase\n");
ncr53c810_do_command(dev, dev->sdid);
c = ncr53c810_do_command(dev, dev->sdid);
if (!c || dev->sstop || dev->waiting || ((dev->sstat1 & 0x7) == PHASE_ST))
break;
dev->dfifo = dev->dbc & 0xff;
dev->ctest5 = (dev->ctest5 & 0xfc) | ((dev->dbc >> 8) & 3);
dev->timer_period += (40LL * TIMER_USEC);
if (dev->dcntl & NCR_DCNTL_SSM)
ncr53c810_script_dma_interrupt(dev, NCR_DSTAT_SSI);
return;
case PHASE_ST:
ncr53c810_log("Status Phase\n");
@@ -1198,7 +1217,6 @@ again:
if (dev->sist1 & NCR_SIST1_STO) {
ncr53c810_log("Delayed select timeout\n");
dev->sstop = 1;
dev->timer_period = dev->timer_enabled = 0;
break;
}
cond = jmp = (insn & (1 << 19)) != 0;
@@ -1290,6 +1308,8 @@ again:
ncr53c810_log("%02X: Unknown command\n", (uint8_t) (insn >> 30));
}
dev->timer_period += (40LL * TIMER_USEC);
ncr53c810_log("instructions processed %i\n", insn_processed);
if (insn_processed > 10000 && !dev->waiting) {
/* Some windows drivers make the device spin waiting for a memory
@@ -1325,7 +1345,8 @@ again:
static void
ncr53c810_execute_script(ncr53c810_t *dev)
{
dev->timer_period = 10LL * TIMER_USEC;
dev->sstop = 0;
dev->timer_period = 40LL * TIMER_USEC;
dev->timer_enabled = 1;
}
@@ -1336,18 +1357,18 @@ ncr53c810_callback(void *p)
ncr53c810_t *dev = (ncr53c810_t *) p;
dev->timer_period = 0;
if (!dev->waiting)
ncr53c810_process_script(dev);
if (!dev->sstop) {
if (dev->waiting)
dev->timer_period = 40LL * TIMER_USEC;
else
ncr53c810_process_script(dev);
}
if (dev->sstop) {
dev->timer_period = 0;
dev->timer_enabled = 0;
return;
dev->timer_period = 0;
} else
dev->timer_enabled = 1;
if (dev->timer_period == 0)
dev->timer_period = 50LL * TIMER_USEC;
}

3
src/scsi/scsi_x54x.c
View File

@@ -12,7 +12,7 @@
*
* These controllers were designed for various buses.
*
* Version: @(#)scsi_x54x.c 1.0.6 2018/03/08
* Version: @(#)scsi_x54x.c 1.0.7 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -1083,6 +1083,7 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
/* Fetch data from the Command Control Block. */
DMAPageRead(CCBPointer, (uint8_t *)&req->CmdBlock, sizeof(CCB32));
x54x_add_to_period(sizeof(CCB32));
req->Is24bit = dev->Mbx24bit;
req->CCBPointer = CCBPointer;

75
src/video/vid_ati28800.c
View File

@@ -8,7 +8,7 @@
*
* ATI 28800 emulation (VGA Charger and Korean VGA)
*
* Version: @(#)vid_ati28800.c 1.0.4 2018/03/05
* Version: @(#)vid_ati28800.c 1.0.5 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -89,8 +89,7 @@ static int in_get_korean_font_kind_set;
static int get_korean_font_enabled;
static int get_korean_font_index;
static uint16_t get_korean_font_base;
extern int dbcs_mode_enabled;
int ksc5601_mode_enabled;
static void ati28800_out(uint16_t addr, uint8_t val, void *p)
@@ -129,7 +128,12 @@ static void ati28800_out(uint16_t addr, uint8_t val, void *p)
break;
case 0xb6:
if((old ^ val) & 0x10) svga_recalctimings(svga);
break;
break;
case 0xb8:
if((old ^ val) & 0x40) svga_recalctimings(svga);
break;
case 0xb9:
if((old ^ val) & 2) svga_recalctimings(svga);
}
break;
@@ -170,7 +174,7 @@ static void ati28800k_out(uint16_t addr, uint8_t val, void *p)
case 0x1CF:
if(ati28800->index == 0xBF && ((ati28800->regs[0xBF] ^ val) & 0x20))
{
dbcs_mode_enabled = val & 0x20;
ksc5601_mode_enabled = val & 0x20;
svga_recalctimings(svga);
}
@@ -312,6 +316,27 @@ static void ati28800_recalctimings(svga_t *svga)
{
ati28800_t *ati28800 = (ati28800_t *)svga->p;
switch(((ati28800->regs[0xbe] & 0x10) >> 1) | ((ati28800->regs[0xb9] & 2) << 1) | ((svga->miscout & 0x0C) >> 2))
{
case 0x00: svga->clock = cpuclock / 42954000.0; break;
case 0x01: svga->clock = cpuclock / 48771000.0; break;
case 0x03: svga->clock = cpuclock / 36000000.0; break;
case 0x04: svga->clock = cpuclock / 50350000.0; break;
case 0x05: svga->clock = cpuclock / 56640000.0; break;
case 0x07: svga->clock = cpuclock / 44900000.0; break;
case 0x08: svga->clock = cpuclock / 30240000.0; break;
case 0x09: svga->clock = cpuclock / 32000000.0; break;
case 0x0A: svga->clock = cpuclock / 37500000.0; break;
case 0x0B: svga->clock = cpuclock / 39000000.0; break;
case 0x0C: svga->clock = cpuclock / 40000000.0; break;
case 0x0D: svga->clock = cpuclock / 56644000.0; break;
case 0x0E: svga->clock = cpuclock / 75000000.0; break;
case 0x0F: svga->clock = cpuclock / 65000000.0; break;
default: break;
}
if(ati28800->regs[0xb8] & 0x40) svga->clock *= 2;
if (ati28800->regs[0xb6] & 0x10)
{
svga->hdisp <<= 1;
@@ -319,6 +344,15 @@ static void ati28800_recalctimings(svga_t *svga)
svga->rowoffset <<= 1;
}
if(svga->crtc[0x17] & 4)
{
svga->vtotal <<= 1;
svga->dispend <<= 1;
svga->vsyncstart <<= 1;
svga->split <<= 1;
svga->vblankstart <<= 1;
}
if (!svga->scrblank && (ati28800->regs[0xb0] & 0x20)) /*Extended 256 colour modes*/
{
svga->render = svga_render_8bpp_highres;
@@ -385,6 +419,16 @@ ati28800_init(device_t *info)
return(ati);
}
void ati28800k_recalctimings(svga_t *svga)
{
ati28800_recalctimings(svga);
if (svga->render == svga_render_text_80 && ksc5601_mode_enabled)
{
svga->render = svga_render_text_80_ksc5601;
}
}
void *
ati28800k_init(device_t *info)
{
@@ -399,13 +443,13 @@ ati28800k_init(device_t *info)
get_korean_font_enabled = 0;
get_korean_font_kind = 0;
in_get_korean_font_kind_set = 0;
dbcs_mode_enabled = 0;
ksc5601_mode_enabled = 0;
rom_init(&ati28800->bios_rom, BIOS_ATIKOR_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(FONT_ATIKOR_PATH, 6);
svga_init(&ati28800->svga, ati28800, ati28800->memory << 10, /*Memory size, default 512KB*/
ati28800_recalctimings,
ati28800k_recalctimings,
ati28800k_in, ati28800k_out,
NULL,
NULL);
@@ -478,6 +522,17 @@ ati28800_force_redraw(void *priv)
ati->svga.fullchange = changeframecount;
}
void ati28800k_add_status_info(char *s, int max_len, void *p)
{
ati28800_t *ati28800 = (ati28800_t *)p;
char temps[128];
svga_add_status_info(s, max_len, &ati28800->svga);
sprintf(temps, "Korean SVGA mode enabled : %s\n\n", ksc5601_mode_enabled ? "Yes" : "No");
strncat(s, temps, max_len);
}
static void ati28800_add_status_info(char *s, int max_len, void *priv)
{
ati28800_t *ati = (ati28800_t *)priv;
@@ -558,7 +613,7 @@ device_t ati28800k_device =
ati28800k_available,
ati28800_speed_changed,
ati28800_force_redraw,
ati28800_add_status_info,
ati28800k_add_status_info,
ati28800_config
};

31
src/video/vid_ati_mach64.c
View File

@@ -8,7 +8,7 @@
*
* ATi Mach64 graphics card emulation.
*
* Version: @(#)vid_ati_mach64.c 1.0.4 2018/03/08
* Version: @(#)vid_ati_mach64.c 1.0.5 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -978,9 +978,16 @@ void mach64_start_fill(mach64_t *mach64)
mach64->accel.dst_y_start = mach64->dst_y_x & 0xfff;
mach64->accel.dst_width = (mach64->dst_height_width >> 16) & 0x1fff;
mach64->accel.dst_height = mach64->dst_height_width & 0x1fff;
mach64->accel.dst_height = mach64->dst_height_width & 0x1fff;
if (((mach64->dp_src >> 16) & 7) == MONO_SRC_BLITSRC)
{
if (mach64->accel.dst_width & 7)
mach64->accel.dst_width = (mach64->accel.dst_width & ~7) + 8;
}
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.src_x = 0;
mach64->accel.src_y = 0;
mach64->accel.src_x_start = (mach64->src_y_x >> 16) & 0xfff;
@@ -1160,7 +1167,8 @@ void mach64_start_line(mach64_t *mach64)
#define READ(addr, dat, width) if (width == 0) dat = svga->vram[((addr)) & mach64->vram_mask]; \
else if (width == 1) dat = *(uint16_t *)&svga->vram[((addr) << 1) & mach64->vram_mask]; \
else if (width == 2) dat = *(uint32_t *)&svga->vram[((addr) << 2) & mach64->vram_mask]; \
else dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> ((addr) & 7)) & 1;
else if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> ((addr) & 7)) & 1; \
else dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> (7 - ((addr) & 7))) & 1;
#define MIX switch (mix ? mach64->accel.mix_fg : mach64->accel.mix_bg) \
{ \
@@ -1199,10 +1207,17 @@ void mach64_start_line(mach64_t *mach64)
} \
else \
{ \
if (dest_dat & 1) \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << ((addr) & 7); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << ((addr) & 7)); \
if (dest_dat & 1) { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << ((addr) & 7); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << (7 - ((addr) & 7)); \
} else { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << ((addr) & 7)); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << (7 - ((addr) & 7)));\
} \
svga->changedvram[(((addr) >> 3) & mach64->vram_mask) >> 12] = changeframecount; \
}

24
src/video/vid_svga.c
View File

@@ -11,7 +11,7 @@
* This is intended to be used by another SVGA driver,
* and not as a card in it's own right.
*
* Version: @(#)vid_svga.c 1.0.5 2018/03/08
* Version: @(#)vid_svga.c 1.0.6 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -129,15 +129,10 @@ void svga_out(uint16_t addr, uint8_t val, void *p)
case 0x3C2:
svga->miscout = val;
svga->vidclock = val & 4;
if (val & 1)
{
io_removehandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->p);
}
else
{
io_sethandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->p);
}
svga_recalctimings(svga);
io_removehandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->p);
if (!(val & 1))
io_sethandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->p);
svga_recalctimings(svga);
break;
case 0x3C4:
svga->seqaddr = val;
@@ -410,15 +405,6 @@ void svga_recalctimings(svga_t *svga)
if (svga->crtc[9] & 0x20) svga->vblankstart |= 0x200;
svga->vblankstart++;
if(svga->crtc[0x17] & 4)
{
svga->vtotal <<= 1;
svga->dispend <<= 1;
svga->vsyncstart <<= 1;
svga->split <<= 1;
svga->vblankstart <<= 1;
}
svga->hdisp = svga->crtc[1];
svga->hdisp++;

203
src/video/vid_svga_render.c
View File

@@ -8,7 +8,7 @@
*
* SVGA renderers.
*
* Version: @(#)vid_svga_render.c 1.0.4 2018/03/06
* Version: @(#)vid_svga_render.c 1.0.5 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -50,7 +50,6 @@
int invert_display = 0;
int video_grayscale = 0;
int video_graytype = 0;
int dbcs_mode_enabled = 0;
uint32_t shade[5][256] =
@@ -226,7 +225,7 @@ void svga_render_text_80(svga_t *svga)
uint32_t *p = &((uint32_t *)buffer32->line[svga->displine + y_add])[32 + x_add];
int x, xx;
int drawcursor;
uint8_t chr, attr, dat, nextchr;
uint8_t chr, attr, dat;
uint32_t charaddr;
int fg, bg;
int xinc = (svga->seqregs[1] & 1) ? 8 : 9;
@@ -237,86 +236,77 @@ void svga_render_text_80(svga_t *svga)
chr = svga->vram[(svga->ma << 1) & svga->vram_display_mask];
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
if(dbcs_mode_enabled && x + xinc < svga->hdisp && chr & 0x80)
{
nextchr = svga->vram[((svga->ma + 4) << 1) & svga->vram_display_mask];
if(nextchr & 0x80)
{
if (drawcursor)
{
bg = svga->pallook[svga->egapal[attr & 15]];
fg = svga->pallook[svga->egapal[attr >> 4]];
}
else
{
fg = svga->pallook[svga->egapal[attr & 15]];
bg = svga->pallook[svga->egapal[attr >> 4]];
if (attr & 0x80 && svga->attrregs[0x10] & 8)
{
bg = svga->pallook[svga->egapal[(attr >> 4) & 7]];
if (svga->blink & 16)
fg = bg;
}
}
dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)][svga->sc];
if (svga->seqregs[1] & 1)
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
}
else
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if ((chr & ~0x1F) != 0xC0 || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
attr = svga->vram[(((svga->ma + 4) << 1) + 1) & svga->vram_display_mask];
if (drawcursor)
{
bg = svga->pallook[svga->egapal[attr & 15]];
fg = svga->pallook[svga->egapal[attr >> 4]];
}
else
{
fg = svga->pallook[svga->egapal[attr & 15]];
bg = svga->pallook[svga->egapal[attr >> 4]];
if (attr & 0x80 && svga->attrregs[0x10] & 8)
{
bg = svga->pallook[svga->egapal[(attr >> 4) & 7]];
if (svga->blink & 16)
fg = bg;
}
}
dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)][svga->sc + 16];
if (svga->seqregs[1] & 1)
{
for (xx = 0; xx < 8; xx++)
p[xx+8] = (dat & (0x80 >> xx)) ? fg : bg;
}
else
{
for (xx = 0; xx < 8; xx++)
p[xx+9] = (dat & (0x80 >> xx)) ? fg : bg;
if ((chr & ~0x1F) != 0xC0 || !(svga->attrregs[0x10] & 4))
p[17] = bg;
else
p[17] = (dat & 1) ? fg : bg;
}
svga->ma += 8;
p += xinc * 2;
continue;
}
}
if (attr & 8) charaddr = svga->charsetb + (chr * 128);
else charaddr = svga->charseta + (chr * 128);
if (drawcursor)
{
bg = svga->pallook[svga->egapal[attr & 15]];
fg = svga->pallook[svga->egapal[attr >> 4]];
}
else
{
fg = svga->pallook[svga->egapal[attr & 15]];
bg = svga->pallook[svga->egapal[attr >> 4]];
if (attr & 0x80 && svga->attrregs[0x10] & 8)
{
bg = svga->pallook[svga->egapal[(attr >> 4) & 7]];
if (svga->blink & 16)
fg = bg;
}
}
fg = svga_color_transform(fg);
bg = svga_color_transform(bg);
dat = svga->vram[charaddr + (svga->sc << 2)];
if (svga->seqregs[1] & 1)
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
}
else
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if ((chr & ~0x1F) != 0xC0 || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
}
svga->ma &= svga->vram_display_mask;
}
}
void svga_render_text_80_ksc5601(svga_t *svga)
{
int y_add = enable_overscan ? (overscan_y >> 1) : 0;
int x_add = enable_overscan ? 8 : 0;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (svga->fullchange)
{
uint32_t *p = &((uint32_t *)buffer32->line[svga->displine + y_add])[32 + x_add];
int x, xx;
int drawcursor;
uint8_t chr, attr, dat, nextchr;
uint32_t charaddr;
int fg, bg;
int xinc = (svga->seqregs[1] & 1) ? 8 : 9;
for (x = 0; x < svga->hdisp; x += xinc)
{
drawcursor = ((svga->ma == svga->ca) && svga->con && svga->cursoron);
chr = svga->vram[(svga->ma << 1) & svga->vram_display_mask];
nextchr = svga->vram[((svga->ma + 4) << 1) & svga->vram_display_mask];
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
if (drawcursor)
{
bg = svga->pallook[svga->egapal[attr & 15]];
@@ -338,6 +328,17 @@ void svga_render_text_80(svga_t *svga)
bg = svga_color_transform(bg);
dat = svga->vram[charaddr + (svga->sc << 2)];
if(x + xinc < svga->hdisp && (chr & nextchr & 0x80))
{
dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)][svga->sc];
}
else
{
if (attr & 8) charaddr = svga->charsetb + (chr * 128);
else charaddr = svga->charseta + (chr * 128);
dat = svga->vram[charaddr + (svga->sc << 2)];
}
if (svga->seqregs[1] & 1)
{
for (xx = 0; xx < 8; xx++)
@@ -354,6 +355,48 @@ void svga_render_text_80(svga_t *svga)
}
svga->ma += 4;
p += xinc;
if(x + xinc < svga->hdisp && (chr & nextchr & 0x80))
{
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
if (drawcursor)
{
bg = svga->pallook[svga->egapal[attr & 15]];
fg = svga->pallook[svga->egapal[attr >> 4]];
}
else
{
fg = svga->pallook[svga->egapal[attr & 15]];
bg = svga->pallook[svga->egapal[attr >> 4]];
if (attr & 0x80 && svga->attrregs[0x10] & 8)
{
bg = svga->pallook[svga->egapal[(attr >> 4) & 7]];
if (svga->blink & 16)
fg = bg;
}
}
dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)][svga->sc + 16];
if (svga->seqregs[1] & 1)
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
}
else
{
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if ((chr & ~0x1F) != 0xC0 || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
x += xinc;
}
}
svga->ma &= svga->vram_display_mask;
}

5
src/video/vid_svga_render.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the SVGA renderers.
*
* Version: @(#)vid_svga_render.h 1.0.1 2018/02/14
* Version: @(#)vid_svga_render.h 1.0.2 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -53,9 +53,8 @@ extern uint8_t edatlookup[4][4];
void svga_render_blank(svga_t *svga);
void svga_render_text_40(svga_t *svga);
void svga_render_text_40_12(svga_t *svga);
void svga_render_text_80(svga_t *svga);
void svga_render_text_80_12(svga_t *svga);
void svga_render_text_80_ksc5601(svga_t *svga);
void svga_render_2bpp_lowres(svga_t *svga);
void svga_render_2bpp_highres(svga_t *svga);

8
src/video/vid_table.c
View File

@@ -8,7 +8,7 @@
*
* Define all known video cards.
*
* Version: @(#)vid_table.c 1.0.7 2018/03/09
* Version: @(#)vid_table.c 1.0.8 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -348,6 +348,8 @@ video_is_mda(void)
case ROM_IBMPS2_M30_286:
case ROM_IBMPS2_M50:
case ROM_IBMPS2_M55SX:
case ROM_IBMPS2_M70_TYPE3:
case ROM_IBMPS2_M70_TYPE4:
case ROM_IBMPS2_M80:
case ROM_IBMPS1_2121:
case ROM_T3100E:
@@ -381,6 +383,8 @@ video_is_cga(void)
case ROM_IBMPS2_M30_286:
case ROM_IBMPS2_M50:
case ROM_IBMPS2_M55SX:
case ROM_IBMPS2_M70_TYPE3:
case ROM_IBMPS2_M70_TYPE4:
case ROM_IBMPS2_M80:
case ROM_IBMPS1_2121:
return(0);
@@ -413,6 +417,8 @@ video_is_ega_vga(void)
case ROM_IBMPS2_M30_286:
case ROM_IBMPS2_M50:
case ROM_IBMPS2_M55SX:
case ROM_IBMPS2_M70_TYPE3:
case ROM_IBMPS2_M70_TYPE4:
case ROM_IBMPS2_M80:
case ROM_IBMPS1_2121:
return(1);

10
src/win/Makefile.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Windows systems using the MinGW32 environment.
#
# Version: @(#)Makefile.mingw 1.0.10 2018/03/11
# Version: @(#)Makefile.mingw 1.0.11 2018/03/12
#
# Author: Fred N. van Kempen, <decwiz@yahoo.com>
#
@@ -110,9 +110,6 @@ endif
ifndef GREENB
GREENB := n
endif
ifndef MRTHOR
MRTHOR := y
endif
ifndef I686
I686 := n
endif
@@ -152,7 +149,6 @@ ifeq ($(DEV_BUILD), y)
LASERXT := y
PORTABLE3 := y
GREENB := y
MRTHOR := y
I686 := y
PAS16 := y
STEALTH32 := y
@@ -408,10 +404,6 @@ ifeq ($(DEV_BRANCH), y)
DEVBROBJ += m_at_4gpv31.o
endif
ifeq ($(MRTHOR), y)
OPTS += -DUSE_MRTHOR
endif
ifeq ($(I686), y)
OPTS += -DUSE_I686
DEVBROBJ += m_at_440fx.o

4
src/win/win_settings.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Settings dialog.
*
* Version: @(#)win_settings.c 1.0.9 2018/03/10
* Version: @(#)win_settings.c 1.0.10 2018/03/12
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -4402,7 +4402,7 @@ static void cdrom_add_locations(HWND hdlg)
}
h = GetDlgItem(hdlg, IDC_COMBO_CD_SPEED);
for (i = 1; i <= 56; i++)
for (i = 1; i <= 72; i++)
{
wsprintf(lptsTemp, L"%ix", i);
SendMessage(h, CB_ADDSTRING, 0, (LPARAM) lptsTemp);