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Reduce number of apertures needed for GPU memory access by refining aperture setup to use PHYS and MMU/EMEM

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apertures instead of PHYS and EMEM1/MMU and EMEM2. Modify setup to utilize all of reserved memory for PHYS
aperture instead of splitting. Now, a 32MB (in platform fixup, mx51_efikamx.c) reserved block is utilized as
the PHYS, or an 8MB chunk is carved out of coherent memory space (DMA allocation) if reservation is disabled.
Normal memory usage for a desktop with browser, office and media player is well over 64MB but the Xorg driver
will evict unused pixmaps where necessary to keep the current performance pixmaps in place.
This commit is contained in:
Matt Sealey
2011-08-11 09:22:55 -05:00
parent c5de0bc6cf
commit a0ae9134ba
3 changed files with 56 additions and 80 deletions
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19
drivers/mxc/amd-gpu/include/gsl_halconfig.h
View File

@@ -34,22 +34,13 @@
#define __GSL_HALCONFIG_H
#define GSL_HAL_GPUBASE_REG_YDX 0x30000000
#define GSL_HAL_SIZE_REG_YDX 0x00020000 /* 128KB */
#define GSL_HAL_SIZE_REG_YDX SZ_128K /* 128KB */
#define GSL_HAL_SIZE_REG_G12 0x00001000 /* 4KB */
#define GSL_HAL_SIZE_REG_G12 SZ_4K /* 4KB */
/* generic, virtualized allocation pool */
#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU 0x08000000 /* 128MB */
/* contiguous pool:
* these two values absolutely have to fit inside the gpu_mem
* reserved area, don't make them bigger (will explode) or
* smaller (wasting memory)!
*/
#define GSL_HAL_SHMEM_SIZE_EMEM2_MMU 0x00800000 /* 8MB */
#define GSL_HAL_SHMEM_SIZE_PHYS_MMU 0x01800000 /* 24MB */
#define GSL_HAL_SHMEM_SIZE_EMEM_MMU SZ_128M
#define GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU 0x00A00000 /* 10MB */
#define GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU 0x00200000 /* 2MB */
#define GSL_HAL_SHMEM_SIZE_PHYS_NOMMU 0x00100000 /* 1MB */
#define GSL_HAL_SHMEM_SIZE_EMEM_NOMMU (10*SZ_1M)
#define GSL_HAL_SHMEM_SIZE_PHYS_NOMMU SZ_1M
#endif /* __GSL_HALCONFIG_H */

115
drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c
View File

@@ -36,9 +36,9 @@
#define GSL_HAL_MEM1 0
#define GSL_HAL_MEM2 1
#define GSL_HAL_MEM3 2
//#define GSL_HAL_MEM3 2
/* #define GSL_HAL_DEBUG */
#define GSL_HAL_DEBUG
extern phys_addr_t gpu_2d_regbase;
extern int gpu_2d_regsize;
@@ -90,7 +90,7 @@ KGSLHAL_API int
kgsl_hal_init(void)
{
gsl_hal_t *hal;
unsigned long totalsize, mem1size;
unsigned long physsize, virtsize;
unsigned int va, pa;
if (gsl_driver.hal) {
@@ -156,94 +156,85 @@ kgsl_hal_init(void)
#endif
}
physsize = SZ_8M;
if (gsl_driver.enable_mmu) {
printk(KERN_INFO "gpu mmu enabled\n");
totalsize = GSL_HAL_SHMEM_SIZE_EMEM2_MMU + GSL_HAL_SHMEM_SIZE_PHYS_MMU;
mem1size = GSL_HAL_SHMEM_SIZE_EMEM1_MMU;
if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) {
printk(KERN_INFO "GPU MMU enabled\n");
virtsize = GSL_HAL_SHMEM_SIZE_EMEM_MMU;
if (gpu_reserved_mem && gpu_reserved_mem_size >= physsize) {
pa = gpu_reserved_mem;
va = (unsigned int)ioremap(gpu_reserved_mem, totalsize);
va = (unsigned int)ioremap/*_wc*/(gpu_reserved_mem, gpu_reserved_mem_size);
physsize = gpu_reserved_mem_size;
} else {
va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
if (gpu_reserved_mem_size > 0) {
printk(KERN_INFO "Reallocating PHYS aperture: reserved memory going to waste\n");
}
gpu_reserved_mem = 0;
va = (unsigned int)dma_alloc_coherent(0, physsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
}
} else {
printk(KERN_INFO "gpu mmu disabled\n");
if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) {
totalsize = gpu_reserved_mem_size;
printk(KERN_INFO "GPU MMU disabled\n");
if (gpu_reserved_mem && gpu_reserved_mem_size >= physsize) {
physsize = gpu_reserved_mem_size;
pa = gpu_reserved_mem;
va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size);
} else {
if (gpu_reserved_mem_size > 0) {
printk(KERN_INFO "Reallocating PHYS aperture: reserved memory going to waste\n");
}
gpu_reserved_mem = 0;
totalsize = GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU + GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
physsize = GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
va = (unsigned int)dma_alloc_coherent(0, physsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
}
mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU);
virtsize = physsize - GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
}
if (va) {
kos_memset((void *)va, 0, totalsize);
kos_memset((void *)va, 0, physsize);
hal->memchunk.mmio_virt_base = (void *)va;
hal->memchunk.mmio_phys_base = pa;
hal->memchunk.sizebytes = totalsize;
hal->memchunk.sizebytes = physsize;
#ifdef GSL_HAL_DEBUG
printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base);
printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base);
printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes);
printk(KERN_INFO "Reserved memory: pa = 0x%p va = 0x%p size = 0x%08x\n",
(void *)hal->memchunk.mmio_phys_base,
(void *)hal->memchunk.mmio_virt_base,
hal->memchunk.sizebytes
);
#endif
hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
hal->memspace[GSL_HAL_MEM2].gpu_base = pa;
if (gsl_driver.enable_mmu) {
hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
va += GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
pa += GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
} else {
hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
va += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
pa += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
}
hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
hal->memspace[GSL_HAL_MEM2].gpu_base = pa;
hal->memspace[GSL_HAL_MEM2].sizebytes = physsize;
va += physsize;
pa += physsize;
#ifdef GSL_HAL_DEBUG
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes);
#endif
hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va;
hal->memspace[GSL_HAL_MEM3].gpu_base = pa;
if (gsl_driver.enable_mmu) {
hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_MMU;
va += GSL_HAL_SHMEM_SIZE_PHYS_MMU;
pa += GSL_HAL_SHMEM_SIZE_PHYS_MMU;
} else {
hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
va += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
pa += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
}
#ifdef GSL_HAL_DEBUG
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes);
printk(KERN_INFO "GSL_HAL_MEM2 aperture (PHYS) pa = 0x%p va = 0x%p size = 0x%08x\n",
(void *)hal->memspace[GSL_HAL_MEM2].gpu_base,
(void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base,
hal->memspace[GSL_HAL_MEM2].sizebytes
);
#endif
if (gsl_driver.enable_mmu) {
gsl_linux_map_init();
hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START;
hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START;
hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size;
} else {
hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va;
hal->memspace[GSL_HAL_MEM1].gpu_base = pa;
hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size;
}
hal->memspace[GSL_HAL_MEM1].sizebytes = virtsize;
#ifdef GSL_HAL_DEBUG
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base);
printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes);
printk(KERN_INFO "GSL_HAL_MEM1 aperture (%s) pa = 0x%p va = 0x%p size = 0x%08x\n",
gsl_driver.enable_mmu ? "MMU" : "EMEM",
(void *)hal->memspace[GSL_HAL_MEM1].gpu_base,
(void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base,
hal->memspace[GSL_HAL_MEM1].sizebytes
);
#endif
} else {
kgsl_hal_close();
@@ -316,18 +307,12 @@ kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config)
config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base;
config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes;
config->apertures[1].id = GSL_APERTURE_EMEM;
config->apertures[1].channel = GSL_CHANNEL_2;
config->apertures[1].id = GSL_APERTURE_PHYS;
config->apertures[1].channel = GSL_CHANNEL_1;
config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base;
config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base;
config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes;
config->apertures[2].id = GSL_APERTURE_PHYS;
config->apertures[2].channel = GSL_CHANNEL_1;
config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base;
config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base;
config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes;
status = GSL_SUCCESS;
}

2
drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
View File

@@ -32,7 +32,7 @@
#include "gsl_halconfig.h"
#define GSL_LINUX_MAP_RANGE_START (1024*1024)
#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1_MMU)
#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM_MMU)
int gsl_linux_map_init(void);
void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size);