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ENGR00120394-2 imx: make tzic use dynamic base address

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Different chips have TZIC interrupt controller at different addresses,
so make the mapping dynamic.

Signed-off-by: Rob Herring <r.herring@freescale.com>
This commit is contained in:
Rob Herring
2010-02-01 17:29:57 -02:00
committed by Matt Sealey
parent a45319ebdb
commit 1ab4fba6b4
9 changed files with 37 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-mx37/devices.c
View File

@@ -22,6 +22,7 @@
#include <linux/iram_alloc.h>
#include <mach/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/mxc_dptc.h>
#include <mach/mxc_dvfs.h>
@@ -1056,6 +1057,11 @@ int __init mxc_init_srpgconfig(void)
return 0;
}
void __init mx37_init_irq(void)
{
mxc_tzic_init_irq(TZIC_BASE_ADDR);
}
int __init mxc_init_devices(void)
{
mxc_init_wdt();

2
arch/arm/mach-mx37/mx37_3stack.c
View File

@@ -960,7 +960,7 @@ MACHINE_START(MX37_3DS, "Freescale MX37 3-Stack Board")
.boot_params = PHYS_OFFSET + 0x100,
.fixup = fixup_mxc_board,
.map_io = mx37_map_io,
.init_irq = mxc_init_irq,
.init_irq = mx37_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END

13
arch/arm/mach-mx51/devices.c
View File

@@ -26,6 +26,7 @@
#include <linux/pwm_backlight.h>
#include <linux/iram_alloc.h>
#include <asm/mach-types.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/sdma.h>
#include <mach/mxc_dvfs.h>
@@ -1326,6 +1327,18 @@ static inline void mxc_init_gpu2d(void)
}
#endif
void __init mx51_init_irq(void)
{
unsigned long tzic_addr;
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
tzic_addr = TZIC_BASE_ADDR_T01;
else
tzic_addr = TZIC_BASE_ADDR;
mxc_tzic_init_irq(tzic_addr);
}
int __init mxc_init_devices(void)
{
mxc_init_wdt();

12
arch/arm/mach-mx51/mm.c
View File

@@ -34,11 +34,6 @@ static struct map_desc mx51_io_desc[] __initdata = {
.pfn = __phys_to_pfn(DEBUG_BASE_ADDR),
.length = DEBUG_SIZE,
.type = MT_DEVICE},
{
.virtual = TZIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(TZIC_BASE_ADDR),
.length = TZIC_SIZE,
.type = MT_DEVICE},
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
@@ -68,12 +63,5 @@ static struct map_desc mx51_io_desc[] __initdata = {
*/
void __init mx51_map_io(void)
{
u32 tzic_addr;
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
tzic_addr = TZIC_BASE_ADDR_T01;
else
tzic_addr = TZIC_BASE_ADDR;
mx51_io_desc[1].pfn = __phys_to_pfn(tzic_addr);
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}

2
arch/arm/mach-mx51/mx51_3stack.c
View File

@@ -1306,7 +1306,7 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
.boot_params = PHYS_OFFSET + 0x100,
.fixup = fixup_mxc_board,
.map_io = mx51_map_io,
.init_irq = mxc_init_irq,
.init_irq = mx51_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END

2
arch/arm/mach-mx51/mx51_babbage.c
View File

@@ -1115,7 +1115,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
.boot_params = PHYS_OFFSET + 0x100,
.fixup = fixup_mxc_board,
.map_io = mx51_map_io,
.init_irq = mxc_init_irq,
.init_irq = mx51_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END

5
arch/arm/plat-mxc/include/mach/common.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -23,6 +23,9 @@ extern void mx35_map_io(void);
extern void mx37_map_io(void);
extern void mx51_map_io(void);
extern void mxc_init_irq(void);
extern void mx51_init_irq(void);
extern void mx37_init_irq(void);
extern void mxc_tzic_init_irq(unsigned long);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
extern int mx1_clocks_init(unsigned long fref);
extern int mx21_clocks_init(unsigned long lref, unsigned long fref);

5
arch/arm/plat-mxc/include/mach/entry-macro.S
View File

@@ -11,6 +11,8 @@
#include <mach/hardware.h>
.extern tzic_base
#define AVIC_NIMASK 0x04
@ this macro disables fast irq (not implemented)
@@ -19,7 +21,8 @@
.macro get_irqnr_preamble, base, tmp
#ifdef CONFIG_MXC_TZIC
ldr \base, =TZIC_IO_ADDRESS(TZIC_BASE_ADDR)
ldr \tmp, =tzic_base
ldr \base, [\tmp]
#else
ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
#ifdef CONFIG_MXC_IRQ_PRIOR

10
arch/arm/plat-mxc/tzic.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -26,7 +26,9 @@
* TZIC Registers *
*****************************************
*/
#define TZIC_BASE IO_ADDRESS(TZIC_BASE_ADDR)
void __iomem *tzic_base;
#define TZIC_BASE (tzic_base)
#define TZIC_INTCNTL (TZIC_BASE + 0x0000) /* control register */
#define TZIC_INTTYPE (TZIC_BASE + 0x0004) /* Controller type register */
#define TZIC_IMPID (TZIC_BASE + 0x0008) /* Distributor Implementer Identification Register */
@@ -117,10 +119,12 @@ static struct irq_chip mxc_tzic_chip = {
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init mxc_init_irq(void)
void __init mxc_tzic_init_irq(unsigned long base)
{
int i;
tzic_base = ioremap(base, SZ_4K);
/* put the TZIC into the reset value with
* all interrupts disabled
*/