amd-gpu: memory barrier for safety after issueibcmds sync mem

Makes sense (and is from Qualcomm's driver) since we cannot guarantee
the memory writes have finished posting before we submit them to the
GPU.

drivers/mxc/amd-gpu/gsl_g12.c

@@ -687,6 +687,7 @@ kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr,
 
     /* sync mem */
     kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false);
+    mb();
 
     g_z1xx.offs = 0;
     g_z1xx.curr = nextbuf;