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ENGR00124762 MX5: Fix clock div zero issue

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Fix clock div zero issue in mx5 clock file

Signed-off-by: Lily Zhang <r58066@freescale.com>
This commit is contained in:
Lily Zhang
2010-06-30 13:05:08 +08:00
committed by Matt Sealey
parent 3e0c7cb2ff
commit b3dcff4217
1 changed files with 15 additions and 5 deletions
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20
arch/arm/mach-mx5/clock.c
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@@ -753,7 +753,9 @@ static unsigned long _clk_axi_a_round_rate(struct clk *clk,
/* Make sure rate is not greater than the maximum value for the clock.
* Also prevent a div of 0.
*/
if ((clk->parent->rate / div > max_axi_a_clk) || div == 0)
if (div == 0)
div++;
if (clk->parent->rate / div > max_axi_a_clk)
div++;
if (div > 8)
@@ -792,7 +794,9 @@ static unsigned long _clk_ddr_hf_round_rate(struct clk *clk,
/* Make sure rate is not greater than the maximum value for the clock.
* Also prevent a div of 0.
*/
if ((clk->parent->rate / div > MAX_DDR_HF_RATE) || div == 0)
if (div == 0)
div++;
if (clk->parent->rate / div > MAX_DDR_HF_RATE)
div++;
if (div > 8)
@@ -902,7 +906,9 @@ static unsigned long _clk_axi_b_round_rate(struct clk *clk,
/* Make sure rate is not greater than the maximum value for the clock.
* Also prevent a div of 0.
*/
if ((clk->parent->rate / div > max_axi_b_clk) || div == 0)
if (div == 0)
div++;
if (clk->parent->rate / div > max_axi_b_clk)
div++;
if (div > 8)
@@ -978,7 +984,9 @@ static unsigned long _clk_ahb_round_rate(struct clk *clk,
/* Make sure rate is not greater than the maximum value for the clock.
* Also prevent a div of 0.
*/
if ((clk->parent->rate / div > MAX_AHB_CLK) || div == 0)
if (div == 0)
div++;
if (clk->parent->rate / div > MAX_AHB_CLK)
div++;
if (div > 8)
@@ -1117,7 +1125,9 @@ static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
/* Make sure rate is not greater than the maximum value for the clock.
* Also prevent a div of 0.
*/
if ((clk->parent->rate / div > MAX_EMI_SLOW_CLK) || div == 0)
if (div == 0)
div++;
if (clk->parent->rate / div > MAX_EMI_SLOW_CLK)
div++;
if (div > 8)