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ENGR00117389 Port 5.0.0 release to 2.6.31

Browse Source 
This is i.MX BSP 5.0.0 release ported to 2.6.31

Signed-off-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Alan Tull <r80115@freescale.com>
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
This commit is contained in:
Rob Herring
2009-10-19 14:43:19 -05:00
committed by Matt Sealey
parent 40f418ad28
commit be0524d38f
860 changed files with 347764 additions and 1166 deletions
Download Patch File Download Diff File Expand all files Collapse all files

369
Documentation/imx_nfc.txt Normal file
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@@ -0,0 +1,369 @@
i.MX NAND Flash Controller Driver Documentation
===============================================
Definitions of Terms
====================
To avoid confusion, let's carefully define some of the terms we'll be using:
"NAND Flash Chip" or "Chip"
A NAND Flash storage array and controller (including a chip select
signal, ready/busy signal, data register, etc.).
"NAND Flash Package" or "Package"
A hardware package containing one or more NAND Flash chips that share
data lines and most control signals, but with separate chip select
and ready/busy signals. Package "boundaries" are unimportant to MTD.
"NAND Flash Medium" or "Medium"
A collection of one or more NAND Flash chips that the system views as
logically contiguous.
"Memory Technology Device" or "MTD"
An abstraction of underlying memory hardware, represented by a single
struct mtd_info.
"NAND Flash MTD"
An abstraction of a NAND Flash medium that is represented by a single
struct nand_chip (the name of this structure is misleading because it
has evolved to represent an entire medium, not just a single chip).
All the physical chips in a NAND Flash MTD medium have answered the
"Read ID" command with the same manufacturer code and device code and
are presumed to have identical characteristics.
"NAND Flash MTD Hardware-independent Layer" or "HIL"
The code that implements an MTD interface and drives all NAND Flash
MTDs.
"NAND Flash MTD Hardware Abstraction Layer" or "HAL"
Code that implements the internal NAND Flash hardware model and
matches it to specific hardware.
"NAND Flash MTD Reference Implementation"
A reference implementation of a HAL "stack."
"Out-of-Band" or "OOB"
An adjective describing information that is not part of the "data" in
a NAND Flash page. NAND Flash pages are generally described in terms
of the amount of data they can hold (e.g., "2K pages" or "4K pages").
The physical page size is actually larger than this and the
additional bytes are called "out-of-band."
The Structure of the MTD NAND Flash System
==========================================
The following figure illustrates how control flows down from the system's
MTD interface into the NAND Flash MTD system and down to the hardware-
specific implementation (this driver):
/ +---------------------------------------+
| | MTD |
| +---------------------------------------+
MTD | |
| | +----------+
| | | |
| v v |
\ ======================================== |
- struct mtd_info |
/ ======================================== |
| | |
| v |
| +---------------------------------------+ |
| | NAND Flash MTD | |
NAND Flash | | Interface Functions | |
Hardware- | +---------------------------------------+ |
Independent | | | |
Layer | | v |
(HIL) | +-------------+ | +-------------+ +-------------+
| | Init | | | Support | | Reference |
| | Functions | | | Functions | |BBT Functions|
| +-------------+ | +-------------+ +-------------+
| | | | ^
| v v v |
\ ======================================== |
- struct nand_chip |
/ ======================================== |
| | ^ | ^ | |
NAND Flash | | | | | | |
Hardware | v | v | | |
Abstraction | +--------------+ +---------------+ | |
Layer | | Hardware- | | Reference | +-----------+
(HAL) | | Specific | | |
| |Implementation| |Implementations|
\ +--------------+ +---------------+
The function pointers and attributes in struct mtd_info embody an abstract
model of memory technology devices.
The struct nand_chip is an aggregation of two categories of function pointers
and attributes:
- Function pointers and attributes used by the HIL. These members embody
an abstract model of NAND Flash media, or a hardware abstraction
layer (HAL).
- Function pointers and attributes used by the reference implementations.
The single most confusing thing about the MTD NAND Flash system is that
struct nand_chip contains all the main HAL members mixed up with all the
members used only by the reference implementation, without any clear
distinction. Recognizing the distinction is critical for understanding the
relationship between the HIL and HAL, and can greatly simplify driver
implementation.
The fundamental operations represented by the function pointers in
struct nand_chip fall into the following categories (from conceptually
"low-level" to "high-level"):
- Signal Control
- Chip Control
- Low-level I/O
- ECC Control
- ECC-aware I/O
- Error Recovery
- High-level I/O
- Bad Block Management
The HIL uses only the following "Replaceable" function pointers in
struct nand_chip:
- Signal Control
- None
- Chip Control
- dev_ready
- select_chip
- cmdfunc
- waitfunc
- Low-level I/O
- read_byte
- ECC Control
- None
- ECC-aware I/O
- ecc.read_page
- ecc.read_page_raw
- Error Recovery
- None
- High-level I/O
- write_page
- ecc.read_oob
- ecc.write_oob
- Bad Block Management
- block_bad
- block_markbad
- scan_bbt
Note that the HIL calls erase_cmd, but this member is marked "Internal."
The HIL uses only the following commands with cmdfunc:
* NAND_CMD_STATUS
- nand_check_wp() - Checks if the current chip is
write-protected.
* NAND_CMD_READID
- nand_get_flash_type() - Gets information about the first chip.
- nand_scan_ident() - Scans for additional chips.
* NAND_CMD_RESET
- nand_do_write_oob() - Clears a bug observed on the
Toshiba TC5832DC and DiskOnChip 2000.
* NAND_CMD_READ0
- nand_do_read_ops() - Used to begin a full page read (both with
and without ECC).
* NAND_CMD_ERASE1
- single_erase_cmd() - Starts a block erase operation.
- multi_erase_cmd() - Starts a block erase operation.
* NAND_CMD_ERASE2
- single_erase_cmd() - Finishes a block erase operation.
- multi_erase_cmd() - Finishes a block erase operation.
Since this is all the HIL uses, this is all a driver needs to implement.
The Structure of the imx_nfc Driver
===================================
This driver supports many different versions of underlying controller, and
also supports higher-level abstractions like interleaving. To facilitate this
versatility, the code is layered as shown in the following diagram:
+--------------------------------------+
| MTD |
+--------------------------------------+
| NAND Flash MTD |
======================================== <-- struct nand_chip
/ | MTD Interface Layer (mil_*) |
| | +----------------------------------+
| | | Medium Abstraction Layer (mal_*) |
imx_nfc | | | |
driver | | | +------------------------+
| | | | NFC Utils (nfc_util_*) |
| ======================================== <-- struct nfc_hal
\ | NFC HAL (nfc_x_y_*) |
======================================== <-- Hardware Interface
| NFC Hardware |
+--------------------------------------+
MTD Interface Layer
-------------------
This layer includes functions that the NAND Flash MTD system calls directly.
In a manner of speaking, this layer "parses" the function calls made by MTD
and translates them into fundamental operations understood by the Medium
Abstraction Layer. Some simple operations don't need any abstraction, so code
in this layer can sometimes use the NFC HAL directly.
Medium Abstraction Layer
------------------------
This layer implements the abstract model of the NAND Flash medium and hides
details that shouldn't concern higher layers (e.g., interleaving).
NFC Utilities
-------------
These functions make it easier to use the NFC HAL. Even though this layer
is shown above the NFC HAL in the diagram, it's actually possible for the
NFC HAL to call some of these functions.
NFC HAL
-------
This layer implements the abstract model of an i.MX NAND Flash controller.
Other Collections of Functions
------------------------------
- System Interface
- imx_nfc_*
- sysfs Interface
- get_module_*
- set_module_*
- show_device_*
- store_device_*
i.MX NAND Flash Controller Versions
===================================
The i.MX NAND Flash controller (NFC) has evolved over time. Both its memory
layout and behaviors have changed. In this driver, we use major and minor
version numbers to label these stages in the NFC's evolution. These version
numbers are very useful, but they are entirely a figment of this driver's
imagination -- you will never find them in Freescale hardware reference
manuals.
When the platform code instantiates an i.MX NFC device, it provides a struct
imx_nfc_platform_data that contains platform-specific information. This
includes the major and minor version numbers for the NFC. This driver uses
the version numbers to select an appopriate NFC HAL structure.
i.MX NFC Memory Map
===================
While many things have changed during the evolution of the NFC, much has
remained the same. All i.MX NFCs have two or three essential memory-mapped
regions: a set of buffers, and one or two sets of registers (one on the AXI
bus and perhaps a second on the IP bus).
The buffer area contains the captive memory to which the NFC writes data
received from the NAND Flash medium. This area is subdivided into several
contiguous "main" buffers that hold 512-byte chunks of data, and several
"spare" buffers that hold varying-size chunks of out-of-band bytes. The
number of main buffers is always the same as the number of spare buffers, but
the exact count and the size of the spare buffers varies across NFC versions.
The register areas contain the NFC's control interface. Some versions have
only one set of registers, and some have two.
The platform-specific resources passed to this driver include the starting
and ending physical addresses of the buffer and register areas. This driver
maps those physical addresses to virtual addresses, and then uses version-
specific offsets and bit masks to operate the NFC.
Matching the NAND Flash MTD Page Model with the i.MX NFC
========================================================
The NAND Flash MTD HAL model views a page as containing two essentially
independent groups of bytes: "data" bytes and "out-of-band" bytes. If the
underlying physical format has data and out-of-band bytes distributed across
the page, they must be reassembled before being delivered to the caller
(e.g., see the function nand_read_page_syndrome(), which is part of the
reference implementation).
The i.MX NFC hardware imposes both a physical page layout and a layout in its
memory buffer that differ from the HAL model. The following figure shows how
all these layouts relate to each other:
i.MX NFC i.MX NFC
Physical Memory NAND Flash
Page Buffers MTD Model
+--------+ +--------+ +--------+
|OOB[N-1]| |OOB[N-1]| |OOB[N-1]|
+--------+ +--------+ +--------+
| | <gap> |OOB[ 1 ]|
| Data | +--------+ +--------+
| [N-1] | |OOB[ 1 ]| |OOB[ 0 ]|
| | +--------+ +--------+
+--------+ <gap>
... +--------+ +--------+
+--------+ |OOB[ 0 ]| | |
|OOB[ 1 ]| +--------+ | Data |
+--------+ | | | [N-1] |
| | | Data | | |
| Data | | [N-1] | +--------+
| [ 1 ] | | | | |
| | +--------+ | Data |
+--------+ ... | [ 1 ] |
|OOB[ 0 ]| +--------+ | |
+--------+ | | +--------+
| | | Data | | |
| Data | | [ 1 ] | | Data |
| [ 0 ] | | | | [ 0 ] |
| | +--------+ | |
+--------+ | | +--------+
| Data |
| [ 0 ] |
| |
+--------+
The NFC memory is *almost* what we want, but not quite. The problems are:
1) There are gaps between the out-of-band fragments.
2) The NFC memory responds only to 16-byte or 32-byte reads and writes.
To resolve these problems, we've encapsulated the NFC memory behind these
functions:
nfc_util_copy_from_the_nfc() - Copies data to main memory from the the NFC.
nfc_util_copy_to_the_nfc() - Copies data from main memory to the NFC.
These functions don't take pointers to locations within the NFC memory - they
take a "column address." These functions know how to skip over the gaps and
handle the NFC memory such that it looks like all the data and out-of-band
bytes are completely contiguous. They also handle copying arbitrary bytes
from/to a memory that only responds to 16- or 32-byte reads/writes. If you're
accessing the NFC memory without these functions, you're *probably* doing
something wrong.

20
arch/arm/Kconfig
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@@ -294,7 +294,8 @@ config ARCH_MXC
select ARCH_MTD_XIP
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
# select HAVE_CLK
select ZONE_DMA
help
Support for Freescale MXC/iMX-based family of processors
@@ -308,6 +309,7 @@ config ARCH_STMP3XXX
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select USB_ARCH_HAS_EHCI
select ZONE_DMA
help
Support for systems based on the Freescale 3xxx CPUs.
@@ -1077,7 +1079,7 @@ config LEDS
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91 || ARCH_DAVINCI || \
ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW || ARCH_MXC
help
If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status.
@@ -1254,7 +1256,7 @@ endmenu
menu "CPU Power Management"
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX || ARCH_MXC || ARCH_STMP3XXX)
source "drivers/cpufreq/Kconfig"
@@ -1289,6 +1291,12 @@ config CPU_FREQ_S3C64XX
bool "CPUfreq support for Samsung S3C64XX CPUs"
depends on CPU_FREQ && CPU_S3C6410
config CPU_FREQ_IMX
tristate "CPUfreq driver for i.MX CPUs"
depends on ARCH_MXC && CPU_FREQ && REGULATOR
help
This enables the CPUfreq driver for i.MX CPUs.
endif
source "drivers/cpuidle/Kconfig"
@@ -1436,6 +1444,8 @@ source "drivers/char/Kconfig"
source "drivers/i2c/Kconfig"
source "drivers/i2c-slave/Kconfig"
source "drivers/spi/Kconfig"
source "drivers/gpio/Kconfig"
@@ -1490,6 +1500,10 @@ source "drivers/uio/Kconfig"
source "drivers/staging/Kconfig"
if ARCH_MXC
source "drivers/mxc/Kconfig"
endif
endmenu
source "fs/Kconfig"

6
arch/arm/Makefile
View File

@@ -50,7 +50,7 @@ comma = ,
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7
@@ -135,7 +135,11 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := mx1
machine-$(CONFIG_ARCH_MX2) := mx2
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX35) := mx35
machine-$(CONFIG_ARCH_MX37) := mx37
machine-$(CONFIG_ARCH_MX51) := mx51
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
machine-$(CONFIG_ARCH_OMAP1) := omap1

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arch/arm/configs/imx25_3stack_defconfig Normal file
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arch/arm/configs/imx31_3stack_defconfig Normal file
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arch/arm/configs/imx35_3stack_defconfig Normal file
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976
arch/arm/configs/imx35evb_defconfig Normal file
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@@ -0,0 +1,976 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
# CONFIG_GENERIC_GPIO is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
CONFIG_ARCH_MXC=y
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
#
# Boot options
#
#
# Power management
#
#
# Freescale MXC Implementations
#
# CONFIG_ARCH_MXC91321 is not set
# CONFIG_ARCH_MX37 is not set
CONFIG_ARCH_MX35=y
# CONFIG_ARCH_MX3 is not set
# CONFIG_ARCH_MX27 is not set
# CONFIG_ARCH_MX21 is not set
CONFIG_MXC_SDMA_API=y
#
# MX35 Options
#
# CONFIG_MACH_MX35_3DS is not set
CONFIG_MACH_MX35EVB=y
# CONFIG_MX35_DOZE_DURING_IDLE is not set
#
# Device options
#
CONFIG_ARCH_HAS_EVTMON=y
CONFIG_DMA_ZONE_SIZE=24
#
# Processor Type
#
CONFIG_CPU_32=y
# CONFIG_CPU_ARM926T is not set
CONFIG_CPU_V6=y
# CONFIG_CPU_32v6K is not set
CONFIG_CPU_32v6=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_OUTER_CACHE=y
CONFIG_CACHE_L2X0=y
#
# Bus support
#
CONFIG_ISA=y
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCCARD=m
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=m
CONFIG_PCMCIA_LOAD_CIS=y
# CONFIG_PCMCIA_IOCTL is not set
#
# PC-card bridges
#
# CONFIG_I82365 is not set
# CONFIG_TCIC is not set
CONFIG_PCMCIA_PROBE=y
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=100
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_VFP=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y
# CONFIG_MAC80211 is not set
CONFIG_IEEE80211=y
# CONFIG_IEEE80211_DEBUG is not set
# CONFIG_IEEE80211_CRYPT_WEP is not set
# CONFIG_IEEE80211_CRYPT_CCMP is not set
# CONFIG_IEEE80211_CRYPT_TKIP is not set
# CONFIG_IEEE80211_SOFTMAC is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_PARPORT is not set
# CONFIG_PNP is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_SMC911X is not set
# CONFIG_SMSC911X is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NET_PCI=y
# CONFIG_AC3200 is not set
# CONFIG_APRICOT is not set
# CONFIG_B44 is not set
# CONFIG_CS89x0 is not set
# CONFIG_FEC is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
CONFIG_NET_PCMCIA=y
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_FMVJ18X is not set
CONFIG_PCMCIA_PCNET=m
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_PCMCIA_XIRC2PS is not set
# CONFIG_PCMCIA_AXNET is not set
# CONFIG_WAN is not set
CONFIG_PPP=m
# CONFIG_PPP_MULTILINK is not set
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_BSDCOMP is not set
# CONFIG_PPP_MPPE is not set
# CONFIG_PPPOE is not set
# CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_MXC_MU is not set
# CONFIG_MXC_SUPER_GEM is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_MXC=y
CONFIG_SERIAL_MXC_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
# SPI support
#
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
CONFIG_SPI_BITBANG=y
CONFIG_SPI_MXC=y
# CONFIG_SPI_MXC_TEST_LOOPBACK is not set
CONFIG_SPI_MXC_SELECT1=y
# CONFIG_SPI_MXC_SELECT2 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_MXC_WATCHDOG=y
#
# ISA-based Watchdog Cards
#
# CONFIG_PCWATCHDOG is not set
# CONFIG_MIXCOMWD is not set
# CONFIG_WDT is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
# CONFIG_HID is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# On-The-Go and USB Peripheral Support
#
# CONFIG_OTG is not set
#
#
#
#
#
#
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_MXC=y
# CONFIG_RTC_DRV_MXC_V2 is not set
#
# MXC support drivers
#
# CONFIG_MXC_IPU is not set
#
# MXC SSI support
#
# CONFIG_MXC_SSI is not set
#
# MXC Digital Audio Multiplexer support
#
# CONFIG_MXC_DAM is not set
#
# MXC PMIC support
#
# CONFIG_MXC_PMIC is not set
#
# Advanced Power Management devices
#
#
# MXC Security Drivers
#
# CONFIG_MXC_SECURITY_SCC is not set
# CONFIG_MXC_SECURITY_RNG is not set
# CONFIG_MXC_SECURITY_RTIC is not set
#
# MXC MPEG4 Encoder Kernel module support
#
# CONFIG_MXC_HMP4E is not set
#
# MXC HARDWARE EVENT
#
CONFIG_MXC_HWEVENT=y
#
# MXC VPU(Video Processing Unit) support
#
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
CONFIG_AUTOFS4_FS=m
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
CONFIG_INSTRUMENTATION=y
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
CONFIG_OPROFILE_ARMV6=y
CONFIG_OPROFILE_ARM11_CORE=y
CONFIG_OPROFILE_ARM11_EVTMON=y
# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_FRAME_POINTER=y
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_USER is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

1828
arch/arm/configs/imx37_3stack_defconfig Normal file
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File diff suppressed because it is too large Load Diff

1954
arch/arm/configs/imx51_defconfig Normal file
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File diff suppressed because it is too large Load Diff

28
arch/arm/include/asm/mach/keypad.h Normal file
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@@ -0,0 +1,28 @@
/*
* include/asm-arm/mach/keypad.h
*
* Generic Keypad struct
*
* Author: Armin Kuster <Akuster@mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_MACH_KEYPAD_H_
#define __ASM_MACH_KEYPAD_H_
#include <linux/input.h>
struct keypad_data {
u16 rowmax;
u16 colmax;
u32 irq;
u16 delay;
u16 learning;
u16 *matrix;
};
#endif /* __ARM_MACH_KEYPAD_H_ */

96
arch/arm/mach-mx25/Kconfig Normal file
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@@ -0,0 +1,96 @@
menu "MX25 Options"
depends on ARCH_MX25
config MX25_OPTIONS
bool
default y
select CPU_ARM926T
select USB_ARCH_HAS_EHCI
config MACH_MX25_3DS
bool "Support MX25 3STACK platforms"
default y
help
Include support for MX25 3STACK platform. This includes specific
configurations for the board and its peripherals.
config MX25_DOZE_DURING_IDLE
bool "Enter Doze mode during idle"
help
Turning on this option will put the CPU into Doze mode during idle.
The default is to enter Wait mode during idle. Doze mode during
idle will save additional power over Wait mode.
config MXC_SDMA_API
bool "Use SDMA API"
default y
help
This selects the Freescale MXC SDMA API.
If unsure, say N.
menu "SDMA options"
depends on MXC_SDMA_API
config SDMA_IRAM
bool "Use Internal RAM for SDMA transfer"
default n
help
Support Internal RAM as SDMA buffer or control structures
config SDMA_IRAM_SIZE
hex "Reserved bytes of IRAM for SDMA (0x800-0x1000)"
range 0x800 0x1000
depends on SDMA_IRAM
default "0x1000"
help
Set the size of IRAM for SDMA. It must be a multiple of 512bytes.
endmenu
config ARCH_MXC_HAS_NFC_V2
bool "MXC NFC Hardware Version 2"
depends on ARCH_MX25
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 2
If unsure, say N.
config ARCH_MXC_HAS_NFC_V2_1
bool "MXC NFC Hardware Version 2.1"
depends on ARCH_MXC_HAS_NFC_V2
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 2.1
If unsure, say N.
menu "Device options"
config I2C_MXC_SELECT1
bool "Enable I2C1 module"
default y
depends on I2C_MXC
help
Enable MX25 I2C1 module.
config I2C_MXC_SELECT2
bool "Enable I2C2 module"
default n
depends on I2C_MXC
help
Enable MX25 I2C2 module.
config I2C_MXC_SELECT3
bool "Enable I2C3 module"
default n
depends on I2C_MXC
help
Enable MX25 I2C3 module.
config FLEXCAN_MXC_SELECT1
bool "Enable FlexCAN1 module"
depends on CAN_FLEXCAN
help
Enable MX25 FlexCAN1 module.
endmenu
endmenu

18
arch/arm/mach-mx25/Makefile Normal file
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@@ -0,0 +1,18 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := system.o iomux.o cpu.o mm.o clock.o bus_freq.o devices.o serial.o
obj-$(CONFIG_MXC_SDMA_API) += dma.o
obj-$(CONFIG_SPI_MXC) += mx25_3stack_cpld.o
obj-$(CONFIG_MACH_MX25_3DS) += mx25_3stack.o mx25_3stack_gpio.o mx25_3stack_pmic_mc34704.o
obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o
obj-$(CONFIG_PM) += pm.o
ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
obj-y += usb_dr.o
endif

3
arch/arm/mach-mx25/Makefile.boot Normal file
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@@ -0,0 +1,3 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

173
arch/arm/mach-mx25/board-mx25_3stack.h Normal file
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@@ -0,0 +1,173 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__
#define __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__
#ifdef CONFIG_MACH_MX25_3DS
/*!
* @defgroup BRDCFG_MX25 Board Configuration Options
* @ingroup MSL_MX25
*/
/*!
* @file mach-mx25/board-mx25_3stack.h
*
* @brief This file contains all the board level configuration options.
*
* It currently hold the options defined for MX25 3STACK Platform.
*
* @ingroup BRDCFG_MX25
*/
/*
* Include Files
*/
#include <mach/mxc_uart.h>
/*!
* @name MXC UART board-level configurations
*/
/*! @{ */
/* UART 1 configuration */
/*!
* This define specifies if the UART port is configured to be in DTE or
* DCE mode. There exists a define like this for each UART port. Valid
* values that can be used are \b MODE_DTE or \b MODE_DCE.
*/
#define UART1_MODE MODE_DCE
/*!
* This define specifies if the UART is to be used for IRDA. There exists a
* define like this for each UART port. Valid values that can be used are
* \b IRDA or \b NO_IRDA.
*/
#define UART1_IR NO_IRDA
/*!
* This define is used to enable or disable a particular UART port. If
* disabled, the UART will not be registered in the file system and the user
* will not be able to access it. There exists a define like this for each UART
* port. Specify a value of 1 to enable the UART and 0 to disable it.
*/
#define UART1_ENABLED 1
/*! @} */
/* UART 2 configuration */
#define UART2_MODE MODE_DCE
#define UART2_IR NO_IRDA
#define UART2_ENABLED 1
/* UART 3 configuration */
#define UART3_MODE MODE_DTE
#define UART3_IR NO_IRDA
#define UART3_ENABLED 0
/* UART 4 configuration */
#define UART4_MODE MODE_DTE
#define UART4_IR NO_IRDA
#define UART4_ENABLED 0
/* UART 5 configuration */
#define UART5_MODE MODE_DTE
#define UART5_IR NO_IRDA
#define UART5_ENABLED 0
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
/*!
* @name debug board parameters
*/
/*! @{ */
/*!
* Base address of debug board
*/
#define DEBUG_BASE_ADDRESS 0x78000000 /* Use a dummy base address */
/* External ethernet LAN9217 base address */
#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS
/* External UART */
#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x08000)
#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000)
#define BOARD_IO_ADDR 0x20000
/* LED switchs */
#define LED_SWITCH_REG (BOARD_IO_ADDR + 0x00)
/* buttons */
#define SWITCH_BUTTON_REG (BOARD_IO_ADDR + 0x08)
/* status, interrupt */
#define INTR_STATUS_REG (BOARD_IO_ADDR + 0x10)
#define INTR_RESET_REG (BOARD_IO_ADDR + 0x20)
/*CPLD configuration*/
#define CONFIG1_REG (BOARD_IO_ADDR + 0x28)
#define CONFIG2_REG (BOARD_IO_ADDR + 0x30)
/*interrupt mask */
#define INTR_MASK_REG (BOARD_IO_ADDR + 0x38)
/* magic word for debug CPLD */
#define MAGIC_NUMBER1_REG (BOARD_IO_ADDR + 0x40)
#define MAGIC_NUMBER2_REG (BOARD_IO_ADDR + 0x48)
/* CPLD code version */
#define CPLD_CODE_VER_REG (BOARD_IO_ADDR + 0x50)
/* magic word for debug CPLD */
#define MAGIC3_NUMBER3_REG (BOARD_IO_ADDR + 0x58)
/* module reset register*/
#define CONTROL_REG (BOARD_IO_ADDR + 0x60)
/* CPU ID and Personality ID*/
#define IDENT_REG (BOARD_IO_ADDR + 0x68)
/* For interrupts like xuart, enet etc */
#define EXPIO_PARENT_INT MX25_PIN_GPIO1_1
#define EXPIO_INT_ENET_INT (MXC_BOARD_IRQ_START + 0)
#define EXPIO_INT_XUARTA_INT (MXC_BOARD_IRQ_START + 1)
#define EXPIO_INT_XUARTB_INT (MXC_BOARD_IRQ_START + 2)
/*! This is System IRQ used by LAN9217 for interrupt generation taken
* from platform.h
*/
#define LAN9217_IRQ EXPIO_INT_ENET_INT
/*! This is base virtual address of debug board*/
extern unsigned int mx25_3stack_board_io;
#define MXC_BD_LED1 (1 << 0)
#define MXC_BD_LED2 (1 << 1)
#define MXC_BD_LED3 (1 << 2)
#define MXC_BD_LED4 (1 << 3)
#define MXC_BD_LED5 (1 << 4)
#define MXC_BD_LED6 (1 << 5)
#define MXC_BD_LED7 (1 << 6)
#define MXC_BD_LED8 (1 << 7)
#define MXC_BD_LED_ON(led)
#define MXC_BD_LED_OFF(led)
#define MXC_DEFAULT_INTENSITY 127
#define MXC_INTENSITY_OFF 0
/*! @} */
extern void mx25_3stack_gpio_init(void) __init;
extern int headphone_det_status(void);
extern void sgtl5000_enable_amp(void);
extern unsigned int sdhc_get_card_det_status(struct device *dev);
extern int sdhc_write_protect(struct device *dev);
extern void gpio_can_active(int id);
extern void gpio_can_inactive(int id);
extern struct flexcan_platform_data flexcan_data[];
extern void mx2fb_set_brightness(uint8_t);
extern int __init mx25_3stack_init_mc34704(void);
#endif /* CONFIG_MACH_MX25_3DS */
#endif /* __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__ */

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/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file bus_freq.c
*
* @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module
* and DVFS CORE module.
*
* The APIs are for setting bus frequency to low or high.
*
* @ingroup PM
*/
#include <linux/proc_fs.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <mach/clock.h>
#include <mach/hardware.h>
int low_bus_freq_mode;
int high_bus_freq_mode;
char *gp_reg_id = "REG3_CORE";
int set_low_bus_freq(void)
{
return 0;
}
int set_high_bus_freq(int high_bus_freq)
{
return 0;
}
int low_freq_bus_used(void)
{
return 0;
}
/*!
* This is the probe routine for the bus frequency driver.
*
* @param pdev The platform device structure
*
* @return The function returns 0 on success
*
*/
static int __devinit busfreq_probe(struct platform_device *pdev)
{
low_bus_freq_mode = 0;
high_bus_freq_mode = 0;
return 0;
}
static struct platform_driver busfreq_driver = {
.driver = {
.name = "busfreq",
},
.probe = busfreq_probe,
};
/*!
* Initialise the busfreq_driver.
*
* @return The function always returns 0.
*/
static int __init busfreq_init(void)
{
if (platform_driver_register(&busfreq_driver) != 0) {
printk(KERN_ERR "busfreq_driver register failed\n");
return -ENODEV;
}
printk(KERN_INFO "Bus freq driver module loaded\n");
return 0;
}
static void __exit busfreq_cleanup(void)
{
/* Unregister the device structure */
platform_driver_unregister(&busfreq_driver);
}
module_init(busfreq_init);
module_exit(busfreq_cleanup);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("BusFreq driver");
MODULE_LICENSE("GPL");

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx25/cpu.c
*
* @brief This file contains the CPU initialization code.
*
* @ingroup MSL_MX25
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/io.h>
/*!
* CPU initialization. It is called by fixup_mxc_board()
*/
void __init mxc_cpu_init(void)
{
if (!system_rev)
mxc_set_system_rev(0x25, CHIP_REV_1_0);
}
static int __init post_cpu_init(void)
{
void __iomem *base;
unsigned int reg;
base = IO_ADDRESS(AIPS1_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
base = IO_ADDRESS(AIPS2_BASE_ADDR);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
return 0;
}
postcore_initcall(post_cpu_init);

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX25_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX25_CRM_REGS_H__
#include <mach/hardware.h>
#define MXC_CCM_BASE ((char *)IO_ADDRESS(CCM_BASE_ADDR))
/* Register offsets */
#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x00)
#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x04)
#define MXC_CCM_CCTL (MXC_CCM_BASE + 0x08)
#define MXC_CCM_CGCR0 (MXC_CCM_BASE + 0x0C)
#define MXC_CCM_CGCR1 (MXC_CCM_BASE + 0x10)
#define MXC_CCM_CGCR2 (MXC_CCM_BASE + 0x14)
#define MXC_CCM_PCDR0 (MXC_CCM_BASE + 0x18)
#define MXC_CCM_PCDR1 (MXC_CCM_BASE + 0x1C)
#define MXC_CCM_PCDR2 (MXC_CCM_BASE + 0x20)
#define MXC_CCM_PCDR3 (MXC_CCM_BASE + 0x24)
#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x28)
#define MXC_CCM_CRDR (MXC_CCM_BASE + 0x2C)
#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x30)
#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x34)
#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x38)
#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x3C)
#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x40)
#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x44)
#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x48)
#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x4C)
#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x50)
#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x54)
#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x58)
#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x5C)
#define MXC_CCM_PMCR2 (MXC_CCM_BASE + 0x60)
#define MXC_CCM_MCR (MXC_CCM_BASE + 0x64)
#define MXC_CCM_LPIMR0 (MXC_CCM_BASE + 0x68)
#define MXC_CCM_LPIMR1 (MXC_CCM_BASE + 0x6C)
#define MXC_CCM_MPCTL_BRMO (1 << 31)
#define MXC_CCM_MPCTL_PD_OFFSET 26
#define MXC_CCM_MPCTL_PD_MASK (0xf << 26)
#define MXC_CCM_MPCTL_MFD_OFFSET 16
#define MXC_CCM_MPCTL_MFD_MASK (0x3ff << 16)
#define MXC_CCM_MPCTL_MFI_OFFSET 10
#define MXC_CCM_MPCTL_MFI_MASK (0xf << 10)
#define MXC_CCM_MPCTL_MFN_OFFSET 0
#define MXC_CCM_MPCTL_MFN_MASK 0x3ff
#define MXC_CCM_MPCTL_LF (1 << 15)
#define MXC_CCM_UPCTL_BRMO (1 << 31)
#define MXC_CCM_UPCTL_PD_OFFSET 26
#define MXC_CCM_UPCTL_PD_MASK (0xf << 26)
#define MXC_CCM_UPCTL_MFD_OFFSET 16
#define MXC_CCM_UPCTL_MFD_MASK (0x3ff << 16)
#define MXC_CCM_UPCTL_MFI_OFFSET 10
#define MXC_CCM_UPCTL_MFI_MASK (0xf << 10)
#define MXC_CCM_UPCTL_MFN_OFFSET 0
#define MXC_CCM_UPCTL_MFN_MASK 0x3ff
#define MXC_CCM_UPCTL_LF (1 << 15)
#define MXC_CCM_CCTL_ARM_OFFSET 30
#define MXC_CCM_CCTL_ARM_MASK (0x3 << 30)
#define MXC_CCM_CCTL_AHB_OFFSET 28
#define MXC_CCM_CCTL_AHB_MASK (0x3 << 28)
#define MXC_CCM_CCTL_MPLL_RST (1 << 27)
#define MXC_CCM_CCTL_UPLL_RST (1 << 26)
#define MXC_CCM_CCTL_LP_CTL_OFFSET 24
#define MXC_CCM_CCTL_LP_CTL_MASK (0x3 << 24)
#define MXC_CCM_CCTL_LP_MODE_RUN (0x0 << 24)
#define MXC_CCM_CCTL_LP_MODE_WAIT (0x1 << 24)
#define MXC_CCM_CCTL_LP_MODE_DOZE (0x2 << 24)
#define MXC_CCM_CCTL_LP_MODE_STOP (0x3 << 24)
#define MXC_CCM_CCTL_UPLL_DISABLE (1 << 23)
#define MXC_CCM_CCTL_MPLL_BYPASS (1 << 22)
#define MXC_CCM_CCTL_USB_DIV_OFFSET 16
#define MXC_CCM_CCTL_USB_DIV_MASK (0x3 << 16)
#define MXC_CCM_CCTL_CG_CTRL (1 << 15)
#define MXC_CCM_CCTL_ARM_SRC (1 << 14)
#define MXC_CCM_CCTL_ARM_SRC_OFFSET 14
#define MXC_CCM_CGCR0_HCLK_ATA_OFFSET 16
#define MXC_CCM_CGCR0_HCLK_BROM_OFFSET 17
#define MXC_CCM_CGCR0_HCLK_CSI_OFFSET 18
#define MXC_CCM_CGCR0_HCLK_EMI_OFFSET 19
#define MXC_CCM_CGCR0_HCLK_ESAI_OFFSET 20
#define MXC_CCM_CGCR0_HCLK_ESDHC1_OFFSET 21
#define MXC_CCM_CGCR0_HCLK_ESDHC2_OFFSET 22
#define MXC_CCM_CGCR0_HCLK_FEC_OFFSET 23
#define MXC_CCM_CGCR0_HCLK_LCDC_OFFSET 24
#define MXC_CCM_CGCR0_HCLK_RTIC_OFFSET 25
#define MXC_CCM_CGCR0_HCLK_SDMA_OFFSET 26
#define MXC_CCM_CGCR0_HCLK_SLCDC_OFFSET 27
#define MXC_CCM_CGCR0_HCLK_USBOTG_OFFSET 28
#define MXC_CCM_CGCR0_PER_CSI_OFFSET 0
#define MXC_CCM_CGCR0_PER_EPIT_OFFSET 1
#define MXC_CCM_CGCR0_PER_ESAI_OFFSET 2
#define MXC_CCM_CGCR0_PER_ESDHC1_OFFSET 3
#define MXC_CCM_CGCR0_PER_ESDHC2_OFFSET 4
#define MXC_CCM_CGCR0_PER_GPT_OFFSET 5
#define MXC_CCM_CGCR0_PER_I2C_OFFSET 6
#define MXC_CCM_CGCR0_PER_LCDC_OFFSET 7
#define MXC_CCM_CGCR0_PER_NFC_OFFSET 8
#define MXC_CCM_CGCR0_PER_OWIRE_OFFSET 9
#define MXC_CCM_CGCR0_PER_PWM_OFFSET 10
#define MXC_CCM_CGCR0_PER_SIM1_OFFSET 11
#define MXC_CCM_CGCR0_PER_SIM2_OFFSET 12
#define MXC_CCM_CGCR0_PER_SSI1_OFFSET 13
#define MXC_CCM_CGCR0_PER_SSI2_OFFSET 14
#define MXC_CCM_CGCR0_PER_UART_OFFSET 15
#define MXC_CCM_CGCR1_AUDMUX_OFFSET 0
#define MXC_CCM_CGCR1_ATA_OFFSET 1
#define MXC_CCM_CGCR1_CAN1_OFFSET 2
#define MXC_CCM_CGCR1_CAN2_OFFSET 3
#define MXC_CCM_CGCR1_CSI_OFFSET 4
#define MXC_CCM_CGCR1_CSPI1_OFFSET 5
#define MXC_CCM_CGCR1_CSPI2_OFFSET 6
#define MXC_CCM_CGCR1_CSPI3_OFFSET 7
#define MXC_CCM_CGCR1_DRYICE_OFFSET 8
#define MXC_CCM_CGCR1_ECT_OFFSET 9
#define MXC_CCM_CGCR1_EPIT1_OFFSET 10
#define MXC_CCM_CGCR1_EPIT2_OFFSET 11
#define MXC_CCM_CGCR1_ESAI_OFFSET 12
#define MXC_CCM_CGCR1_ESDHC1_OFFSET 13
#define MXC_CCM_CGCR1_ESDHC2_OFFSET 14
#define MXC_CCM_CGCR1_FEC_OFFSET 15
#define MXC_CCM_CGCR1_GPIO1_OFFSET 16
#define MXC_CCM_CGCR1_GPIO2_OFFSET 17
#define MXC_CCM_CGCR1_GPIO3_OFFSET 18
#define MXC_CCM_CGCR1_GPT1_OFFSET 19
#define MXC_CCM_CGCR1_GPT2_OFFSET 20
#define MXC_CCM_CGCR1_GPT3_OFFSET 21
#define MXC_CCM_CGCR1_GPT4_OFFSET 22
#define MXC_CCM_CGCR1_I2C1_OFFSET 23
#define MXC_CCM_CGCR1_I2C2_OFFSET 24
#define MXC_CCM_CGCR1_I2C3_OFFSET 25
#define MXC_CCM_CGCR1_IIM_OFFSET 26
#define MXC_CCM_CGCR1_IOMUXC_OFFSET 27
#define MXC_CCM_CGCR1_KPP_OFFSET 28
#define MXC_CCM_CGCR1_LCDC_OFFSET 29
#define MXC_CCM_CGCR1_OWIRE_OFFSET 30
#define MXC_CCM_CGCR1_PWM1_OFFSET 31
#define MXC_CCM_CGCR2_PWM2_OFFSET (32-32)
#define MXC_CCM_CGCR2_PWM3_OFFSET (33-32)
#define MXC_CCM_CGCR2_PWM4_OFFSET (34-32)
#define MXC_CCM_CGCR2_RNGB_OFFSET (35-32)
#define MXC_CCM_CGCR2_RTIC_OFFSET (36-32)
#define MXC_CCM_CGCR2_SCC_OFFSET (37-32)
#define MXC_CCM_CGCR2_SDMA_OFFSET (38-32)
#define MXC_CCM_CGCR2_SIM1_OFFSET (39-32)
#define MXC_CCM_CGCR2_SIM2_OFFSET (40-32)
#define MXC_CCM_CGCR2_SLCDC_OFFSET (41-32)
#define MXC_CCM_CGCR2_SPBA_OFFSET (42-32)
#define MXC_CCM_CGCR2_SSI1_OFFSET (43-32)
#define MXC_CCM_CGCR2_SSI2_OFFSET (44-32)
#define MXC_CCM_CGCR2_TCHSCRN_OFFSET (45-32)
#define MXC_CCM_CGCR2_UART1_OFFSET (46-32)
#define MXC_CCM_CGCR2_UART2_OFFSET (47-32)
#define MXC_CCM_CGCR2_UART3_OFFSET (48-32)
#define MXC_CCM_CGCR2_UART4_OFFSET (49-32)
#define MXC_CCM_CGCR2_UART5_OFFSET (50-32)
#define MXC_CCM_CGCR2_WDOG_OFFSET (51-32)
#define MXC_CCM_CGCR0_STOP_MODE_MASK \
((1 << MXC_CCM_CGCR0_HCLK_SLCDC_OFFSET) | \
(1 << MXC_CCM_CGCR0_HCLK_RTIC_OFFSET) | \
(1 << MXC_CCM_CGCR0_HCLK_EMI_OFFSET) | \
(1 << MXC_CCM_CGCR0_HCLK_BROM_OFFSET))
#define MXC_CCM_CGCR1_STOP_MODE_MASK ((1 << MXC_CCM_CGCR1_IIM_OFFSET) | \
(1 << MXC_CCM_CGCR1_CAN2_OFFSET) | \
(1 << MXC_CCM_CGCR1_CAN1_OFFSET))
#define MXC_CCM_CGCR2_STOP_MODE_MASK ((1 << MXC_CCM_CGCR2_SPBA_OFFSET) | \
(1 << MXC_CCM_CGCR2_SDMA_OFFSET) | \
(1 << MXC_CCM_CGCR2_RTIC_OFFSET))
#define MXC_CCM_PCDR1_PERDIV1_MASK 0x3f
#define MXC_CCM_RCSR_NF16B (1 << 14)
#define MXC_CCM_PMCR2_VSTBY (1 << 17)
#define MXC_CCM_PMCR2_OSC24M_DOWN (1 << 16)
#define MXC_CCM_MCR_USB_XTAL_MUX_OFFSET 31
#define MXC_CCM_MCR_CLKO_EN_OFFSET 30
#define MXC_CCM_MCR_CLKO_DIV_OFFSET 24
#define MXC_CCM_MCR_CLKO_DIV_MASK (0x3F << 24)
#define MXC_CCM_MCR_CLKO_SEL_OFFSET 20
#define MXC_CCM_MCR_CLKO_SEL_MASK (0xF << 20)
#define MXC_CCM_MCR_ESAI_CLK_MUX_OFFSET 19
#define MXC_CCM_MCR_SSI2_CLK_MUX_OFFSET 18
#define MXC_CCM_MCR_SSI1_CLK_MUX_OFFSET 17
#define MXC_CCM_MCR_USB_CLK_MUX_OFFSET 16
#define MXC_CCM_MCR_PER_CLK_MUX_MASK (0xFFFF << 0)
#define MXC_CCM_LPIMR0_MASK 0xFFFFFFFF
#define MXC_CCM_LPIMR1_MASK 0xFFFFFFFF
#endif /* __ARCH_ARM_MACH_MX25_CRM_REGS_H__ */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spba.h>
#include <mach/sdma.h>
#include "iomux.h"
#include "sdma_script_code.h"
#include "board-mx25_3stack.h"
void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr)
{
sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR;
sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR;
sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR;
sdma_script_addr->mxc_sdma_per_2_per_addr = -1;
sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR;
sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR;
sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR;
sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR;
sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR;
sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;
sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = -1;
sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR;
sdma_script_addr->mxc_sdma_descrambler_addr = -1;
sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code;
sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR;
}
static void mxc_nop_release(struct device *dev)
{
/* Nothing */
}
#if defined(CONFIG_RTC_DRV_IMXDI) || defined(CONFIG_RTC_DRV_IMXDI_MODULE)
static struct resource rtc_resources[] = {
{
.start = SRTC_BASE_ADDR,
.end = SRTC_BASE_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
{
.start = MXC_INT_DRYICE_NORM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device imxdi_rtc_device = {
.name = "imxdi_rtc",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static void mxc_init_rtc(void)
{
(void)platform_device_register(&imxdi_rtc_device);
}
#else
static inline void mxc_init_rtc(void)
{
}
#endif
#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = WDOG1_BASE_ADDR,
.end = WDOG1_BASE_ADDR + 0x30,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mxc_wdt_device = {
.name = "mxc_wdt",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
static void mxc_init_wdt(void)
{
(void)platform_device_register(&mxc_wdt_device);
}
#else
static inline void mxc_init_wdt(void)
{
}
#endif
/* SPI controller and device data */
#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)
#ifdef CONFIG_SPI_MXC_SELECT1
/*!
* Resource definition for the CSPI1
*/
static struct resource mxcspi1_resources[] = {
[0] = {
.start = CSPI1_BASE_ADDR,
.end = CSPI1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_CSPI1,
.end = MXC_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC CSPI1 */
static struct mxc_spi_master mxcspi1_data = {
.maxchipselect = 4,
.spi_version = 7,
};
/*! Device Definition for MXC CSPI1 */
static struct platform_device mxcspi1_device = {
.name = "mxc_spi",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxcspi1_data,
},
.num_resources = ARRAY_SIZE(mxcspi1_resources),
.resource = mxcspi1_resources,
};
#endif /* CONFIG_SPI_MXC_SELECT1 */
#ifdef CONFIG_SPI_MXC_SELECT2
/*!
* Resource definition for the CSPI2
*/
static struct resource mxcspi2_resources[] = {
[0] = {
.start = CSPI2_BASE_ADDR,
.end = CSPI2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_CSPI2,
.end = MXC_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC CSPI2 */
static struct mxc_spi_master mxcspi2_data = {
.maxchipselect = 4,
.spi_version = 7,
};
/*! Device Definition for MXC CSPI2 */
static struct platform_device mxcspi2_device = {
.name = "mxc_spi",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxcspi2_data,
},
.num_resources = ARRAY_SIZE(mxcspi2_resources),
.resource = mxcspi2_resources,
};
#endif /* CONFIG_SPI_MXC_SELECT2 */
#ifdef CONFIG_SPI_MXC_SELECT3
/*!
* Resource definition for the CSPI3
*/
static struct resource mxcspi3_resources[] = {
[0] = {
.start = CSPI3_BASE_ADDR,
.end = CSPI3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_CSPI3,
.end = MXC_INT_CSPI3,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC CSPI3 */
static struct mxc_spi_master mxcspi3_data = {
.maxchipselect = 4,
.spi_version = 7,
};
/*! Device Definition for MXC CSPI3 */
static struct platform_device mxcspi3_device = {
.name = "mxc_spi",
.id = 2,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxcspi3_data,
},
.num_resources = ARRAY_SIZE(mxcspi3_resources),
.resource = mxcspi3_resources,
};
#endif /* CONFIG_SPI_MXC_SELECT3 */
static inline void mxc_init_spi(void)
{
spba_take_ownership(SPBA_CSPI2, SPBA_MASTER_A);
spba_take_ownership(SPBA_CSPI3, SPBA_MASTER_A);
#ifdef CONFIG_SPI_MXC_SELECT1
if (platform_device_register(&mxcspi1_device) < 0)
printk(KERN_ERR "Error: Registering the SPI Controller_1\n");
#endif /* CONFIG_SPI_MXC_SELECT1 */
#ifdef CONFIG_SPI_MXC_SELECT2
if (platform_device_register(&mxcspi2_device) < 0)
printk(KERN_ERR "Error: Registering the SPI Controller_2\n");
#endif /* CONFIG_SPI_MXC_SELECT2 */
#ifdef CONFIG_SPI_MXC_SELECT3
if (platform_device_register(&mxcspi3_device) < 0)
printk(KERN_ERR "Error: Registering the SPI Controller_3\n");
#endif /* CONFIG_SPI_MXC_SELECT3 */
}
#else
static inline void mxc_init_spi(void)
{
}
#endif
/* I2C controller and device data */
#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
#ifdef CONFIG_I2C_MXC_SELECT1
/*!
* Resource definition for the I2C1
*/
static struct resource mxci2c1_resources[] = {
[0] = {
.start = I2C_BASE_ADDR,
.end = I2C_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C,
.end = MXC_INT_I2C,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c1_data = {
.i2c_clk = 100000,
};
#endif
#ifdef CONFIG_I2C_MXC_SELECT2
/*!
* Resource definition for the I2C2
*/
static struct resource mxci2c2_resources[] = {
[0] = {
.start = I2C2_BASE_ADDR,
.end = I2C2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C2,
.end = MXC_INT_I2C2,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c2_data = {
.i2c_clk = 100000,
};
#endif
#ifdef CONFIG_I2C_MXC_SELECT3
/*!
* Resource definition for the I2C3
*/
static struct resource mxci2c3_resources[] = {
[0] = {
.start = I2C3_BASE_ADDR,
.end = I2C3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C3,
.end = MXC_INT_I2C3,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c3_data = {
.i2c_clk = 100000,
};
#endif
/*! Device Definition for MXC I2C1 */
static struct platform_device mxci2c_devices[] = {
#ifdef CONFIG_I2C_MXC_SELECT1
{
.name = "mxc_i2c",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c1_data,
},
.num_resources = ARRAY_SIZE(mxci2c1_resources),
.resource = mxci2c1_resources,},
#endif
#ifdef CONFIG_I2C_MXC_SELECT2
{
.name = "mxc_i2c",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c2_data,
},
.num_resources = ARRAY_SIZE(mxci2c2_resources),
.resource = mxci2c2_resources,},
#endif
#ifdef CONFIG_I2C_MXC_SELECT3
{
.name = "mxc_i2c",
.id = 2,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c3_data,
},
.num_resources = ARRAY_SIZE(mxci2c3_resources),
.resource = mxci2c3_resources,},
#endif
};
static inline void mxc_init_i2c(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) {
if (platform_device_register(&mxci2c_devices[i]) < 0)
dev_err(&mxci2c_devices[i].dev,
"Unable to register I2C device\n");
}
}
#else
static inline void mxc_init_i2c(void)
{
}
#endif
struct mxc_gpio_port mxc_gpio_ports[] = {
[0] = {
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START
},
[1] = {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32
},
[2] = {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
},
[3] = {
.chip.label = "gpio-3",
.base = IO_ADDRESS(GPIO4_BASE_ADDR),
.irq = MXC_INT_GPIO4,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
}
};
int __init mxc_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
}
static inline void mxc_init_ssi(void)
{
/* SPBA configuration for SSI - SDMA and MCU are set */
spba_take_ownership(SPBA_SSI1, SPBA_MASTER_A | SPBA_MASTER_C);
spba_take_ownership(SPBA_SSI2, SPBA_MASTER_A | SPBA_MASTER_C);
}
static struct platform_device mxc_dma_device = {
.name = "mxc_dma",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
};
static inline void mxc_init_dma(void)
{
(void)platform_device_register(&mxc_dma_device);
}
/* imx adc driver */
#if defined(CONFIG_IMX_ADC) || defined(CONFIG_IMX_ADC_MODULE)
static struct resource imx_adc_resources[] = {
[0] = {
.start = MXC_INT_TSC,
.end = MXC_INT_TSC,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TSC_BASE_ADDR,
.end = TSC_BASE_ADDR + PAGE_SIZE,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device imx_adc_device = {
.name = "imx_adc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_adc_resources),
.resource = imx_adc_resources,
.dev = {
.release = NULL,
},
};
static void imx_init_adc(void)
{
(void)platform_device_register(&imx_adc_device);
}
#else
static void imx_init_adc(void)
{
}
#endif
#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
static struct resource flexcan1_resources[] = {
{
.start = CAN1_BASE_ADDR,
.end = CAN1_BASE_ADDR + 0x97F,
.flags = IORESOURCE_MEM,},
{
.start = MXC_INT_CAN1,
.end = MXC_INT_CAN1,
.flags = IORESOURCE_IRQ,}
};
static struct resource flexcan2_resources[] = {
{
.start = CAN3_BASE_ADDR,
.end = CAN3_BASE_ADDR + 0x97F,
.flags = IORESOURCE_MEM,},
{
.start = MXC_INT_CAN2,
.end = MXC_INT_CAN2,
.flags = IORESOURCE_IRQ,}
};
static struct platform_device flexcan_devices[] = {
{
.name = "FlexCAN",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &flexcan_data[0],
},
.num_resources = ARRAY_SIZE(flexcan1_resources),
.resource = flexcan1_resources,},
{
.name = "FlexCAN",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &flexcan_data[1],
},
.num_resources = ARRAY_SIZE(flexcan2_resources),
.resource = flexcan2_resources,},
};
static inline void mxc_init_flexcan(void)
{
#ifdef CONFIG_FLEXCAN_MXC_SELECT1
/* MX25 3stack doesn't use CAN1 */
platform_device_register(&flexcan_devices[0]);
#endif
platform_device_register(&flexcan_devices[1]);
}
#else
static inline void mxc_init_flexcan(void)
{
}
#endif
static struct platform_device mxc_alsa_surround_device = {
.name = "imx-3stack-wm8580",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
};
static void mxc_init_surround_audio(void)
{
platform_device_register(&mxc_alsa_surround_device);
}
#if defined(CONFIG_MXC_IIM) || defined(CONFIG_MXC_IIM_MODULE)
static struct resource mxc_iim_resources[] = {
{
.start = IIM_BASE_ADDR,
.end = IIM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mxc_iim_device = {
.name = "mxc_iim",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(mxc_iim_resources),
.resource = mxc_iim_resources
};
static inline void mxc_init_iim(void)
{
if (platform_device_register(&mxc_iim_device) < 0)
dev_err(&mxc_iim_device.dev,
"Unable to register mxc iim device\n");
}
#else
static inline void mxc_init_iim(void)
{
}
#endif
static int __init mxc_init_devices(void)
{
mxc_init_wdt();
mxc_init_spi();
mxc_init_i2c();
mxc_init_dma();
mxc_init_ssi();
mxc_init_surround_audio();
mxc_init_rtc();
imx_init_adc();
mxc_init_flexcan();
mxc_init_iim();
return 0;
}
arch_initcall(mxc_init_devices);

663
arch/arm/mach-mx25/dma.c Normal file
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@@ -0,0 +1,663 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/device.h>
#include <asm/dma.h>
#include <mach/hardware.h>
#include "serial.h"
#ifdef CONFIG_SND_MXC_SOC_IRAM
#define soc_trans_type int_2_per
#else
#define soc_trans_type emi_2_per
#endif
#define MXC_SSI_TX0_REG 0x0
#define MXC_SSI_TX1_REG 0x4
#define MXC_SSI_RX0_REG 0x8
#define MXC_SSI_RX1_REG 0xC
#define MXC_SSI_TXFIFO_WML 0x4
#define MXC_SSI_RXFIFO_WML 0x6
#define MXC_ESAI_TX_REG 0x00
#define MXC_ESAI_RX_REG 0x04
#define MXC_ESAI_FIFO_WML 0x40
struct mxc_sdma_info_entry_s {
mxc_dma_device_t device;
mxc_sdma_channel_params_t *chnl_info;
};
static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = {
.chnl_params = {
.watermark_level = UART1_UFCR_RXTL,
.per_address = UART1_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART1_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART1_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = {
.chnl_params = {
.watermark_level = UART1_UFCR_TXTL,
.per_address = UART1_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART1_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART1_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = {
.chnl_params = {
.watermark_level = UART2_UFCR_RXTL,
.per_address = UART2_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART2_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART2_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = {
.chnl_params = {
.watermark_level = UART2_UFCR_TXTL,
.per_address = UART2_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART2_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART2_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = {
.chnl_params = {
.watermark_level = UART3_UFCR_RXTL,
.per_address = UART3_BASE_ADDR,
.peripheral_type = UART_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART3_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART3_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = {
.chnl_params = {
.watermark_level = UART3_UFCR_TXTL,
.per_address = UART3_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART3_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART3_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = {
.chnl_params = {
.watermark_level = UART4_UFCR_RXTL,
.per_address = UART4_BASE_ADDR,
.peripheral_type = UART_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART4_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART4_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = {
.chnl_params = {
.watermark_level = UART4_UFCR_TXTL,
.per_address = UART4_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART4_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART4_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = {
.chnl_params = {
.watermark_level = UART5_UFCR_RXTL,
.per_address = UART5_BASE_ADDR,
.peripheral_type = UART_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART5_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART5_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = {
.chnl_params = {
.watermark_level = UART5_UFCR_TXTL,
.per_address = UART5_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART5_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART5_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX0,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX0,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX0,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX0,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX0,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX0,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX0,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX0,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX0,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX0,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX0,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX0,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_memory_params = {
.chnl_params = {
.peripheral_type = MEMORY,
.transfer_type = emi_2_emi,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MEMORY,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = {
.chnl_params = {
.watermark_level = MXC_ESAI_FIFO_WML,
.per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG,
.peripheral_type = ESAI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_ESAI_RX,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_ESAI_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = {
.chnl_params = {
.watermark_level = MXC_ESAI_FIFO_WML,
.per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
.peripheral_type = ESAI,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_ESAI_TX,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_ESAI_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = {
.chnl_params = {
.watermark_level = MXC_ESAI_FIFO_WML,
.per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG,
.peripheral_type = ESAI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_ESAI_RX,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_ESAI_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = {
.chnl_params = {
.watermark_level = MXC_ESAI_FIFO_WML,
.per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG,
.peripheral_type = ESAI,
.transfer_type = soc_trans_type,
.event_id = DMA_REQ_ESAI_TX,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_ESAI_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static struct mxc_sdma_info_entry_s mxc_sdma_active_dma_info[] = {
{MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params},
{MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params},
{MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params},
{MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params},
{MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params},
{MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params},
{MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params},
{MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params},
{MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params},
{MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params},
{MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params},
{MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params},
{MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params},
{MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params},
{MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params},
{MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params},
{MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params},
{MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params},
{MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params},
{MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params},
{MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params},
{MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params},
{MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params},
{MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params},
{MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params},
{MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params},
{MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params},
{MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params},
{MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params},
{MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params},
{MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params},
{MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params},
{MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params},
{MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params},
{MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params},
{MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params},
{MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params},
{MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params},
{MXC_DMA_MEMORY, &mxc_sdma_memory_params},
};
static int mxc_sdma_info_entrys =
sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]);
/*!
* This functions Returns the SDMA paramaters associated for a module
*
* @param channel_id the ID of the module requesting DMA
* @return returns the sdma parameters structure for the device
*/
mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t
channel_id)
{
struct mxc_sdma_info_entry_s *p = mxc_sdma_active_dma_info;
int i;
for (i = 0; i < mxc_sdma_info_entrys; i++, p++) {
if (p->device == channel_id)
return p->chnl_info;
}
return NULL;
}
EXPORT_SYMBOL(mxc_sdma_get_channel_params);
/*!
* This functions marks the SDMA channels that are statically allocated
*
* @param chnl the channel array used to store channel information
*/
void mxc_get_static_channels(mxc_dma_channel_t *chnl)
{
#ifdef CONFIG_SDMA_IRAM
int i;
for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++)
chnl[i].dynamic = 0;
#endif
}
EXPORT_SYMBOL(mxc_get_static_channels);

199
arch/arm/mach-mx25/iomux.c Normal file
View File

@@ -0,0 +1,199 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @defgroup GPIO_MX25 Board GPIO and Muxing Setup
* @ingroup MSL_MX25
*/
/*!
* @file mach-mx25/iomux.c
*
* @brief I/O Muxing control functions
*
* @ingroup GPIO_MX25
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "iomux.h"
/*!
* IOMUX register (base) addresses
*/
#define IOMUXGPR (IO_ADDRESS(IOMUXC_BASE_ADDR))
#define IOMUXSW_MUX_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x008)
#define IOMUXSW_MUX_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x228)
#define IOMUXSW_PAD_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x22C)
#define IOMUXSW_PAD_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x414)
#define IOMUXSW_INPUT_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x460)
#define IOMUXSW_INPUT_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x580)
#define MUX_PIN_NUM_MAX \
(((IOMUXSW_MUX_END - IOMUXSW_MUX_CTL) >> 2) + 1)
#define MUX_INPUT_NUM_MUX \
(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
static DEFINE_SPINLOCK(gpio_mux_lock);
static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX];
#define MUX_USED 0x80
/*!
* This function is used to configure a pin through the IOMUX module.
* FIXED ME: for backward compatible. Will be static function!
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param cfg an output function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 ret = 0;
u32 pin_index = PIN_TO_IOMUX_INDEX(pin);
void *mux_reg = IOMUXGPR + PIN_TO_IOMUX_MUX(pin);
u8 *rp;
BUG_ON(pin_index > MUX_PIN_NUM_MAX);
BUG_ON((mux_reg > IOMUXSW_MUX_END) || (mux_reg < IOMUXSW_MUX_CTL));
spin_lock(&gpio_mux_lock);
__raw_writel(cfg, mux_reg);
/*
* Log a warning if a pin changes ownership
*/
rp = iomux_pin_res_table + pin_index;
if (*rp && *rp != (cfg | MUX_USED)) {
/*Console: how to do */
printk(KERN_ERR "iomux_config_mux: Warning: iomux pin"
" config changed, index=%d register=%p, "
" prev=0x%x new=0x%x\n", pin_index, mux_reg,
*rp, cfg);
ret = -EINVAL;
}
*rp = cfg | MUX_USED;
spin_unlock(&gpio_mux_lock);
return ret;
}
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
int ret = iomux_config_mux(pin, cfg);
if (IOMUX_TO_GPIO(pin) < MXC_GPIO_IRQS) {
if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) ||
(((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) &&
((pin == MX25_PIN_GPIO_A) || (pin == MX25_PIN_GPIO_B) ||
(pin == MX25_PIN_GPIO_C) || (pin == MX25_PIN_GPIO_D) ||
(pin == MX25_PIN_GPIO_E) || (pin == MX25_PIN_GPIO_F))))
ret |= gpio_request(IOMUX_TO_GPIO(pin), NULL);
}
return ret;
}
EXPORT_SYMBOL(mxc_request_iomux);
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 pin_index = PIN_TO_IOMUX_INDEX(pin);
u8 *rp = iomux_pin_res_table + pin_index;
BUG_ON((pin_index > MUX_PIN_NUM_MAX));
*rp = 0;
if (IOMUX_TO_GPIO(pin) < MXC_GPIO_IRQS) {
if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) ||
(((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) &&
((pin == MX25_PIN_GPIO_A) || (pin == MX25_PIN_GPIO_B) ||
(pin == MX25_PIN_GPIO_C) || (pin == MX25_PIN_GPIO_D) ||
(pin == MX25_PIN_GPIO_E) || (pin == MX25_PIN_GPIO_F))))
gpio_free(IOMUX_TO_GPIO(pin));
}
}
EXPORT_SYMBOL(mxc_free_iomux);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b #iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
{
void *pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
BUG_ON((pad_reg > IOMUXSW_PAD_END) || (pad_reg < IOMUXSW_PAD_CTL));
__raw_writel(config, pad_reg);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en)
{
u32 l;
spin_lock(&gpio_mux_lock);
l = __raw_readl(IOMUXGPR);
if (en)
l |= gp;
else
l &= ~gp;
__raw_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
/*!
* This function configures input path.
*
* @param input index of input select register as defined in \b
* #iomux_input_select_t
* @param config the binary value of elements defined in \b
* #iomux_input_config_t
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
{
void *reg = IOMUXSW_INPUT_CTL + (input << 2);
BUG_ON(input >= MUX_INPUT_NUM_MUX);
__raw_writel(config, reg);
}
EXPORT_SYMBOL(mxc_iomux_set_input);

233
arch/arm/mach-mx25/iomux.h Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_MX25_IOMUX_H__
#define __MACH_MX25_IOMUX_H__
#include <linux/types.h>
#include <mach/gpio.h>
#include "mx25_pins.h"
/*!
* @file mach-mx25/iomux.h
*
* @brief I/O Muxing control definitions and functions
*
* @ingroup GPIO_MX25
*/
typedef unsigned int iomux_pin_name_t;
/*!
* IOMUX functions
* SW_MUX_CTL
*/
typedef enum iomux_pin_config {
MUX_CONFIG_FUNC = 0, /*!< used as function */
MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
} iomux_pin_cfg_t;
/*!
* IOMUX pad functions
* SW_PAD_CTL
*/
typedef enum iomux_pad_config {
PAD_CTL_DRV_3_3V = 0x0 << 13,
PAD_CTL_DRV_1_8V = 0x1 << 13,
PAD_CTL_HYS_CMOS = 0x0 << 8,
PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
PAD_CTL_PKE_NONE = 0x0 << 7,
PAD_CTL_PKE_ENABLE = 0x1 << 7,
PAD_CTL_PUE_KEEPER = 0x0 << 6,
PAD_CTL_PUE_PULL = 0x1 << 6,
PAD_CTL_PUE_PUD = 0x1 << 6,
PAD_CTL_100K_PD = 0x0 << 4,
PAD_CTL_47K_PU = 0x1 << 4,
PAD_CTL_100K_PU = 0x2 << 4,
PAD_CTL_22K_PU = 0x3 << 4,
PAD_CTL_ODE_CMOS = 0x0 << 3,
PAD_CTL_ODE_OpenDrain = 0x1 << 3,
PAD_CTL_DRV_NORMAL = 0x0 << 1,
PAD_CTL_DRV_HIGH = 0x1 << 1,
PAD_CTL_DRV_MAX = 0x2 << 1,
PAD_CTL_SRE_SLOW = 0x0 << 0,
PAD_CTL_SRE_FAST = 0x1 << 0
} iomux_pad_config_t;
/*!
* IOMUX general purpose functions
* IOMUXC_GPR1
*/
typedef enum iomux_gp_func {
MUX_SDCTL_CSD0_SEL = 0x1 << 0,
MUX_SDCTL_CSD1_SEL = 0x1 << 1,
} iomux_gp_func_t;
/*!
* IOMUX SELECT_INPUT register index
* Base register is IOMUXSW_INPUT_CTL in iomux.c
*/
typedef enum iomux_input_select {
MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0,
MUX_IN_AUDMUX_P4_INPUT_DB_AMX,
MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX,
MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX,
MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX,
MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX,
MUX_IN_AUDMUX_P7_INPUT_DA_AMX,
MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX,
MUX_IN_CAN1_IPP_IND_CANRX,
MUX_IN_CAN2_IPP_IND_CANRX,
MUX_IN_CSI_IPP_CSI_D_0,
MUX_IN_CSI_IPP_CSI_D_1,
MUX_IN_CSPI1_IPP_IND_SS3_B,
MUX_IN_CSPI2_IPP_CSPI_CLK_IN,
MUX_IN_CSPI2_IPP_IND_DATAREADY_B,
MUX_IN_CSPI2_IPP_IND_MISO,
MUX_IN_CSPI2_IPP_IND_MOSI,
MUX_IN_CSPI2_IPP_IND_SS0_B,
MUX_IN_CSPI2_IPP_IND_SS1_B,
MUX_IN_CSPI3_IPP_CSPI_CLK_IN,
MUX_IN_CSPI3_IPP_IND_DATAREADY_B,
MUX_IN_CSPI3_IPP_IND_MISO,
MUX_IN_CSPI3_IPP_IND_MOSI,
MUX_IN_CSPI3_IPP_IND_SS0_B,
MUX_IN_CSPI3_IPP_IND_SS1_B,
MUX_IN_CSPI3_IPP_IND_SS2_B,
MUX_IN_CSPI3_IPP_IND_SS3_B,
MUX_IN_ESDHC1_IPP_DAT4_IN,
MUX_IN_ESDHC1_IPP_DAT5_IN,
MUX_IN_ESDHC1_IPP_DAT6_IN,
MUX_IN_ESDHC1_IPP_DAT7_IN,
MUX_IN_ESDHC2_IPP_CARD_CLK_IN,
MUX_IN_ESDHC2_IPP_CMD_IN,
MUX_IN_ESDHC2_IPP_DAT0_IN,
MUX_IN_ESDHC2_IPP_DAT1_IN,
MUX_IN_ESDHC2_IPP_DAT2_IN,
MUX_IN_ESDHC2_IPP_DAT3_IN,
MUX_IN_ESDHC2_IPP_DAT4_IN,
MUX_IN_ESDHC2_IPP_DAT5_IN,
MUX_IN_ESDHC2_IPP_DAT6_IN,
MUX_IN_ESDHC2_IPP_DAT7_IN,
MUX_IN_FEC_FEC_COL,
MUX_IN_FEC_FEC_CRS,
MUX_IN_FEC_FEC_RDATA_2,
MUX_IN_FEC_FEC_RDATA_3,
MUX_IN_FEC_FEC_RX_CLK,
MUX_IN_FEC_FEC_RX_ER,
MUX_IN_I2C2_IPP_SCL_IN,
MUX_IN_I2C2_IPP_SDA_IN,
MUX_IN_I2C3_IPP_SCL_IN,
MUX_IN_I2C3_IPP_SDA_IN,
MUX_IN_KPP_IPP_IND_COL_4,
MUX_IN_KPP_IPP_IND_COL_5,
MUX_IN_KPP_IPP_IND_COL_6,
MUX_IN_KPP_IPP_IND_COL_7,
MUX_IN_KPP_IPP_IND_ROW_4,
MUX_IN_KPP_IPP_IND_ROW_5,
MUX_IN_KPP_IPP_IND_ROW_6,
MUX_IN_KPP_IPP_IND_ROW_7,
MUX_IN_SIM1_PIN_SIM_RCVD1_IN,
MUX_IN_SIM1_PIN_SIM_SIMPD1,
MUX_IN_SIM1_SIM_RCVD1_IO,
MUX_IN_SIM2_PIN_SIM_RCVD1_IN,
MUX_IN_SIM2_PIN_SIM_SIMPD1,
MUX_IN_SIM2_SIM_RCVD1_IO,
MUX_IN_UART3_IPP_UART_RTS_B,
MUX_IN_UART3_IPP_UART_RXD_MUX,
MUX_IN_UART4_IPP_UART_RTS_B,
MUX_IN_UART4_IPP_UART_RXD_MUX,
MUX_IN_UART5_IPP_UART_RTS_B,
MUX_IN_UART5_IPP_UART_RXD_MUX,
MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC,
MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC,
} iomux_input_select_t;
/*!
* IOMUX input functions
* SW_SELECT_INPUT bits 2-0
*/
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
INPUT_CTL_PATH1,
INPUT_CTL_PATH2,
INPUT_CTL_PATH3,
INPUT_CTL_PATH4,
INPUT_CTL_PATH5,
INPUT_CTL_PATH6,
INPUT_CTL_PATH7,
} iomux_input_cfg_t;
struct mxc_iomux_pin_cfg {
iomux_pin_name_t pin;
u8 mux_mode;
u16 pad_cfg;
u8 in_select;
u8 in_mode;
};
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b
* #iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
/*!
* This function configures input path.
*
* @param input index of input select register as defined in \b
* #iomux_input_select_t
* @param config the binary value of elements defined in \b
* #iomux_input_cfg_t
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
#endif

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arch/arm/mach-mx25/mm.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
/*!
* @file mach-mx25/mm.c
*
* @brief This file creates static mapping between physical to virtual memory.
*
* @ingroup Memory_MX25
*/
/*!
* This structure defines the MX25 memory map.
*/
static struct map_desc mx25_io_desc[] __initdata = {
{
.virtual = IRAM_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(IRAM_BASE_ADDR),
.length = IRAM_SIZE,
.type = MT_DEVICE},
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE,
.type = MT_DEVICE},
{
.virtual = NFC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(NFC_BASE_ADDR),
.length = NFC_SIZE,
.type = MT_DEVICE},
{
.virtual = ROMP_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(ROMP_BASE_ADDR),
.length = ROMP_SIZE,
.type = MT_DEVICE},
{
.virtual = ASIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(ASIC_BASE_ADDR),
.length = ASIC_SIZE,
.type = MT_DEVICE},
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE},
{
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE},
{
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE},
};
/*!
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory map for
* the IO modules.
*/
void __init mx25_map_io(void)
{
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
}

741
arch/arm/mach-mx25/mx25_3stack.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/input.h>
#include <linux/nodemask.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <asm/mach/flash.h>
#endif
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/keypad.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/memory.h>
#include <mach/gpio.h>
#include <mach/mmc.h>
#include "board-mx25_3stack.h"
#include "crm_regs.h"
#include "iomux.h"
/*!
* @file mach-mx25/mx25_3stack.c
*
* @brief This file contains the board specific initialization routines.
*
* @ingroup MSL_MX25
*/
unsigned int mx25_3stack_board_io;
/* working point(wp): 0 - 399MHz; 1 - 266MHz; 2 - 133MHz; */
/* 24MHz input clock table */
static struct cpu_wp cpu_wp_mx25[] = {
{
.pll_rate = 399000000,
.cpu_rate = 399000000,
.cpu_podf = 0x0,
.cpu_voltage = 1450000},
{
.pll_rate = 532000000,
.cpu_rate = 266000000,
.cpu_podf = 0x1,
.cpu_voltage = 1340000},
{
.pll_rate = 532000000,
.cpu_rate = 133000000,
.cpu_podf = 0x3,
.cpu_voltage = 1340000},
};
struct cpu_wp *get_cpu_wp(int *wp)
{
*wp = 3;
return cpu_wp_mx25;
}
static void mxc_nop_release(struct device *dev)
{
/* Nothing */
}
#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE)
static u16 keymapping[16] = {
KEY_UP, KEY_DOWN, KEY_VOLUMEDOWN, KEY_HOME,
KEY_RIGHT, KEY_LEFT, KEY_ENTER, KEY_VOLUMEUP,
KEY_F6, KEY_F8, KEY_F9, KEY_F10,
KEY_F1, KEY_F2, KEY_F3, KEY_POWER,
};
static struct resource mxc_kpp_resources[] = {
[0] = {
.start = MXC_INT_KPP,
.end = MXC_INT_KPP,
.flags = IORESOURCE_IRQ,
}
};
static struct keypad_data keypad_plat_data = {
.rowmax = 4,
.colmax = 4,
.irq = MXC_INT_KPP,
.learning = 0,
.delay = 2,
.matrix = keymapping,
};
/* mxc keypad driver */
static struct platform_device mxc_keypad_device = {
.name = "mxc_keypad",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_kpp_resources),
.resource = mxc_kpp_resources,
.dev = {
.release = mxc_nop_release,
.platform_data = &keypad_plat_data,
},
};
static void mxc_init_keypad(void)
{
(void)platform_device_register(&mxc_keypad_device);
}
#else
static inline void mxc_init_keypad(void)
{
}
#endif
/* MTD NAND flash */
#if defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE)
static struct mtd_partition mxc_nand_partitions[] = {
{
.name = "nand.bootloader",
.offset = 0,
.size = 1024 * 1024},
{
.name = "nand.kernel",
.offset = MTDPART_OFS_APPEND,
.size = 5 * 1024 * 1024},
{
.name = "nand.rootfs",
.offset = MTDPART_OFS_APPEND,
.size = 256 * 1024 * 1024},
{
.name = "nand.configure",
.offset = MTDPART_OFS_APPEND,
.size = 8 * 1024 * 1024},
{
.name = "nand.userfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL},
};
static struct flash_platform_data mxc_nand_data = {
.parts = mxc_nand_partitions,
.nr_parts = ARRAY_SIZE(mxc_nand_partitions),
.width = 1,
};
static struct platform_device mxc_nand_mtd_device = {
.name = "mxc_nandv2_flash",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxc_nand_data,
},
};
static void mxc_init_nand_mtd(void)
{
if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B)
mxc_nand_data.width = 2;
platform_device_register(&mxc_nand_mtd_device);
}
#else
static inline void mxc_init_nand_mtd(void)
{
}
#endif
#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
static const char fb_default_mode[] = "CPT-VGA";
/* mxc lcd driver */
static struct platform_device mxc_fb_device = {
.name = "mxc_sdc_fb",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &fb_default_mode,
.coherent_dma_mask = 0xFFFFFFFF,
},
};
/*
* Power on/off CPT VGA panel.
*/
void board_power_lcd(int on)
{
if (on)
mx2fb_set_brightness(MXC_DEFAULT_INTENSITY);
else
mx2fb_set_brightness(MXC_INTENSITY_OFF);
}
EXPORT_SYMBOL_GPL(board_power_lcd);
static void mxc_init_fb(void)
{
(void)platform_device_register(&mxc_fb_device);
}
#else
static inline void mxc_init_fb(void)
{
}
#endif
#if defined(CONFIG_BACKLIGHT_MXC)
static struct platform_device mxcbl_devices[] = {
#if defined(CONFIG_BACKLIGHT_MXC_LCDC) || \
defined(CONFIG_BACKLIGHT_MXC_LCDC_MODULE)
{
.name = "mxc_lcdc_bl",
.id = 0,
},
#endif
};
static inline void mxc_init_bl(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++)
platform_device_register(&mxcbl_devices[i]);
}
#else
static inline void mxc_init_bl(void)
{
}
#endif
/*!
* Power Key interrupt handler.
*/
static irqreturn_t power_key_int(int irq, void *dev_id)
{
pr_info("on-off key pressed\n");
return 0;
}
/*!
* Power Key initialization.
*/
static int __init mxc_init_power_key(void)
{
/*Set power key as wakeup resource */
int irq, ret;
mxc_request_iomux(MX25_PIN_A25, MUX_CONFIG_ALT5);
mxc_iomux_set_pad(MX25_PIN_A25, PAD_CTL_DRV_NORMAL);
gpio_request(IOMUX_TO_GPIO(MX25_PIN_A25), NULL);
gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A25));
irq = IOMUX_TO_IRQ(MX25_PIN_A25);
set_irq_type(irq, IRQF_TRIGGER_RISING);
ret = request_irq(irq, power_key_int, 0, "power_key", 0);
if (ret)
pr_info("register on-off key interrupt failed\n");
else
enable_irq_wake(irq);
return ret;
}
late_initcall(mxc_init_power_key);
static struct spi_board_info mxc_spi_board_info[] __initdata = {
{
.modalias = "cpld_spi",
.max_speed_hz = 18000000,
.bus_num = 1,
.chip_select = 0,
.mode = SPI_MODE_2,
},
{
.modalias = "wm8580_spi",
.max_speed_hz = 8000000, /* max spi SCK clock speed in HZ */
.bus_num = 1,
.chip_select = 1,
},
};
static struct mxc_camera_platform_data camera_data = {
.core_regulator = NULL,
.io_regulator = NULL,
.analog_regulator = NULL,
.gpo_regulator = NULL,
.mclk = 24000000,
};
static struct i2c_board_info mxc_i2c_board_info[] __initdata = {
{
.type = "sgtl5000-i2c",
.addr = 0x0a,
},
{
.type = "ak5702-i2c",
.addr = 0x13,
},
{
.type = "ov2640",
.addr = 0x30,
.platform_data = (void *)&camera_data,
},
};
#if defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) \
|| defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000_MODULE)
static struct mxc_audio_platform_data sgtl5000_data = {
.ssi_num = 2,
.src_port = 1,
.ext_port = 4,
.hp_irq = IOMUX_TO_IRQ(MX25_PIN_A10),
.hp_status = headphone_det_status,
.vddio = 1800000,
.vdda = 3300000,
.vddd = 0,
.sysclk = 8300000,
};
static struct platform_device mxc_sgtl5000_device = {
.name = "imx-3stack-sgtl5000",
.dev = {
.release = mxc_nop_release,
.platform_data = &sgtl5000_data,
},
};
static void mxc_init_sgtl5000(void)
{
struct clk *cko1, *parent;
unsigned long rate;
/* cko1 clock */
mxc_request_iomux(MX25_PIN_CLKO, MUX_CONFIG_FUNC);
cko1 = clk_get(NULL, "clko_clk");
if (IS_ERR(cko1))
return;
parent = clk_get(NULL, "ipg_clk");
if (IS_ERR(parent))
return;
clk_set_parent(cko1, parent);
rate = clk_round_rate(cko1, 13000000);
if (rate < 8000000 || rate > 27000000) {
pr_err("Error: SGTL5000 mclk freq %ld out of range!\n", rate);
clk_put(parent);
clk_put(cko1);
return;
}
clk_set_rate(cko1, rate);
clk_enable(cko1);
sgtl5000_data.sysclk = rate;
sgtl5000_enable_amp();
platform_device_register(&mxc_sgtl5000_device);
}
#else
static inline void mxc_init_sgtl5000(void)
{
}
#endif
#if defined(CONFIG_SND_SOC_IMX_3STACK_AK5702) \
|| defined(CONFIG_SND_SOC_IMX_3STACK_AK5702_MODULE)
static struct platform_device mxc_ak5702_device = {
.name = "imx-3stack-ak5702",
.dev = {
.release = mxc_nop_release,
},
};
static void mxc_init_ak5702(void)
{
platform_device_register(&mxc_ak5702_device);
}
#else
static inline void mxc_init_ak5702(void)
{
}
#endif
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
static struct resource smsc911x_resources[] = {
{
.start = LAN9217_BASE_ADDR,
.end = LAN9217_BASE_ADDR + 255,
.flags = IORESOURCE_MEM,
},
{
.start = MXC_BOARD_IRQ_START,
.flags = IORESOURCE_IRQ,
}
};
struct smsc911x_platform_config smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.flags = 0x8000 | SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
};
static struct platform_device smsc_lan9217_device = {
.name = "smsc911x",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &smsc911x_config,
},
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
};
static int __init mxc_init_enet(void)
{
(void)platform_device_register(&smsc_lan9217_device);
return 0;
}
#else
static int __init mxc_init_enet(void)
{
return 0;
}
#endif
late_initcall(mxc_init_enet);
#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
static struct resource mxc_fec_resources[] = {
{
.start = FEC_BASE_ADDR,
.end = FEC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MXC_INT_FEC,
.end = MXC_INT_FEC,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mxc_fec_device = {
.name = "fec",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fec_resources),
.resource = mxc_fec_resources,
};
static __init int mxc_init_fec(void)
{
return platform_device_register(&mxc_fec_device);
}
#else
static inline int mxc_init_fec(void)
{
return 0;
}
#endif
#if defined(CONFIG_IMX_SIM) || defined(CONFIG_IMX_SIM_MODULE)
/* Used to configure the SIM bus */
static struct mxc_sim_platform_data sim1_data = {
.clk_rate = 5000000,
.clock_sim = "sim1_clk",
.power_sim = NULL,
.init = NULL,
.exit = NULL,
.detect = 1,
};
/*!
* Resource definition for the SIM
*/
static struct resource mxc_sim1_resources[] = {
[0] = {
.start = SIM1_BASE_ADDR,
.end = SIM1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_SIM1,
.end = MXC_INT_SIM1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
/*! Device Definition for IMX SIM */
static struct platform_device mxc_sim1_device = {
.name = "mxc_sim",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &sim1_data,
},
.num_resources = ARRAY_SIZE(mxc_sim1_resources),
.resource = mxc_sim1_resources,
};
static inline void mxc_init_sim(void)
{
(void)platform_device_register(&mxc_sim1_device);
}
#else
static inline void mxc_init_sim(void)
{
}
#endif
#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
static struct mxc_mmc_platform_data mmc1_data = {
.ocr_mask = MMC_VDD_29_30 | MMC_VDD_32_33,
.caps = MMC_CAP_4_BIT_DATA,
.min_clk = 400000,
.max_clk = 52000000,
.card_inserted_state = 1,
.status = sdhc_get_card_det_status,
.wp_status = sdhc_write_protect,
.clock_mmc = "esdhc_clk",
};
/*!
* Resource definition for the SDHC1
*/
static struct resource mxcsdhc1_resources[] = {
[0] = {
.start = MMC_SDHC1_BASE_ADDR,
.end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_SDHC1,
.end = MXC_INT_SDHC1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IOMUX_TO_IRQ(MX25_PIN_A15),
.end = IOMUX_TO_IRQ(MX25_PIN_A15),
.flags = IORESOURCE_IRQ,
},
};
/*! Device Definition for MXC SDHC1 */
static struct platform_device mxcsdhc1_device = {
.name = "mxsdhci",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mmc1_data,
},
.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
.resource = mxcsdhc1_resources,
};
#ifdef CONFIG_MMC_IMX_ESDHCI_SELECT2
static struct mxc_mmc_platform_data mmc2_data = {
.ocr_mask = MMC_VDD_29_30 | MMC_VDD_32_33,
.caps = MMC_CAP_4_BIT_DATA,
.min_clk = 400000,
.max_clk = 52000000,
.card_fixed = 1,
.card_inserted_state = 1,
.status = sdhc_get_card_det_status,
.clock_mmc = "esdhc2_clk",
};
/*!
* Resource definition for the SDHC2
*/
static struct resource mxcsdhc2_resources[] = {
[0] = {
.start = MMC_SDHC2_BASE_ADDR,
.end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_SDHC2,
.end = MXC_INT_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
/*! Device Definition for MXC SDHC2 */
static struct platform_device mxcsdhc2_device = {
.name = "mxsdhci",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mmc2_data,
},
.num_resources = ARRAY_SIZE(mxcsdhc2_resources),
.resource = mxcsdhc2_resources,
};
#endif
static inline void mxc_init_mmc(void)
{
(void)platform_device_register(&mxcsdhc1_device);
#ifdef CONFIG_MMC_IMX_ESDHCI_SELECT2
(void)platform_device_register(&mxcsdhc2_device);
#endif
}
#else
static inline void mxc_init_mmc(void)
{
}
#endif
static void __init mx25_3stack_timer_init(void)
{
mx25_clocks_init(24000000);
}
static struct sys_timer mxc_timer = {
.init = mx25_3stack_timer_init,
};
#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
static void flexcan_xcvr_enable(int id, int en)
{
static int pwdn;
if (id != 1) /* MX25 3-stack uses only CAN2 */
return;
if (en) {
if (!pwdn++)
gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 0);
} else {
if (!--pwdn)
gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 1);
}
}
struct flexcan_platform_data flexcan_data[] = {
{
.core_reg = NULL,
.io_reg = NULL,
.xcvr_enable = flexcan_xcvr_enable,
.active = gpio_can_active,
.inactive = gpio_can_inactive,},
{
.core_reg = NULL,
.io_reg = NULL,
.xcvr_enable = flexcan_xcvr_enable,
.active = gpio_can_active,
.inactive = gpio_can_inactive,},
};
#endif
/*!
* Board specific fixup function. It is called by \b setup_arch() in
* setup.c file very early on during kernel starts. It allows the user to
* statically fill in the proper values for the passed-in parameters. None of
* the parameters is used currently.
*
* @param desc pointer to \b struct \b machine_desc
* @param tags pointer to \b struct \b tag
* @param cmdline pointer to the command line
* @param mi pointer to \b struct \b meminfo
*/
static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
mxc_cpu_init();
#ifdef CONFIG_DISCONTIGMEM
do {
int nid;
mi->nr_banks = MXC_NUMNODES;
for (nid = 0; nid < mi->nr_banks; nid++)
SET_NODE(mi, nid);
} while (0);
#endif
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
pr_info("AIPS1 VA base: 0x%p\n", IO_ADDRESS(AIPS1_BASE_ADDR));
mxc_cpu_common_init();
mxc_register_gpios();
mx25_3stack_gpio_init();
early_console_setup(saved_command_line);
mxc_init_keypad();
#ifdef CONFIG_I2C
i2c_register_board_info(0, mxc_i2c_board_info,
ARRAY_SIZE(mxc_i2c_board_info));
#endif
spi_register_board_info(mxc_spi_board_info,
ARRAY_SIZE(mxc_spi_board_info));
mx25_3stack_init_mc34704();
mxc_init_fb();
mxc_init_bl();
mxc_init_nand_mtd();
mxc_init_sgtl5000();
mxc_init_ak5702();
mxc_init_mmc();
mxc_init_sim();
mxc_init_fec();
}
/*
* The following uses standard kernel macros define in arch.h in order to
* initialize __mach_desc_MX25_3DS data structure.
*/
/* *INDENT-OFF* */
MACHINE_START(MX25_3DS, "Freescale MX25 3-Stack Board")
/* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.fixup = fixup_mxc_board,
.map_io = mx25_map_io,
.init_irq = mxc_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <mach/hardware.h>
#include <asm/mach/irq.h>
#include <mach/gpio.h>
#include "board-mx25_3stack.h"
#include "iomux.h"
/*!
* @file mach-mx25/mx25_3stack_cpld.c
*
* @brief This file contains the board specific initialization routines.
*
* @ingroup MSL_MX25
*/
extern int mxc_spi_poll_transfer(struct spi_device *spi,
struct spi_transfer *t);
static int __init mxc_expio_init(void);
struct spi_device *cpld_spi;
/*!
* This function is used to tranfer data to CPLD regs over CSPI
*/
static inline int mx25_3ds_cpld_rw(u8 *buf, size_t len)
{
struct spi_transfer t = {
.tx_buf = (const void *)buf,
.rx_buf = buf,
.len = len,
.cs_change = 0,
.delay_usecs = 0,
};
if (!cpld_spi)
return -1;
mxc_spi_poll_transfer(cpld_spi, &t);
return 0;
}
/*!
* This function is called to read a CPLD register over CSPI.
*
* @param offset number of the cpld register to be read
*
* @return Returns 0 on success -1 on failure.
*/
unsigned int spi_cpld_read(unsigned int offset)
{
unsigned int frame[2];
unsigned int reg_num = offset >> 1;
unsigned int data = 0;
frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000;
frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f);
mx25_3ds_cpld_rw((u8 *) frame, 2);
data = (frame[1] >> 6) & 0xFFFF;
reg_num = (offset + 2) >> 1;
frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000;
frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f);
mx25_3ds_cpld_rw((u8 *) frame, 2);
data |= (((frame[1] >> 6) & 0xFFFF) << 16);
return data;
}
EXPORT_SYMBOL(spi_cpld_read);
/*!
* This function is called to write to a CPLD register over CSPI.
*
* @param offset number of the cpld register to be written
* @param reg_val value to be written
*
* @return Returns 0 on success -1 on failure.
*/
unsigned int spi_cpld_write(unsigned int offset, unsigned int reg_val)
{
unsigned int frame[2] = { 0, 0 };
unsigned int reg_num = offset >> 1;
unsigned int data = reg_val;
frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000;
frame[1] = (((reg_num & 0x0000001F) << 27) |
((data & 0x0000FFFF) << 6) | 0x03C00027);
mx25_3ds_cpld_rw((u8 *) frame, 2);
reg_num = (offset + 2) >> 1;
data = reg_val >> 16;
frame[0] = 0;
frame[1] = 0;
frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000;
frame[1] = (((reg_num & 0x0000001F) << 27) |
((data & 0x0000FFFF) << 6) | 0x03C00027);
mx25_3ds_cpld_rw((u8 *) frame, 2);
return 0;
}
EXPORT_SYMBOL(spi_cpld_write);
static int __init mx25_3ds_cpld_probe(struct spi_device *spi)
{
unsigned int i = 0;
spi->bits_per_word = 46;
cpld_spi = spi;
spi_setup(spi);
i = spi_cpld_read(CPLD_CODE_VER_REG);
pr_info("3-Stack Debug board detected, rev = 0x%04X\n", i);
spi_cpld_write(LED_SWITCH_REG, 0xFF);
/* disable the interrupt and clear the status */
spi_cpld_write(INTR_MASK_REG, 0);
spi_cpld_write(INTR_RESET_REG, 0xFFFF);
spi_cpld_write(INTR_RESET_REG, 0);
spi_cpld_write(INTR_MASK_REG, 0x1E);
mxc_expio_init();
return 0;
}
/*!
* This structure contains pointers to the CPLD callback functions.
*/
static struct spi_driver mx25_3ds_cpld_driver = {
.driver = {
.name = "cpld_spi",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = mx25_3ds_cpld_probe,
};
static int __init mx25_3ds_cpld_init(void)
{
pr_info("Registering the CPLD Driver\n");
return spi_register_driver(&mx25_3ds_cpld_driver);
}
device_initcall(mx25_3ds_cpld_init);
static int __initdata is_dbg_removed = { 0 };
static int __init remove_dbg_setup(char *__unused)
{
is_dbg_removed = 1;
return 0;
}
__setup("remove_dbg", remove_dbg_setup);
static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 expio_irq;
struct irq_desc *d;
desc->chip->mask(irq); /* irq = gpio irq number */
expio_irq = MXC_BOARD_IRQ_START;
d = irq_desc + expio_irq;
if (unlikely(!(d->handle_irq))) {
printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", expio_irq);
BUG(); /* oops */
}
d->handle_irq(expio_irq, d);
desc->chip->ack(irq);
desc->chip->unmask(irq);
}
/*
* Disable an expio pin's interrupt by setting the bit in the imr.
* @param irq an expio virtual irq number
*/
static void expio_mask_irq(u32 irq)
{
}
/*
* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
* @param irq an expanded io virtual irq number
*/
static void expio_ack_irq(u32 irq)
{
/* clear the interrupt status */
spi_cpld_write(INTR_RESET_REG, 1);
spi_cpld_write(INTR_RESET_REG, 0);
}
/*
* Enable a expio pin's interrupt by clearing the bit in the imr.
* @param irq a expio virtual irq number
*/
static void expio_unmask_irq(u32 irq)
{
}
static struct irq_chip expio_irq_chip = {
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
};
static int __init mxc_expio_init(void)
{
int i;
if (is_dbg_removed)
return 0;
/*
* Configure INT line as GPIO input
*/
mxc_request_iomux(MX25_PIN_PWM, MUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PUE_PUD);
gpio_request(IOMUX_TO_GPIO(MX25_PIN_PWM), NULL);
gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_PWM));
for (i = MXC_BOARD_IRQ_START; i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS);
i++) {
set_irq_chip(i, &expio_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
set_irq_type(IOMUX_TO_IRQ(MX25_PIN_PWM), IRQF_TRIGGER_LOW);
set_irq_chained_handler(IOMUX_TO_IRQ(MX25_PIN_PWM),
mxc_expio_irq_handler);
return 0;
}

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arch/arm/mach-mx25/mx25_3stack_gpio.c Normal file
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arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c Normal file
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/*
* mx25-3stack-pmic-mc34704.c -- i.MX25 3STACK Driver for MC34704 PMIC
*/
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/pmic_external.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc34704/core.h>
#include "iomux.h"
/*
* Convenience conversion.
* Here atm, maybe there is somewhere better for this.
*/
#define mV_to_uV(mV) (mV * 1000)
#define uV_to_mV(uV) (uV / 1000)
#define V_to_uV(V) (mV_to_uV(V * 1000))
#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
struct mc34704;
static struct regulator_init_data rbklt_init = {
.constraints = {
.name = "REG1_BKLT",
.min_uV =
mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MIN_PCT * 10) /
1000),
.max_uV =
mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MAX_PCT * 10) /
1000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data rcpu_init = {
.constraints = {
.name = "REG2_CPU",
.min_uV =
mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MIN_PCT * 10) /
1000),
.max_uV =
mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MAX_PCT * 10) /
1000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data rcore_init = {
.constraints = {
.name = "REG3_CORE",
.min_uV =
mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MIN_PCT * 10) /
1000),
.max_uV =
mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MAX_PCT * 10) /
1000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data rddr_init = {
.constraints = {
.name = "REG4_DDR",
.min_uV =
mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MIN_PCT * 10) /
1000),
.max_uV =
mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MAX_PCT * 10) /
1000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data rpers_init = {
.constraints = {
.name = "REG5_PERS",
.min_uV =
mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MIN_PCT * 10) /
1000),
.max_uV =
mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MAX_PCT * 10) /
1000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static int mc34704_regulator_init(struct mc34704 *mc34704)
{
mc34704_register_regulator(mc34704, MC34704_BKLT, &rbklt_init);
mc34704_register_regulator(mc34704, MC34704_CPU, &rcpu_init);
mc34704_register_regulator(mc34704, MC34704_CORE, &rcore_init);
mc34704_register_regulator(mc34704, MC34704_DDR, &rddr_init);
mc34704_register_regulator(mc34704, MC34704_PERS, &rpers_init);
return 0;
}
static struct mc34704_platform_data mc34704_plat = {
.init = mc34704_regulator_init,
};
static struct i2c_board_info __initdata mc34704_i2c_device = {
.type = "mc34704",
.addr = 0x54,
.platform_data = &mc34704_plat,
};
int __init mx25_3stack_init_mc34704(void)
{
return i2c_register_board_info(0, &mc34704_i2c_device, 1);
}

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arch/arm/mach-mx25/mx25_pins.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_MX25_PINS_H__
#define __ASM_ARCH_MXC_MX25_PINS_H__
/*!
* @file arch-mxc/mx25_pins.h
*
* @brief MX25 I/O Pin List
*
* @ingroup GPIO_MX25
*/
#ifndef __ASSEMBLY__
/*!
* @name IOMUX/PAD Bit field definitions
*/
/*! @{ */
/*!
* In order to identify pins more effectively, each mux-controlled pin's
* enumerated value is constructed in the following way:
*
* -------------------------------------------------------------------
* 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
* -------------------------------------------------------------------
* IO_P | IO_I | RSVD | PAD_I | MUX_I
* -------------------------------------------------------------------
*
* Bit 0 to 7 contains MUX_I used to identify the register
* offset (base is IOMUX_module_base ) defined in the Section
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Similar field
* definitions are used for the pad control register. For example,
* MX25_PIN_A14 is defined in the enumeration:
* ( 0x10 << MUX_I) | ( 0x230 << PAD_I)
* So the absolute address is: IOMUX_module_base + 0x10.
* The pad control register offset is: 0x230.
*/
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* MUX control register offset
*/
#define MUX_I 0
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* PAD control register offset
*/
#define PAD_I 10
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* reserved filed
*/
#define RSVD_I 21
#define NON_GPIO_I 0x7
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
#define NON_MUX_I PIN_TO_MUX_MASK
#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
((mi) << MUX_I) | ((pi) << PAD_I))
#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
_MXC_BUILD_PIN(gp, gi, mi, pi)
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
/*! @} End IOMUX/PAD Bit field definitions */
enum iomux_pins {
MX25_PIN_A10 = _MXC_BUILD_GPIO_PIN(3, 0, 0x8, 0x0),
MX25_PIN_A13 = _MXC_BUILD_GPIO_PIN(3, 1, 0x0c, 0x22C),
MX25_PIN_A14 = _MXC_BUILD_GPIO_PIN(1, 0, 0x10, 0x230),
MX25_PIN_A15 = _MXC_BUILD_GPIO_PIN(1, 1, 0x14, 0x234),
MX25_PIN_A16 = _MXC_BUILD_GPIO_PIN(1, 2, 0x18, 0x0),
MX25_PIN_A17 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1c, 0x238),
MX25_PIN_A18 = _MXC_BUILD_GPIO_PIN(1, 4, 0x20, 0x23c),
MX25_PIN_A19 = _MXC_BUILD_GPIO_PIN(1, 5, 0x24, 0x240),
MX25_PIN_A20 = _MXC_BUILD_GPIO_PIN(1, 6, 0x28, 0x244),
MX25_PIN_A21 = _MXC_BUILD_GPIO_PIN(1, 7, 0x2c, 0x248),
MX25_PIN_A22 = _MXC_BUILD_GPIO_PIN(1, 8, 0x30, 0x0),
MX25_PIN_A23 = _MXC_BUILD_GPIO_PIN(1, 9, 0x34, 0x24c),
MX25_PIN_A24 = _MXC_BUILD_GPIO_PIN(1, 10, 0x38, 0x250),
MX25_PIN_A25 = _MXC_BUILD_GPIO_PIN(1, 11, 0x3c, 0x254),
MX25_PIN_EB0 = _MXC_BUILD_GPIO_PIN(1, 12, 0x40, 0x258),
MX25_PIN_EB1 = _MXC_BUILD_GPIO_PIN(1, 13, 0x44, 0x25c),
MX25_PIN_OE = _MXC_BUILD_GPIO_PIN(1, 14, 0x48, 0x260),
MX25_PIN_CS0 = _MXC_BUILD_GPIO_PIN(3, 2, 0x4c, 0x0),
MX25_PIN_CS1 = _MXC_BUILD_GPIO_PIN(3, 3, 0x50, 0x0),
MX25_PIN_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 0x54, 0x264),
MX25_PIN_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 0x58, 0x268),
MX25_PIN_NF_CE0 = _MXC_BUILD_GPIO_PIN(2, 22, 0x5c, 0x26c),
MX25_PIN_ECB = _MXC_BUILD_GPIO_PIN(2, 23, 0x60, 0x270),
MX25_PIN_LBA = _MXC_BUILD_GPIO_PIN(2, 24, 0x64, 0x274),
MX25_PIN_BCLK = _MXC_BUILD_GPIO_PIN(3, 4, 0x68, 0x0),
MX25_PIN_RW = _MXC_BUILD_GPIO_PIN(2, 25, 0x6c, 0x278),
MX25_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(2, 26, 0x70, 0x0),
MX25_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(2, 27, 0x74, 0x0),
MX25_PIN_NFALE = _MXC_BUILD_GPIO_PIN(2, 28, 0x78, 0x0),
MX25_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(2, 29, 0x7c, 0x0),
MX25_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(2, 30, 0x80, 0x0),
MX25_PIN_NFRB = _MXC_BUILD_GPIO_PIN(2, 31, 0x84, 0x27c),
MX25_PIN_D15 = _MXC_BUILD_GPIO_PIN(3, 5, 0x88, 0x280),
MX25_PIN_D14 = _MXC_BUILD_GPIO_PIN(3, 6, 0x8c, 0x284),
MX25_PIN_D13 = _MXC_BUILD_GPIO_PIN(3, 7, 0x90, 0x288),
MX25_PIN_D12 = _MXC_BUILD_GPIO_PIN(3, 8, 0x94, 0x28c),
MX25_PIN_D11 = _MXC_BUILD_GPIO_PIN(3, 9, 0x98, 0x290),
MX25_PIN_D10 = _MXC_BUILD_GPIO_PIN(3, 10, 0x9c, 0x294),
MX25_PIN_D9 = _MXC_BUILD_GPIO_PIN(3, 11, 0xa0, 0x298),
MX25_PIN_D8 = _MXC_BUILD_GPIO_PIN(3, 12, 0xa4, 0x29c),
MX25_PIN_D7 = _MXC_BUILD_GPIO_PIN(3, 13, 0xa8, 0x2a0),
MX25_PIN_D6 = _MXC_BUILD_GPIO_PIN(3, 14, 0xac, 0x2a4),
MX25_PIN_D5 = _MXC_BUILD_GPIO_PIN(3, 15, 0xb0, 0x2a8),
MX25_PIN_D4 = _MXC_BUILD_GPIO_PIN(3, 16, 0xb4, 0x2ac),
MX25_PIN_D3 = _MXC_BUILD_GPIO_PIN(3, 17, 0xb8, 0x2b0),
MX25_PIN_D2 = _MXC_BUILD_GPIO_PIN(3, 18, 0xbc, 0x2b4),
MX25_PIN_D1 = _MXC_BUILD_GPIO_PIN(3, 19, 0xc0, 0x2b8),
MX25_PIN_D0 = _MXC_BUILD_GPIO_PIN(3, 20, 0xc4, 0x2bc),
MX25_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 15, 0xc8, 0x2c0),
MX25_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 16, 0xcc, 0x2c4),
MX25_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 17, 0xd0, 0x2c8),
MX25_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 18, 0xd4, 0x2cc),
MX25_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 19, 0xd8, 0x2d0),
MX25_PIN_LD5 = _MXC_BUILD_GPIO_PIN(0, 19, 0xdc, 0x2d4),
MX25_PIN_LD6 = _MXC_BUILD_GPIO_PIN(0, 20, 0xe0, 0x2d8),
MX25_PIN_LD7 = _MXC_BUILD_GPIO_PIN(0, 21, 0xe4, 0x2dc),
MX25_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(0xe8, 0x2e0),
MX25_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(0xec, 0x2e4),
MX25_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(0xf0, 0x2e8),
MX25_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(0xf4, 0x2ec),
MX25_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(0xf8, 0x2f0),
MX25_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(0xfc, 0x2f4),
MX25_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(0x100, 0x2f8),
MX25_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x2fc),
MX25_PIN_HSYNC = _MXC_BUILD_GPIO_PIN(0, 22, 0x108, 0x300),
MX25_PIN_VSYNC = _MXC_BUILD_GPIO_PIN(0, 23, 0x10c, 0x304),
MX25_PIN_LSCLK = _MXC_BUILD_GPIO_PIN(0, 24, 0x110, 0x308),
MX25_PIN_OE_ACD = _MXC_BUILD_GPIO_PIN(0, 25, 0x114, 0x30c),
MX25_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(0x118, 0x310),
MX25_PIN_PWM = _MXC_BUILD_GPIO_PIN(0, 26, 0x11c, 0x314),
MX25_PIN_CSI_D2 = _MXC_BUILD_GPIO_PIN(0, 27, 0x120, 0x318),
MX25_PIN_CSI_D3 = _MXC_BUILD_GPIO_PIN(0, 28, 0x124, 0x31c),
MX25_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(0, 29, 0x128, 0x320),
MX25_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(0, 30, 0x12c, 0x324),
MX25_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(0, 31, 0x130, 0x328),
MX25_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(0, 6, 0x134, 0x32c),
MX25_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 7, 0x138, 0x330),
MX25_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(3, 21, 0x13c, 0x334),
MX25_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 8, 0x140, 0x338),
MX25_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 9, 0x144, 0x33c),
MX25_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 10, 0x148, 0x340),
MX25_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 11, 0x14c, 0x344),
MX25_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(0, 12, 0x150, 0x348),
MX25_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(0, 13, 0x154, 0x34c),
MX25_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 14, 0x158, 0x350),
MX25_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 15, 0x15c, 0x354),
MX25_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 16, 0x160, 0x358),
MX25_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 17, 0x164, 0x35c),
MX25_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(0, 18, 0x168, 0x360),
MX25_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(1, 22, 0x16c, 0x364),
MX25_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 22, 0x170, 0x368),
MX25_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 23, 0x174, 0x36c),
MX25_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 24, 0x178, 0x370),
MX25_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 25, 0x17c, 0x374),
MX25_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(3, 26, 0x180, 0x378),
MX25_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(3, 27, 0x184, 0x37c),
MX25_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(3, 28, 0x188, 0x380),
MX25_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(3, 29, 0x18c, 0x384),
MX25_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 23, 0x190, 0x388),
MX25_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x194, 0x38c),
MX25_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 25, 0x198, 0x390),
MX25_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 26, 0x19c, 0x394),
MX25_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 27, 0x1a0, 0x398),
MX25_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 28, 0x1a4, 0x39c),
MX25_PIN_KPP_ROW0 = _MXC_BUILD_GPIO_PIN(1, 29, 0x1a8, 0x3a0),
MX25_PIN_KPP_ROW1 = _MXC_BUILD_GPIO_PIN(1, 30, 0x1ac, 0x3a4),
MX25_PIN_KPP_ROW2 = _MXC_BUILD_GPIO_PIN(1, 31, 0x1b0, 0x3a8),
MX25_PIN_KPP_ROW3 = _MXC_BUILD_GPIO_PIN(2, 0, 0x1b4, 0x3ac),
MX25_PIN_KPP_COL0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1b8, 0x3b0),
MX25_PIN_KPP_COL1 = _MXC_BUILD_GPIO_PIN(2, 2, 0x1bc, 0x3b4),
MX25_PIN_KPP_COL2 = _MXC_BUILD_GPIO_PIN(2, 3, 0x1c0, 0x3b8),
MX25_PIN_KPP_COL3 = _MXC_BUILD_GPIO_PIN(2, 4, 0x1c4, 0x3bc),
MX25_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 5, 0x1c8, 0x3c0),
MX25_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 6, 0x1cc, 0x3c4),
MX25_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 7, 0x1d0, 0x3c8),
MX25_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x1d4, 0x3cc),
MX25_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 9, 0x1d8, 0x3d0),
MX25_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x1dc, 0x3d4),
MX25_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 11, 0x1e0, 0x3d8),
MX25_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 12, 0x1e4, 0x3dc),
MX25_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 13, 0x1e8, 0x3e0),
MX25_PIN_RTCK = _MXC_BUILD_GPIO_PIN(2, 14, 0x1ec, 0x3e4),
MX25_PIN_DE_B = _MXC_BUILD_GPIO_PIN(1, 20, 0x1f0, 0x3ec),
MX25_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3e8),
MX25_PIN_GPIO_A = _MXC_BUILD_GPIO_PIN(0, 0, 0x1f4, 0x3f0),
MX25_PIN_GPIO_B = _MXC_BUILD_GPIO_PIN(0, 1, 0x1f8, 0x3f4),
MX25_PIN_GPIO_C = _MXC_BUILD_GPIO_PIN(0, 2, 0x1fc, 0x3f8),
MX25_PIN_GPIO_D = _MXC_BUILD_GPIO_PIN(0, 3, 0x200, 0x3fc),
MX25_PIN_GPIO_E = _MXC_BUILD_GPIO_PIN(0, 4, 0x204, 0x400),
MX25_PIN_GPIO_F = _MXC_BUILD_GPIO_PIN(0, 5, 0x208, 0x404),
MX25_PIN_EXT_ARMCLK = _MXC_BUILD_GPIO_PIN(2, 15, 0x20c, 0x0),
MX25_PIN_UPLL_BYPCLK = _MXC_BUILD_GPIO_PIN(2, 16, 0x210, 0x0),
MX25_PIN_VSTBY_REQ = _MXC_BUILD_GPIO_PIN(2, 17, 0x214, 0x408),
MX25_PIN_VSTBY_ACK = _MXC_BUILD_GPIO_PIN(2, 18, 0x218, 0x40c),
MX25_PIN_POWER_FAIL = _MXC_BUILD_GPIO_PIN(2, 19, 0x21c, 0x410),
MX25_PIN_CLKO = _MXC_BUILD_GPIO_PIN(1, 21, 0x220, 0x414),
MX25_PIN_BOOT_MODE0 = _MXC_BUILD_GPIO_PIN(3, 30, 0x224, 0x0),
MX25_PIN_BOOT_MODE1 = _MXC_BUILD_GPIO_PIN(3, 31, 0x228, 0x0),
MX25_PIN_CTL_GRP_DVS_MISC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x418),
MX25_PIN_CTL_GRP_DSE_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x41c),
MX25_PIN_CTL_GRP_DVS_JTAG = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x420),
MX25_PIN_CTL_GRP_DSE_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x424),
MX25_PIN_CTL_GRP_DSE_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x428),
MX25_PIN_CTL_GRP_DSE_WEIM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x42c),
MX25_PIN_CTL_GRP_DSE_DDR = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x430),
MX25_PIN_CTL_GRP_DVS_CRM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x434),
MX25_PIN_CTL_GRP_DSE_KPP = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x438),
MX25_PIN_CTL_GRP_DSE_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43c),
MX25_PIN_CTL_GRP_DSE_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
MX25_PIN_CTL_GRP_DSE_UART = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
MX25_PIN_CTL_GRP_DVS_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
MX25_PIN_CTL_GRP_DVS_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44c),
MX25_PIN_CTL_GRP_DSE_CSPI1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
MX25_PIN_CTL_GRP_DDRTYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
MX25_PIN_CTL_GRP_DVS_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x458),
MX25_PIN_CTL_GRP_DVS_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x45c)
};
#endif
#endif

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/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "crm_regs.h"
/*!
* @defgroup MSL_MX25 i.MX25 Machine Specific Layer (MSL)
*/
/*!
* @file mach-mx25/pm.c
* @brief This file contains suspend operations
*
* @ingroup MSL_MX25
*/
static unsigned int cgcr0, cgcr1, cgcr2;
static int mx25_suspend_enter(suspend_state_t state)
{
unsigned int reg;
switch (state) {
case PM_SUSPEND_MEM:
mxc_cpu_lp_set(STOP_POWER_OFF);
break;
case PM_SUSPEND_STANDBY:
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
break;
default:
return -EINVAL;
}
/* Executing CP15 (Wait-for-Interrupt) Instruction */
cpu_do_idle();
reg = (__raw_readl(MXC_CCM_CGCR0) & ~MXC_CCM_CGCR0_STOP_MODE_MASK) |
cgcr0;
__raw_writel(reg, MXC_CCM_CGCR0);
reg = (__raw_readl(MXC_CCM_CGCR1) & ~MXC_CCM_CGCR1_STOP_MODE_MASK) |
cgcr1;
__raw_writel(reg, MXC_CCM_CGCR1);
reg = (__raw_readl(MXC_CCM_CGCR2) & ~MXC_CCM_CGCR2_STOP_MODE_MASK) |
cgcr2;
__raw_writel(reg, MXC_CCM_CGCR2);
return 0;
}
/*
* Called after processes are frozen, but before we shut down devices.
*/
static int mx25_suspend_prepare(void)
{
cgcr0 = __raw_readl(MXC_CCM_CGCR0) & MXC_CCM_CGCR0_STOP_MODE_MASK;
cgcr1 = __raw_readl(MXC_CCM_CGCR1) & MXC_CCM_CGCR1_STOP_MODE_MASK;
cgcr2 = __raw_readl(MXC_CCM_CGCR2) & MXC_CCM_CGCR2_STOP_MODE_MASK;
return 0;
}
/*
* Called after devices are re-setup, but before processes are thawed.
*/
static void mx25_suspend_finish(void)
{
}
static int mx25_pm_valid(suspend_state_t state)
{
return state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX;
}
struct platform_suspend_ops mx25_suspend_ops = {
.valid = mx25_pm_valid,
.prepare = mx25_suspend_prepare,
.enter = mx25_suspend_enter,
.finish = mx25_suspend_finish,
};
static int __init mx25_pm_init(void)
{
pr_info("Static Power Management for Freescale i.MX25\n");
suspend_set_ops(&mx25_suspend_ops);
return 0;
}
late_initcall(mx25_pm_init);

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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*!
* @file sdma_script_code.h
* @brief This file contains functions of SDMA scripts code initialization
*
* The file was generated automatically. Based on sdma scripts library.
*
* @ingroup SDMA
*/
/************************************************************************
SDMA RELEASE LABEL: "SS15_SENNA"
************************************************************************/
#ifndef SDMA_SCRIPT_CODE_H
#define SDMA_SCRIPT_CODE_H
/*!
* SDMA ROM scripts start addresses and sizes
*/
#define start_ADDR 0
#define start_SIZE 22
#define core_ADDR 80
#define core_SIZE 233
#define common_ADDR 313
#define common_SIZE 416
#define ap_2_ap_ADDR 729
#define ap_2_ap_SIZE 41
#define app_2_mcu_ADDR 770
#define app_2_mcu_SIZE 64
#define mcu_2_app_ADDR 834
#define mcu_2_app_SIZE 70
#define uart_2_mcu_ADDR 904
#define uart_2_mcu_SIZE 75
#define shp_2_mcu_ADDR 979
#define shp_2_mcu_SIZE 69
#define mcu_2_shp_ADDR 1048
#define mcu_2_shp_SIZE 72
#define uartsh_2_mcu_ADDR 1120
#define uartsh_2_mcu_SIZE 69
#define app_2_per_ADDR 1189
#define app_2_per_SIZE 66
#define per_2_app_ADDR 1255
#define per_2_app_SIZE 74
#define per_2_shp_ADDR 1329
#define per_2_shp_SIZE 78
#define shp_2_per_ADDR 1407
#define shp_2_per_SIZE 72
#define mcu_2_ata_ADDR 1479
#define mcu_2_ata_SIZE 81
#define ata_2_mcu_ADDR 1560
#define ata_2_mcu_SIZE 96
#define loop_DMAs_routines_ADDR 1656
#define loop_DMAs_routines_SIZE 227
#define test_ADDR 1883
#define test_SIZE 63
#define signature_ADDR 1022
#define signature_SIZE 1
/*!
* SDMA RAM scripts start addresses and sizes
*/
#define ext_mem__ipu_ram_ADDR 6144
#define ext_mem__ipu_ram_SIZE 123
#define uart_2_per_ADDR 6267
#define uart_2_per_SIZE 73
#define uartsh_2_per_ADDR 6340
#define uartsh_2_per_SIZE 67
/*!
* SDMA RAM image start address and size
*/
#define RAM_CODE_START_ADDR 6144
#define RAM_CODE_SIZE 263
/*!
* Buffer that holds the SDMA RAM image
*/
__attribute__ ((__aligned__(4)))
#ifndef CONFIG_XIP_KERNEL
const
#endif
static const short sdma_code[] = {
0x0e70, 0x0611, 0x5616, 0xc18a, 0x7d2a, 0x5ade, 0x008e, 0xc19c,
0x7c26, 0x5be0, 0x5ef0, 0x5ce8, 0x0688, 0x08ff, 0x0011, 0x28ff,
0x00bc, 0x53f6, 0x05df, 0x7d0b, 0x6dc5, 0x03df, 0x7d03, 0x6bd5,
0xd84f, 0x982b, 0x6b05, 0xc6d8, 0x7e27, 0x7f29, 0x982b, 0x6d01,
0x03df, 0x7d05, 0x6bd5, 0xc702, 0x7e18, 0x7f1a, 0x982b, 0x6b05,
0xc678, 0x7e07, 0x7f06, 0x52de, 0x53e6, 0xc1a8, 0x7dd7, 0x0200,
0x9803, 0x0007, 0x6004, 0x680c, 0x53f6, 0x028e, 0x00a3, 0xc2ad,
0x048b, 0x0498, 0x0454, 0x068a, 0x982b, 0x0207, 0x680c, 0x6ddf,
0x0107, 0x68ff, 0x60d0, 0x9834, 0x0207, 0x68ff, 0x6d28, 0x0107,
0x6004, 0x680c, 0x9834, 0x0007, 0x68ff, 0x60d0, 0x9834, 0x0288,
0x03a5, 0x3b03, 0x3d03, 0x4d00, 0x7d0a, 0x0804, 0x00a5, 0x00da,
0x7d1a, 0x02a0, 0x7b01, 0x65d8, 0x7eee, 0x65ff, 0x7eec, 0x0804,
0x02d0, 0x7d11, 0x4b00, 0x7c0f, 0x008a, 0x3003, 0x6dcf, 0x6bdf,
0x0015, 0x0015, 0x7b02, 0x65d8, 0x0000, 0x7edd, 0x63ff, 0x7edb,
0x3a03, 0x6dcd, 0x6bdd, 0x008a, 0x7b02, 0x65d8, 0x0000, 0x7ed3,
0x65ff, 0x7ed1, 0x0006, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb,
0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3,
0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb,
0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501,
0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260,
0x7df1, 0x62d0, 0xc2d1, 0x98c0, 0x6ee3, 0x008f, 0x2001, 0x00d5,
0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a,
0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc251,
0x57db, 0x987f, 0x0007, 0x6aff, 0x62d0, 0xc2d1, 0x0458, 0x0454,
0x6add, 0x7ff8, 0xc261, 0x987c, 0xc230, 0xc23a, 0x57db, 0x52f3,
0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94,
0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8,
0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260,
0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc2d1, 0x9903, 0x008f, 0x2001,
0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8,
0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b,
0xc251, 0x57db, 0x98c9, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0,
0xc2d1, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc261, 0x98c6
};
#endif

263
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx25/serial.c
*
* @brief This file contains the UART initiliazation.
*
* @ingroup MSL_MX25
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <mach/hardware.h>
#include <mach/mxc_uart.h>
#include <mach/spba.h>
#include "serial.h"
#include "board-mx25_3stack.h"
#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
/*!
* This is an array where each element holds information about a UART port,
* like base address of the UART, interrupt numbers etc. This structure is
* passed to the serial_core.c file. Based on which UART is used, the core file
* passes back the appropriate port structure as an argument to the control
* functions.
*/
static uart_mxc_port mxc_ports[] = {
[0] = {
.port = {
.membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
.mapbase = UART1_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART1_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.ints_muxed = UART1_MUX_INTS,
.irqs = {UART1_INT2, UART1_INT3},
.mode = UART1_MODE,
.ir_mode = UART1_IR,
.enabled = UART1_ENABLED,
.hardware_flow = UART1_HW_FLOW,
.cts_threshold = UART1_UCR4_CTSTL,
.dma_enabled = UART1_DMA_ENABLE,
.dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
.rx_threshold = UART1_UFCR_RXTL,
.tx_threshold = UART1_UFCR_TXTL,
.shared = UART1_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART1_TX,
.dma_rx_id = MXC_DMA_UART1_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
[1] = {
.port = {
.membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
.mapbase = UART2_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART2_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 1,
},
.ints_muxed = UART2_MUX_INTS,
.irqs = {UART2_INT2, UART2_INT3},
.mode = UART2_MODE,
.ir_mode = UART2_IR,
.enabled = UART2_ENABLED,
.hardware_flow = UART2_HW_FLOW,
.cts_threshold = UART2_UCR4_CTSTL,
.dma_enabled = UART2_DMA_ENABLE,
.dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
.rx_threshold = UART2_UFCR_RXTL,
.tx_threshold = UART2_UFCR_TXTL,
.shared = UART2_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART2_TX,
.dma_rx_id = MXC_DMA_UART2_RX,
.rxd_mux = MXC_UART_IR_RXDMUX,
},
#if UART3_ENABLED == 1
[2] = {
.port = {
.membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
.mapbase = UART3_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART3_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 2,
},
.ints_muxed = UART3_MUX_INTS,
.irqs = {UART3_INT2, UART3_INT3},
.mode = UART3_MODE,
.ir_mode = UART3_IR,
.enabled = UART3_ENABLED,
.hardware_flow = UART3_HW_FLOW,
.cts_threshold = UART3_UCR4_CTSTL,
.dma_enabled = UART3_DMA_ENABLE,
.dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
.rx_threshold = UART3_UFCR_RXTL,
.tx_threshold = UART3_UFCR_TXTL,
.shared = UART3_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART3_TX,
.dma_rx_id = MXC_DMA_UART3_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
#endif
#if UART4_ENABLED == 1
[3] = {
.port = {
.membase = (void *)IO_ADDRESS(UART4_BASE_ADDR),
.mapbase = UART4_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART4_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 3,
},
.ints_muxed = UART4_MUX_INTS,
.irqs = {UART4_INT2, UART4_INT3},
.mode = UART4_MODE,
.ir_mode = UART4_IR,
.enabled = UART4_ENABLED,
.hardware_flow = UART4_HW_FLOW,
.cts_threshold = UART4_UCR4_CTSTL,
.dma_enabled = UART4_DMA_ENABLE,
.dma_rxbuf_size = UART4_DMA_RXBUFSIZE,
.rx_threshold = UART4_UFCR_RXTL,
.tx_threshold = UART4_UFCR_TXTL,
.shared = UART4_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART4_TX,
.dma_rx_id = MXC_DMA_UART4_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
#endif
#if UART5_ENABLED == 1
[4] = {
.port = {
.membase = (void *)IO_ADDRESS(UART5_BASE_ADDR),
.mapbase = UART5_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART5_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 4,
},
.ints_muxed = UART5_MUX_INTS,
.irqs = {UART5_INT2, UART5_INT3},
.mode = UART5_MODE,
.ir_mode = UART5_IR,
.enabled = UART5_ENABLED,
.hardware_flow = UART5_HW_FLOW,
.cts_threshold = UART5_UCR4_CTSTL,
.dma_enabled = UART5_DMA_ENABLE,
.dma_rxbuf_size = UART5_DMA_RXBUFSIZE,
.rx_threshold = UART5_UFCR_RXTL,
.tx_threshold = UART5_UFCR_TXTL,
.shared = UART5_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART5_TX,
.dma_rx_id = MXC_DMA_UART5_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
#endif
};
static struct platform_device mxc_uart_device1 = {
.name = "mxcintuart",
.id = 0,
.dev = {
.platform_data = &mxc_ports[0],
},
};
static struct platform_device mxc_uart_device2 = {
.name = "mxcintuart",
.id = 1,
.dev = {
.platform_data = &mxc_ports[1],
},
};
#if UART3_ENABLED == 1
static struct platform_device mxc_uart_device3 = {
.name = "mxcintuart",
.id = 2,
.dev = {
.platform_data = &mxc_ports[2],
},
};
#endif
#if UART4_ENABLED == 1
static struct platform_device mxc_uart_device4 = {
.name = "mxcintuart",
.id = 3,
.dev = {
.platform_data = &mxc_ports[3],
},
};
#endif
#if UART5_ENABLED == 1
static struct platform_device mxc_uart_device5 = {
.name = "mxcintuart",
.id = 4,
.dev = {
.platform_data = &mxc_ports[4],
},
};
#endif
static int __init mxc_init_uart(void)
{
/* Register all the MXC UART platform device structures */
platform_device_register(&mxc_uart_device1);
platform_device_register(&mxc_uart_device2);
/* Grab ownership of shared UARTs 3 and 4, only when enabled */
#if UART3_ENABLED == 1
#if UART3_DMA_ENABLE == 1
spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C));
#else
spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A);
#endif /* UART3_DMA_ENABLE */
platform_device_register(&mxc_uart_device3);
#endif /* UART3_ENABLED */
#if UART4_ENABLED == 1
#if UART4_DMA_ENABLE == 1
spba_take_ownership(UART4_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C));
#else
spba_take_ownership(UART4_SHARED_PERI, SPBA_MASTER_A);
#endif /* UARTr_DMA_ENABLE */
platform_device_register(&mxc_uart_device4);
#endif /* UART4_ENABLED */
#if UART5_ENABLED == 1
#if UART5_DMA_ENABLE == 1
spba_take_ownership(UART5_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C));
#else
spba_take_ownership(UART5_SHARED_PERI, SPBA_MASTER_A);
#endif /* UART5_DMA_ENABLE */
platform_device_register(&mxc_uart_device5);
#endif /* UART5_ENABLED */
return 0;
}
#else
static int __init mxc_init_uart(void)
{
return 0;
}
#endif
arch_initcall(mxc_init_uart);

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX25_SERIAL_H__
#define __ARCH_ARM_MACH_MX25_SERIAL_H__
/*!
* @file mach-mx25/serial.h
*
* @ingroup MSL_MX25
*/
#include <mach/mxc_uart.h>
/* UART 1 configuration */
/*!
* This option allows to choose either an interrupt-driven software controlled
* hardware flow control (set this option to 0) or hardware-driven hardware
* flow control (set this option to 1).
*/
#define UART1_HW_FLOW 1
/*!
* This specifies the threshold at which the CTS pin is deasserted by the
* RXFIFO. Set this value in Decimal to anything from 0 to 32 for
* hardware-driven hardware flow control. Read the HW spec while specifying
* this value. When using interrupt-driven software controlled hardware
* flow control set this option to -1.
*/
#define UART1_UCR4_CTSTL 16
/*!
* This is option to enable (set this option to 1) or disable DMA data transfer
*/
#define UART1_DMA_ENABLE 0
/*!
* Specify the size of the DMA receive buffer. The minimum buffer size is 512
* bytes. The buffer size should be a multiple of 256.
*/
#define UART1_DMA_RXBUFSIZE 1024
/*!
* Specify the MXC UART's Receive Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the RxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_RXTL 16
/*!
* Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the TxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_TXTL 16
/* UART 2 configuration */
#define UART2_HW_FLOW 0
#define UART2_UCR4_CTSTL (-1)
#define UART2_DMA_ENABLE 0
#define UART2_DMA_RXBUFSIZE 512
#define UART2_UFCR_RXTL 16
#define UART2_UFCR_TXTL 16
/* UART 3 configuration */
#define UART3_HW_FLOW 1
#define UART3_UCR4_CTSTL 16
#define UART3_DMA_ENABLE 1
#define UART3_DMA_RXBUFSIZE 1024
#define UART3_UFCR_RXTL 16
#define UART3_UFCR_TXTL 16
/* UART 4 configuration */
#define UART4_HW_FLOW 1
#define UART4_UCR4_CTSTL 16
#define UART4_DMA_ENABLE 1
#define UART4_DMA_RXBUFSIZE 1024
#define UART4_UFCR_RXTL 16
#define UART4_UFCR_TXTL 16
/* UART 5 configuration */
#define UART5_HW_FLOW 1
#define UART5_UCR4_CTSTL 16
#define UART5_DMA_ENABLE 1
#define UART5_DMA_RXBUFSIZE 1024
#define UART5_UFCR_RXTL 16
#define UART5_UFCR_TXTL 16
/*
* UART Chip level Configuration that a user may not have to edit. These
* configuration vary depending on how the UART module is integrated with
* the ARM core
*/
/*
* Is the MUXED interrupt output sent to the ARM core
*/
#define INTS_NOTMUXED 0
#define INTS_MUXED 1
/* UART 1 configuration */
/*!
* This define specifies whether the muxed ANDed interrupt line or the
* individual interrupts from the UART port is integrated with the ARM core.
* There exists a define like this for each UART port. Valid values that can
* be used are \b INTS_NOTMUXED or \b INTS_MUXED.
*/
#define UART1_MUX_INTS INTS_MUXED
/*!
* This define specifies the transmitter interrupt number or the interrupt
* number of the ANDed interrupt in case the interrupts are muxed. There exists
* a define like this for each UART port.
*/
#define UART1_INT1 MXC_INT_UART1
/*!
* This define specifies the receiver interrupt number. If the interrupts of
* the UART are muxed, then we specify here a dummy value -1. There exists a
* define like this for each UART port.
*/
#define UART1_INT2 (-1)
/*!
* This specifies the master interrupt number. If the interrupts of the UART
* are muxed, then we specify here a dummy value of -1. There exists a define
* like this for each UART port.
*/
#define UART1_INT3 (-1)
/*!
* This specifies if the UART is a shared peripheral. It holds the shared
* peripheral number if it is shared or -1 if it is not shared. There exists
* a define like this for each UART port.
*/
#define UART1_SHARED_PERI (-1)
/* UART 2 configuration */
#define UART2_MUX_INTS INTS_MUXED
#define UART2_INT1 MXC_INT_UART2
#define UART2_INT2 (-1)
#define UART2_INT3 (-1)
#define UART2_SHARED_PERI (-1)
/* UART 3 configuration */
#define UART3_MUX_INTS INTS_MUXED
#define UART3_INT1 MXC_INT_UART3
#define UART3_INT2 (-1)
#define UART3_INT3 (-1)
#define UART3_SHARED_PERI SPBA_UART3
/* UART 4 configuration */
#define UART4_MUX_INTS INTS_MUXED
#define UART4_INT1 MXC_INT_UART4
#define UART4_INT2 (-1)
#define UART4_INT3 (-1)
#define UART4_SHARED_PERI SPBA_UART4
/* UART 5 configuration */
#define UART5_MUX_INTS INTS_MUXED
#define UART5_INT1 MXC_INT_UART5
#define UART5_INT2 (-1)
#define UART5_INT3 (-1)
#define UART5_SHARED_PERI SPBA_UART5
#endif /* __ARCH_ARM_MACH_MX25_SERIAL_H__ */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <mach/hardware.h>
#include <asm/proc-fns.h>
#include <asm/system.h>
#include <mach/clock.h>
#include "crm_regs.h"
/*!
* @defgroup MSL_MX25 i.MX25 Machine Specific Layer (MSL)
*/
/*!
* @file mach-mx25/system.c
* @brief This file contains idle and reset functions.
*
* @ingroup MSL_MX25
*/
/*!
* MX25 low-power mode
*/
enum mx25_low_pwr_mode {
MX25_RUN_MODE,
MX25_WAIT_MODE,
MX25_DOZE_MODE,
MX25_STOP_MODE
};
extern int mxc_jtag_enabled;
/*!
* This function is used to set cpu low power mode before WFI instruction
*
* @param mode indicates different kinds of power modes
*/
void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
unsigned int lpm;
unsigned long reg;
unsigned int pmcr2, lpimr;
unsigned int cgcr0, cgcr1, cgcr2;
struct irq_desc *desc;
int i;
/*read CCTL value */
reg = __raw_readl(MXC_CCM_CCTL);
switch (mode) {
case WAIT_UNCLOCKED_POWER_OFF:
lpm = MX25_DOZE_MODE;
break;
case STOP_POWER_ON:
case STOP_POWER_OFF:
lpm = MX25_STOP_MODE;
/* The clock of LCDC/SLCDC, SDMA, RTIC, RNGC, MAX, CAN
and EMI needs to be gated on when entering Stop mode.
*/
cgcr0 = __raw_readl(MXC_CCM_CGCR0);
cgcr1 = __raw_readl(MXC_CCM_CGCR1);
cgcr2 = __raw_readl(MXC_CCM_CGCR2);
__raw_writel(cgcr0 | MXC_CCM_CGCR0_STOP_MODE_MASK,
MXC_CCM_CGCR0);
__raw_writel(cgcr1 | MXC_CCM_CGCR1_STOP_MODE_MASK,
MXC_CCM_CGCR1);
__raw_writel(cgcr2 | MXC_CCM_CGCR2_STOP_MODE_MASK,
MXC_CCM_CGCR2);
/* The interrupts which are not wake-up sources need
be mask when entering Stop mode.
*/
lpimr = MXC_CCM_LPIMR0_MASK;
for (i = 0; i < 32; i++) {
desc = irq_desc + i;
if ((desc->status & IRQ_WAKEUP) != 0)
lpimr &= ~(1 << i);
}
__raw_writel(lpimr, MXC_CCM_LPIMR0);
lpimr = MXC_CCM_LPIMR1_MASK;
for (i = 32; i < 64; i++) {
desc = irq_desc + i;
if ((desc->status & IRQ_WAKEUP) != 0)
lpimr &= ~(1 << (i - 32));
}
__raw_writel(lpimr, MXC_CCM_LPIMR1);
if (mode == STOP_POWER_OFF) {
pmcr2 = __raw_readl(MXC_CCM_PMCR2);
pmcr2 |= (MXC_CCM_PMCR2_OSC24M_DOWN |
MXC_CCM_PMCR2_VSTBY);
__raw_writel(pmcr2, MXC_CCM_PMCR2);
}
break;
case WAIT_CLOCKED:
case WAIT_UNCLOCKED:
default:
/* Wait is the default mode used when idle. */
lpm = MX25_WAIT_MODE;
break;
}
/* program LP CTL bit */
reg = ((reg & (~MXC_CCM_CCTL_LP_CTL_MASK)) |
lpm << MXC_CCM_CCTL_LP_CTL_OFFSET);
__raw_writel(reg, MXC_CCM_CCTL);
}
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks.
*/
if (!mxc_jtag_enabled) {
/* set as Wait mode */
mxc_cpu_lp_set(WAIT_UNCLOCKED);
cpu_do_idle();
}
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
void arch_reset(char mode)
{
/* Assert SRS signal */
mxc_wd_reset();
}

103
arch/arm/mach-mx25/usb.h Normal file
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@@ -0,0 +1,103 @@
/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
extern int usbotg_init(struct platform_device *pdev);
extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
extern int gpio_usbotg_utmi_active(void);
extern void gpio_usbotg_utmi_inactive(void);
extern struct platform_device *host_pdev_register(struct resource *res,
int n_res,
struct fsl_usb2_platform_data
*config);
extern int fsl_usb_host_init(struct platform_device *pdev);
extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
extern int gpio_usbh2_active(void);
extern void gpio_usbh2_inactive(void);
/*
* Determine which platform_data struct to use for the DR controller,
* based on which transceiver is configured.
* PDATA is a pointer to it.
*/
static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config;
#define PDATA (&dr_utmi_config)
/*
* Used to set pdata->operating_mode before registering the platform_device.
* If OTG is configured, the controller operates in OTG mode,
* otherwise it's either host or device.
*/
#ifdef CONFIG_USB_OTG
#define DR_UDC_MODE FSL_USB2_DR_OTG
#define DR_HOST_MODE FSL_USB2_DR_OTG
#else
#define DR_UDC_MODE FSL_USB2_DR_DEVICE
#define DR_HOST_MODE FSL_USB2_DR_HOST
#endif
#ifdef CONFIG_USB_EHCI_ARC_OTG
static inline void dr_register_host(struct resource *r, int rs)
{
PDATA->operating_mode = DR_HOST_MODE;
host_pdev_register(r, rs, PDATA);
}
#else
static inline void dr_register_host(struct resource *r, int rs)
{
}
#endif
#ifdef CONFIG_USB_GADGET_ARC
static struct platform_device dr_udc_device;
static inline void dr_register_udc(void)
{
PDATA->operating_mode = DR_UDC_MODE;
dr_udc_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_udc_device))
printk(KERN_ERR "usb: can't register DR gadget\n");
else
printk(KERN_INFO "usb: DR gadget (%s) registered\n",
PDATA->transceiver);
}
#else
static inline void dr_register_udc(void)
{
}
#endif
#ifdef CONFIG_USB_OTG
static struct platform_device dr_otg_device;
/*
* set the proper operating_mode and
* platform_data pointer, then register the
* device.
*/
static inline void dr_register_otg(void)
{
PDATA->operating_mode = FSL_USB2_DR_OTG;
dr_otg_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_otg_device))
printk(KERN_ERR "usb: can't register otg device\n");
else
printk(KERN_INFO "usb: DR OTG registered\n");
}
#else
static inline void dr_register_otg(void)
{
}
#endif

102
arch/arm/mach-mx25/usb_dr.c Normal file
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@@ -0,0 +1,102 @@
/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
/*
* platform data structs
* - Which one to use is determined by CONFIG options in usb.h
* - operating_mode plugged at run time
*/
static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
.name = "DR",
.platform_init = usbotg_init,
.platform_uninit = usbotg_uninit,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
.power_budget = 500, /* via RT9706 */
.gpio_usb_active = gpio_usbotg_utmi_active,
.gpio_usb_inactive = gpio_usbotg_utmi_inactive,
.transceiver = "utmi",
};
/*
* resources
*/
static struct resource otg_resources[] = {
[0] = {
.start = (u32)(USB_OTGREGS_BASE),
.end = (u32)(USB_OTGREGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USB_OTG,
.flags = IORESOURCE_IRQ,
},
};
static u64 dr_udc_dmamask = ~(u32) 0;
static void dr_udc_release(struct device *dev)
{
}
static u64 dr_otg_dmamask = ~(u32) 0;
static void dr_otg_release(struct device *dev)
{
}
/*
* platform device structs
* dev.platform_data field plugged at run time
*/
static struct platform_device __maybe_unused dr_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.release = dr_udc_release,
.dma_mask = &dr_udc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static struct platform_device __maybe_unused dr_otg_device = {
.name = "fsl-usb2-otg",
.id = -1,
.dev = {
.release = dr_otg_release,
.dma_mask = &dr_otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static int __init usb_dr_init(void)
{
pr_debug("%s: \n", __func__);
dr_register_otg();
dr_register_host(otg_resources, ARRAY_SIZE(otg_resources));
dr_register_udc();
return 0;
}
module_init(usb_dr_init);

88
arch/arm/mach-mx25/usb_h2.c Normal file
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@@ -0,0 +1,88 @@
/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/usb/fsl_xcvr.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
static struct fsl_usb2_platform_data usbh2_config = {
.name = "Host 2",
.platform_init = fsl_usb_host_init,
.platform_uninit = fsl_usb_host_uninit,
.operating_mode = FSL_USB2_MPH_HOST,
.phy_mode = FSL_USB2_PHY_SERIAL,
.power_budget = 500, /* via RT9702 */
.gpio_usb_active = gpio_usbh2_active,
.gpio_usb_inactive = gpio_usbh2_inactive,
.transceiver = "serial", /* on-chip */
};
static struct resource usbh2_resources[] = {
[0] = {
.start = (u32) (USB_H2REGS_BASE),
.end = (u32) (USB_H2REGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USB_HTG,
.flags = IORESOURCE_IRQ,
},
};
void usbh2_get_xcvr_power(struct device *dev)
{
struct regulator *usbh2_regux;
usbh2_regux = regulator_get(dev, "GPO1");
regulator_enable(usbh2_regux);
((struct fsl_usb2_platform_data *)dev->platform_data)->
xcvr_pwr->regu1 = usbh2_regux;
usbh2_regux = regulator_get(dev, "GPO3");
regulator_enable(usbh2_regux);
((struct fsl_usb2_platform_data *)dev->platform_data)->
xcvr_pwr->regu2 = usbh2_regux;
}
EXPORT_SYMBOL(usbh2_get_xcvr_power);
void usbh2_put_xcvr_power(struct device *dev)
{
struct regulator *usbh2_regux;
usbh2_regux = ((struct fsl_usb2_platform_data *)dev->
platform_data)->xcvr_pwr->regu2;
regulator_disable(usbh2_regux);
regulator_put(usbh2_regux);
usbh2_regux = ((struct fsl_usb2_platform_data *)dev->
platform_data)->xcvr_pwr->regu1;
regulator_disable(usbh2_regux);
regulator_put(usbh2_regux);
}
EXPORT_SYMBOL(usbh2_put_xcvr_power);
static int __init usbh2_init(void)
{
pr_debug("%s: \n", __func__);
host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
&usbh2_config);
return 0;
}
module_init(usbh2_init);

86
arch/arm/mach-mx3/Kconfig
View File

@@ -4,9 +4,17 @@ config ARCH_MX31
select ARCH_HAS_RNGA
bool
config ARCH_MX35
config MX3_OPTIONS
bool
select ARCH_MXC_IOMUX_V3
default y
select CPU_V6
select ARM_ERRATA_364296
select ARM_ERRATA_411920
select CACHE_L2X0
select OUTER_CACHE
select USB_ARCH_HAS_EHCI
select ARCH_HAS_EVTMON
select ARCH_HAS_RNGA
comment "MX3 platforms:"
@@ -81,7 +89,7 @@ config MACH_QONG
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35
# select ARCH_MX35
help
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
@@ -92,12 +100,72 @@ config MACH_ARMADILLO5X0
help
Include support for Atmark Armadillo-500 platform. This includes
specific configurations for the board and its peripherals.
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
default n
config MXC_SDMA_API
bool "Use SDMA API"
default y
help
This selects the Freescale MXC SDMA API.
If unsure, say N.
menu "SDMA options"
depends on MXC_SDMA_API
config SDMA_IRAM
bool "Use Internal RAM for SDMA transfer"
default n
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
Support Internal RAM as SDMA buffer or control structures
config SDMA_IRAM_SIZE
hex "Reserved bytes of IRAM for SDMA (0x800-0x2000)"
range 0x800 0x2000
depends on SDMA_IRAM
default "0x1000"
help
Set the size of IRAM for SDMA. It must be multiple of 512bytes.
endmenu
config ARCH_MXC_HAS_NFC_V1
bool "MXC NFC Hardware Version 1"
depends on !(MACH_MX31ADS && XIP_KERNEL)
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 1
If unsure, say N.
config ARCH_MXC_HAS_NFC_V2
bool "MXC NFC Hardware Version 2"
depends on !(MACH_MX31ADS && XIP_KERNEL)
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 2
If unsure, say N.
menu "Device options"
config I2C_MXC_SELECT1
bool "Enable I2C1 module"
default y
depends on I2C_MXC
help
Enable MX31 I2C1 module.
config I2C_MXC_SELECT2
bool "Enable I2C2 module"
default n
depends on I2C_MXC
help
Enable MX31 I2C2 module.
config I2C_MXC_SELECT3
bool "Enable I2C3 module"
default n
depends on I2C_MXC
help
Enable MX31 I2C3 module.
endmenu
endif

19
arch/arm/mach-mx3/Makefile
View File

@@ -4,18 +4,25 @@
# Object file lists.
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
obj-y := system.o iomux.o cpu.o mm.o clock.o dptc.o devices.o serial.o dma.o mxc_pm.o dvfs_v2.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o mx31ads_gpio.o
obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
obj-$(CONFIG_MACH_PCM037) += pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o
obj-$(CONFIG_MACH_MX31_3DS) += mx3_3stack.o mx3_3stack_gpio.o mx3_3stack_pmic_mc13783.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o
obj-$(CONFIG_MACH_QONG) += qong.o
obj-$(CONFIG_MACH_PCM043) += pcm043.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o
obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o
# power management
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o
ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
obj-y += usb_dr.o
endif

329
arch/arm/mach-mx3/board-mx31ads.h Normal file
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@@ -0,0 +1,329 @@
/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#ifdef CONFIG_MACH_MX31ADS
/*!
* @defgroup BRDCFG_MX31 Board Configuration Options
* @ingroup MSL_MX31
*/
/*!
* @file mach-mx3/board-mx31ads.h
*
* @brief This file contains all the board level configuration options.
*
* It currently hold the options defined for MX31 ADS Platform.
*
* @ingroup BRDCFG_MX31
*/
/*
* Include Files
*/
#include <mach/mxc_uart.h>
/*!
* @name MXC UART EVB board level configurations
*/
/*! @{ */
/*!
* Specifies if the Irda transmit path is inverting
*/
#define MXC_IRDA_TX_INV 0
/*!
* Specifies if the Irda receive path is inverting
*/
#define MXC_IRDA_RX_INV 0
/* UART 1 configuration */
/*!
* This define specifies if the UART port is configured to be in DTE or
* DCE mode. There exists a define like this for each UART port. Valid
* values that can be used are \b MODE_DTE or \b MODE_DCE.
*/
#define UART1_MODE MODE_DCE
/*!
* This define specifies if the UART is to be used for IRDA. There exists a
* define like this for each UART port. Valid values that can be used are
* \b IRDA or \b NO_IRDA.
*/
#define UART1_IR NO_IRDA
/*!
* This define is used to enable or disable a particular UART port. If
* disabled, the UART will not be registered in the file system and the user
* will not be able to access it. There exists a define like this for each UART
* port. Specify a value of 1 to enable the UART and 0 to disable it.
*/
#define UART1_ENABLED 1
/*! @} */
/* UART 2 configuration */
#define UART2_MODE MODE_DCE
#define UART2_IR IRDA
#ifdef CONFIG_MXC_FIR_MODULE
#define UART2_ENABLED 0
#else
#define UART2_ENABLED 1
#endif
/* UART 3 configuration */
#define UART3_MODE MODE_DTE
#define UART3_IR NO_IRDA
#define UART3_ENABLED 1
/* UART 4 configuration */
#define UART4_MODE MODE_DTE
#define UART4_IR NO_IRDA
#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */
/* UART 5 configuration */
#define UART5_MODE MODE_DTE
#define UART5_IR NO_IRDA
#define UART5_ENABLED 1
#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x10000)
#define MXC_LL_EXTUART_VADDR CS4_IO_ADDRESS(MXC_LL_EXTUART_PADDR)
#undef MXC_LL_EXTUART_16BIT_BUS
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
/*!
* @name PBC Controller parameters
*/
/*! @{ */
/*!
* Base address of PBC controller
*/
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
/* Offsets for the PBC Controller register */
/*!
* PBC Board status register offset
*/
#define PBC_BSTAT 0x000002
/*!
* PBC Board control register 1 set address.
*/
#define PBC_BCTRL1_SET 0x000004
/*!
* PBC Board control register 1 clear address.
*/
#define PBC_BCTRL1_CLEAR 0x000006
/*!
* PBC Board control register 2 set address.
*/
#define PBC_BCTRL2_SET 0x000008
/*!
* PBC Board control register 2 clear address.
*/
#define PBC_BCTRL2_CLEAR 0x00000A
/*!
* PBC Board control register 3 set address.
*/
#define PBC_BCTRL3_SET 0x00000C
/*!
* PBC Board control register 3 clear address.
*/
#define PBC_BCTRL3_CLEAR 0x00000E
/*!
* PBC Board control register 4 set address.
*/
#define PBC_BCTRL4_SET 0x000010
/*!
* PBC Board control register 4 clear address.
*/
#define PBC_BCTRL4_CLEAR 0x000012
/*!
* PBC Board status register 1.
*/
#define PBC_BSTAT1 0x000014
/*!
* PBC Board interrupt status register.
*/
#define PBC_INTSTATUS 0x000016
/*!
* PBC Board interrupt current status register.
*/
#define PBC_INTCURR_STATUS 0x000018
/*!
* PBC Interrupt mask register set address.
*/
#define PBC_INTMASK_SET 0x00001A
/*!
* PBC Interrupt mask register clear address.
*/
#define PBC_INTMASK_CLEAR 0x00001C
/*!
* External UART A.
*/
#define PBC_SC16C652_UARTA 0x010000
/*!
* External UART B.
*/
#define PBC_SC16C652_UARTB 0x010010
/*!
* Ethernet Controller IO base address.
*/
#define PBC_CS8900A_IOBASE 0x020000
/*!
* Ethernet Controller Memory base address.
*/
#define PBC_CS8900A_MEMBASE 0x021000
/*!
* Ethernet Controller DMA base address.
*/
#define PBC_CS8900A_DMABASE 0x022000
/*!
* External chip select 0.
*/
#define PBC_XCS0 0x040000
/*!
* LCD Display enable.
*/
#define PBC_LCD_EN_B 0x060000
/*!
* Code test debug enable.
*/
#define PBC_CODE_B 0x070000
/*!
* PSRAM memory select.
*/
#define PBC_PSRAM_B 0x5000000
/* PBC Board Status Register 1 bit definitions */
#define PBC_BSTAT1_NF_DET 0x0001 /* NAND flash card. 0 = connected */
#define PBC_BSTAT1_KP_ON 0x0002 /* KPP board. 0 = connected */
#define PBC_BSTAT1_LS 0x0004 /* KPP:LightSense signal */
#define PBC_BSTAT1_ATA_IOCS16 0x0008 /* ATA_IOCS16 signal */
#define PBC_BSTAT1_ATA_CBLID 0x0010 /* ATA_CBLID signal */
#define PBC_BSTAT1_ATA_DASP 0x0020 /* ATA_DASP signal */
#define PBC_BSTAT1_PWR_RDY 0x0040 /* MC13783 power. 1 = ready */
#define PBC_BSTAT1_SD1_WP 0x0080 /* 0 = SD1 card is write protected */
#define PBC_BSTAT1_SD2_WP 0x0100 /* 0 = SD2 card is write protected */
#define PBC_BSTAT1_FS1 0x0200 /* KPP:FlipSense1 signal */
#define PBC_BSTAT1_FS2 0x0400 /* KPP:FlipSense2 signal */
#define PBC_BSTAT1_PTT 0x0800 /* KPP:PTT signal */
#define PBC_BSTAT1_MC13783_IN 0x1000 /* MC13783 board. 0 = connected. */
/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
#define PBC_BCTRL1_UENA 0x0004 /* Enable UART A transceiver */
#define PBC_BCTRL1_UENB 0x0008 /* Enable UART B transceiver */
#define PBC_BCTRL1_UENCE 0x0010 /* Enable UART CE transceiver */
#define PBC_BCTRL1_IREN 0x0020 /* Enable the IRDA transmitter */
#define PBC_BCTRL1_LED0 0x0040 /* Used to control LED 0 (green) */
#define PBC_BCTRL1_LED1 0x0080 /* Used to control LED 1 (yellow) */
#define PBC_BCTRL1_SENSOR1_ON 0x0600 /* Enable Sensor 1 */
#define PBC_BCTRL1_SENSOR2_ON 0x3000 /* Enable Sensor 2 */
#define PBC_BCTRL1_BEND 0x4000 /* Big Endian Select */
#define PBC_BCTRL1_LCDON 0x8000 /* Enable the LCD */
/* PBC Board Control Register 2 bit definitions */
#define PBC_BCTRL2_USELA 0x0001 /* UART A Select, 0 = UART1, 1 = UART5 */
#define PBC_BCTRL2_USELB 0x0002 /* UART B Select, 0 = UART3, 1 = UART5 */
#define PBC_BCTRL2_USELC 0x0004 /* UART C Select, 0 = UART2, 1 = UART1 */
#define PBC_BCTRL2_UMODENA 0x0008 /* UART A Modem Signals Enable, 0 = enabled */
#define PBC_BCTRL2_UMODENC 0x0008 /* UART C Modem Signals Enable, 0 = enabled */
#define PBC_BCTRL2_CSI_EN 0x0020 /* Enable the CSI interface, 0 = enabled */
#define PBC_BCTRL2_ATA_EN 0x0040 /* Enable the ATA interface, 0 = enabled */
#define PBC_BCTRL2_ATA_SEL 0x0080 /* ATA Select, 0 = group A, 1 = group B */
#define PBC_BCTRL2_IRDA_MOD 0x0100 /* IRDA Mode (see CPLD spec) */
#define PBC_BCTRL2_LDC_RST0 0x0200 /* LCD 0 Reset, 1 = reset signal asserted */
#define PBC_BCTRL2_LDC_RST1 0x0400 /* LCD 1 Reset, 1 = reset signal asserted */
#define PBC_BCTRL2_LDC_RST2 0x0800 /* LCD 2 Reset, 1 = reset signal asserted */
#define PBC_BCTRL2_LDCIO_EN 0x1000 /* LCD GPIO Enable, 0 = enabled */
#define PBC_BCTRL2_CT_CS 0x2000 /* Code Test Chip Select, = Code Test selected */
#define PBC_BCTRL2_VPP_EN 0x4000 /* PCMCIA VPP Enable, 1 = power on */
#define PBC_BCTRL2_VCC_EN 0x8000 /* PCMCIA VCC Enable, 1 = power on */
/* PBC Board Control Register 3 bit definitions */
#define PBC_BCTRL3_OTG_FS_SEL 0x0001 /* USB OTG Full Speed Select, 0 = PMIC, 1 = CPU */
#define PBC_BCTRL3_OTG_FS_EN 0x0002 /* USB OTG Full Speed Enable, 0 = enabled */
#define PBC_BCTRL3_FSH_SEL 0x0004 /* USB Full Speed Host Select, 0 = Group A, 1 = Group B */
#define PBC_BCTRL3_FSH_EN 0x0008 /* USB Full Speed Host Enable, 0 = enabled */
#define PBC_BCTRL3_HSH_SEL 0x0010 /* USB High Speed Host Select, 0 = Group A, 1 = Group B */
#define PBC_BCTRL3_HSH_EN 0x0020 /* USB High Speed Host Enable, 0 = enabled */
#define PBC_BCTRL3_FSH_MOD 0x0040 /* USB Full Speed Host Mode, 0 = Differential, 1 = Single ended */
#define PBC_BCTRL3_OTG_HS_EN 0x0080 /* USB OTG High Speed Enable, 0 = enabled */
#define PBC_BCTRL3_OTG_VBUS_EN 0x0100 /* USB OTG VBUS Regulator Enable, 0 = enabled */
#define PBC_BCTRL3_FSH_VBUS_EN 0x0200 /* USB Full Speed Host VBUS Regulator Enable, 0 = enabled */
#define PBC_BCTRL3_CARD1_SEL 0x0400 /* Card1 Select, 0 = SD1, 1 = MS1 */
#define PBC_BCTRL3_CARD2_SEL 0x0800 /* Card2 Select, 0 = PCMCIA & SD2, 1 = MS2 */
#define PBC_BCTRL3_SYNTH_RST 0x1000 /* Audio Synthesizer Reset, 0 = reset asserted */
#define PBC_BCTRL3_VSIM_EN 0x2000 /* VSIM Regulator Enable, 1 = enabled */
#define PBC_BCTRL3_VESIM_EN 0x4000 /* VESIM Regulator Enable, 1 = enabled */
#define PBC_BCTRL3_SPI3_RESET 0x8000 /* CSPI3 Connector Reset, 0 = reset asserted */
/* PBC Board Control Register 4 bit definitions */
#define PBC_BCTRL4_CSI_MSB_EN 0x0001 /* CSI MSB Enable, 0 = CSI_Data[3:0] enabled */
#define PBC_BCTRL4_REGEN_SEL 0x0002 /* Regulator Enable Select, 0 = enabled */
#define PBC_BCTRL4_USER_OFF 0x0004 /* User Off Indication, 1 = user off confirmation */
#define PBC_BCTRL4_VIB_EN 0x0008 /* Vibrator Enable, 1 = enabled */
#define PBC_BCTRL4_PCMCIA_EN 0x0010 /* PCMCIA Enable, 0 = buffer enabled */
#define CKIH_27MHZ_BIT_SET (1 << 4)
#define PBC_INT_CS8900A 4
/*! @} */
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
#define MXC_MAX_EXP_IO_LINES 16
/*!
* @name Defines Base address and IRQ used for CS8900A Ethernet Controller on MXC Boards
*/
/*! @{*/
/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */
#define CS8900AIRQ EXPIO_INT_ENET_INT
/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */
#define CS8900A_BASE_ADDRESS (PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300)
/*! @} */
#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX31_PIN_GPIO1_3)
#define AHB_FREQ 133000000
#define IPG_FREQ 66500000
#define MXC_BD_LED1 (1 << 6)
#define MXC_BD_LED2 (1 << 7)
#define MXC_BD_LED_ON(led) \
__raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_SET)
#define MXC_BD_LED_OFF(led) \
__raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR)
#endif /* CONFIG_MACH_MX31ADS */
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

153
arch/arm/mach-mx3/board-mx3_3stack.h Normal file
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@@ -0,0 +1,153 @@
/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
#ifdef CONFIG_MACH_MX31_3DS
/*!
* @defgroup BRDCFG_MX31 Board Configuration Options
* @ingroup MSL_MX31
*/
/*!
* @file mach-mx3/board-mx3_3stack.h
*
* @brief This file contains all the board level configuration options.
*
* It currently hold the options defined for MX31 3STACK Platform.
*
* @ingroup BRDCFG_MX31
*/
/*
* Include Files
*/
#include <mach/mxc_uart.h>
/*!
* @name MXC UART EVB board level configurations
*/
/*! @{ */
/*!
* Specifies if the Irda transmit path is inverting
*/
#define MXC_IRDA_TX_INV 0
/*!
* Specifies if the Irda receive path is inverting
*/
#define MXC_IRDA_RX_INV 0
/* UART 1 configuration */
/*!
* This define specifies if the UART port is configured to be in DTE or
* DCE mode. There exists a define like this for each UART port. Valid
* values that can be used are \b MODE_DTE or \b MODE_DCE.
*/
#define UART1_MODE MODE_DCE
/*!
* This define specifies if the UART is to be used for IRDA. There exists a
* define like this for each UART port. Valid values that can be used are
* \b IRDA or \b NO_IRDA.
*/
#define UART1_IR NO_IRDA
/*!
* This define is used to enable or disable a particular UART port. If
* disabled, the UART will not be registered in the file system and the user
* will not be able to access it. There exists a define like this for each UART
* port. Specify a value of 1 to enable the UART and 0 to disable it.
*/
#define UART1_ENABLED 1
/*! @} */
/* UART 2 configuration */
#define UART2_MODE MODE_DCE
#define UART2_IR NO_IRDA
#define UART2_ENABLED 1
/* UART 3 configuration */
#define UART3_MODE MODE_DTE
#define UART3_IR NO_IRDA
#define UART3_ENABLED 1
/* UART 4 configuration */
#define UART4_MODE MODE_DTE
#define UART4_IR NO_IRDA
#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */
/* UART 5 configuration */
#define UART5_MODE MODE_DTE
#define UART5_IR NO_IRDA
#define UART5_ENABLED 0
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#define DEBUG_BASE_ADDRESS CS5_BASE_ADDR
/* LAN9217 ethernet base address */
#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS
/* External UART */
#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x8000)
#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000)
#define BOARD_IO_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
/* LED switchs */
#define LED_SWITCH_REG 0x00
/* buttons */
#define SWITCH_BUTTONS_REG 0x08
/* status, interrupt */
#define INTR_STATUS_REG 0x10
#define INTR_MASK_REG 0x38
#define INTR_RESET_REG 0x20
/* magic word for debug CPLD */
#define MAGIC_NUMBER1_REG 0x40
#define MAGIC_NUMBER2_REG 0x48
/* CPLD code version */
#define CPLD_CODE_VER_REG 0x50
/* magic word for debug CPLD */
#define MAGIC_NUMBER3_REG 0x58
/* module reset register*/
#define MODULE_RESET_REG 0x60
/* CPU ID and Personality ID */
#define MCU_BOARD_ID_REG 0x68
/* interrupts like external uart , external ethernet etc*/
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0)
#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1)
#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2)
#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3)
#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
/*! This is System IRQ used by LAN9217 */
#define LAN9217_IRQ EXPIO_INT_ENET
/*! LED definition*/
#define MXC_BD_LED1 (1)
#define MXC_BD_LED2 (1 << 1)
#define MXC_BD_LED3 (1 << 2)
#define MXC_BD_LED4 (1 << 3)
#define MXC_BD_LED5 (1 << 4)
#define MXC_BD_LED6 (1 << 5)
#define MXC_BD_LED7 (1 << 6)
#define MXC_BD_LED8 (1 << 7)
#define MXC_BD_LED_ON(led)
#define MXC_BD_LED_OFF(led)
extern unsigned int sdhc_get_card_det_status(struct device *dev);
extern int sdhc_init_card_det(int id);
extern int sdhc_write_protect(struct device *dev);
extern int __init mx3_3stack_init_mc13783(void);
#endif /* CONFIG_MACH_MX31_3DS */
#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */

1313
arch/arm/mach-mx3/clock.c
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71
arch/arm/mach-mx3/cpu.c Normal file
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@@ -0,0 +1,71 @@
/*
* Copyright (C) 2001 Deep Blue Solutions Ltd.
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*!
* @file mach-mx3/cpu.c
*
* @brief This file contains the CPU initialization code.
*
* @ingroup MSL_MX31
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <asm/hardware/cache-l2x0.h>
/*!
* CPU initialization. It is called by fixup_mxc_board()
*/
void __init mxc_cpu_init(void)
{
/* Setup Peripheral Port Remap register for AVIC */
asm("ldr r0, =0xC0000015 \n\
mcr p15, 0, r0, c15, c2, 4");
if (!system_rev) {
mxc_set_system_rev(0x31, CHIP_REV_2_0);
}
}
/*!
* Post CPU init code
*
* @return 0 always
*/
static int __init post_cpu_init(void)
{
volatile unsigned long aips_reg;
/*
* S/W workaround: Clear the off platform peripheral modules
* Supervisor Protect bit for SDMA to access them.
*/
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
return 0;
}
postcore_initcall(post_cpu_init);

162
arch/arm/mach-mx3/crm_regs.h
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@@ -1,5 +1,5 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
@@ -24,7 +24,7 @@
#define CKIH_CLK_FREQ_27MHZ 27000000
#define CKIL_CLK_FREQ 32768
#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
#define MXC_CCM_BASE ((char *)IO_ADDRESS(CCM_BASE_ADDR))
/* Register addresses */
#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
@@ -55,6 +55,7 @@
#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64)
/* Register bit definitions */
#define MXC_CCM_CCMR_VSTBY (1 << 28)
#define MXC_CCM_CCMR_WBEN (1 << 27)
#define MXC_CCM_CCMR_CSCS (1 << 25)
#define MXC_CCM_CCMR_PERCS (1 << 24)
@@ -66,6 +67,7 @@
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
#define MXC_CCM_CCMR_FIRS_OFFSET 11
#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
#define MXC_CCM_CCMR_WAMO (1 << 10)
#define MXC_CCM_CCMR_UPE (1 << 9)
#define MXC_CCM_CCMR_SPE (1 << 8)
#define MXC_CCM_CCMR_MDS (1 << 7)
@@ -91,6 +93,47 @@
#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11)
#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11)
#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11)
#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11)
#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11)
#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11)
#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11)
#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11)
#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6)
#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6)
#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6)
#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6)
#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3)
#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3)
#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3)
#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3)
#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3)
#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3)
#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3)
#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3)
#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8)
#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8)
#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8)
#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8)
#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8)
#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8)
#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8)
#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8)
#define MXC_CCM_PDR0_MCU_DIV_1 0x0
#define MXC_CCM_PDR0_MCU_DIV_2 0x1
#define MXC_CCM_PDR0_MCU_DIV_3 0x2
#define MXC_CCM_PDR0_MCU_DIV_4 0x3
#define MXC_CCM_PDR0_MCU_DIV_5 0x4
#define MXC_CCM_PDR0_MCU_DIV_6 0x5
#define MXC_CCM_PDR0_MCU_DIV_7 0x6
#define MXC_CCM_PDR0_MCU_DIV_8 0x7
#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
@@ -109,7 +152,120 @@
#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
/* Bit definitions for RCSR */
#define MXC_CCM_RCSR_NF16B 0x80000000
#define MXC_CCM_RCSR_NF16B (0x1 << 31)
#define MXC_CCM_RCSR_NFMS (0x1 << 30)
/* Bit definitions for both MCU, USB and SR PLL control registers */
#define MXC_CCM_PCTL_BRM 0x80000000
#define MXC_CCM_PCTL_PD_OFFSET 26
#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
#define MXC_CCM_PCTL_MFD_OFFSET 16
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
#define MXC_CCM_PCTL_MFI_OFFSET 10
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
#define MXC_CCM_PCTL_MFN_OFFSET 0
#define MXC_CCM_PCTL_MFN_MASK 0x3FF
#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0
#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0)
#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2
#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2)
#define MXC_CCM_CGR0_GPT_OFFSET 4
#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4)
#define MXC_CCM_CGR0_EPIT1_OFFSET 6
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6)
#define MXC_CCM_CGR0_EPIT2_OFFSET 8
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8)
#define MXC_CCM_CGR0_IIM_OFFSET 10
#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10)
#define MXC_CCM_CGR0_ATA_OFFSET 12
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12)
#define MXC_CCM_CGR0_SDMA_OFFSET 14
#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14)
#define MXC_CCM_CGR0_CSPI3_OFFSET 16
#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16)
#define MXC_CCM_CGR0_RNG_OFFSET 18
#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18)
#define MXC_CCM_CGR0_UART1_OFFSET 20
#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20)
#define MXC_CCM_CGR0_UART2_OFFSET 22
#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22)
#define MXC_CCM_CGR0_SSI1_OFFSET 24
#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24)
#define MXC_CCM_CGR0_I2C1_OFFSET 26
#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26)
#define MXC_CCM_CGR0_I2C2_OFFSET 28
#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28)
#define MXC_CCM_CGR0_I2C3_OFFSET 30
#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30)
#define MXC_CCM_CGR1_HANTRO_OFFSET 0
#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0)
#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2
#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2)
#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4
#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4)
#define MXC_CCM_CGR1_CSI_OFFSET 6
#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6)
#define MXC_CCM_CGR1_RTC_OFFSET 8
#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8)
#define MXC_CCM_CGR1_WDOG_OFFSET 10
#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10)
#define MXC_CCM_CGR1_PWM_OFFSET 12
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12)
#define MXC_CCM_CGR1_SIM_OFFSET 14
#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14)
#define MXC_CCM_CGR1_ECT_OFFSET 16
#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16)
#define MXC_CCM_CGR1_USBOTG_OFFSET 18
#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18)
#define MXC_CCM_CGR1_KPP_OFFSET 20
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
#define MXC_CCM_CGR1_IPU_OFFSET 22
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22)
#define MXC_CCM_CGR1_UART3_OFFSET 24
#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24)
#define MXC_CCM_CGR1_UART4_OFFSET 26
#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26)
#define MXC_CCM_CGR1_UART5_OFFSET 28
#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28)
#define MXC_CCM_CGR1_OWIRE_OFFSET 30
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30)
#define MXC_CCM_CGR2_SSI2_OFFSET 0
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0)
#define MXC_CCM_CGR2_CSPI1_OFFSET 2
#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2)
#define MXC_CCM_CGR2_CSPI2_OFFSET 4
#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4)
#define MXC_CCM_CGR2_GACC_OFFSET 6
#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6)
#define MXC_CCM_CGR2_EMI_OFFSET 8
#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8)
#define MXC_CCM_CGR2_RTIC_OFFSET 10
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10)
#define MXC_CCM_CGR2_FIRI_OFFSET 12
#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12)
#define MXC_CCM_CGR2_IPMUX1_OFFSET 14
#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14)
#define MXC_CCM_CGR2_IPMUX2_OFFSET 16
#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16)
/* These new CGR2 bits are added in MX32 */
#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18
#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18)
#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20
#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20)
#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22
#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22)
#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24
#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24)
#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25
#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25)
#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26
#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26)
#define MXC_CCM_CGR2_APMENA_OFFSET 30
#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30)
/*
* LTR0 register offsets

1233
arch/arm/mach-mx3/devices.c
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arch/arm/mach-mx3/dma.c Normal file
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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/device.h>
#include <asm/dma.h>
#include <mach/hardware.h>
#include "serial.h"
#define MXC_MMC_BUFFER_ACCESS 0x38
#define MXC_SSI_TX0_REG 0x0
#define MXC_SSI_TX1_REG 0x4
#define MXC_SSI_RX0_REG 0x8
#define MXC_SSI_RX1_REG 0xC
#define MXC_FIRI_TXFIFO 0x14
#define MXC_SDHC_MMC_WML 16
#define MXC_SDHC_SD_WML 64
#define MXC_SSI_TXFIFO_WML 0x4
#define MXC_SSI_RXFIFO_WML 0x6
#define MXC_FIRI_WML 16
#ifdef CONFIG_SDMA_IRAM
#define trans_type int_2_per
#else
#define trans_type emi_2_per
#endif
typedef struct mxc_sdma_info_entry_s {
mxc_dma_device_t device;
mxc_sdma_channel_params_t *chnl_info;
} mxc_sdma_info_entry_t;
static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = {
.chnl_params = {
.watermark_level = UART1_UFCR_RXTL,
.per_address = UART1_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART1_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART1_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = {
.chnl_params = {
.watermark_level = UART1_UFCR_TXTL,
.per_address = UART1_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART1_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART1_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = {
.chnl_params = {
.watermark_level = UART2_UFCR_RXTL,
.per_address = UART2_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART2_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART2_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = {
.chnl_params = {
.watermark_level = UART2_UFCR_TXTL,
.per_address = UART2_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART2_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART2_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = {
.chnl_params = {
.watermark_level = UART3_UFCR_RXTL,
.per_address = UART3_BASE_ADDR,
.peripheral_type = UART_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART3_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART3_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = {
.chnl_params = {
.watermark_level = UART3_UFCR_TXTL,
.per_address = UART3_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART3_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART3_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = {
.chnl_params = {
.watermark_level = UART4_UFCR_RXTL,
.per_address = UART4_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART4_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART4_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = {
.chnl_params = {
.watermark_level = UART4_UFCR_TXTL,
.per_address = UART4_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART4_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART4_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = {
.chnl_params = {
.watermark_level = UART5_UFCR_RXTL,
.per_address = UART5_BASE_ADDR,
.peripheral_type = UART,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_UART5_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART5_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = {
.chnl_params = {
.watermark_level = UART5_UFCR_TXTL,
.per_address = UART5_BASE_ADDR + MXC_UARTUTXD,
.peripheral_type = UART,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_UART5_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_UART5_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = {
.chnl_params = {
.watermark_level = MXC_SDHC_MMC_WML,
.per_address =
MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS,
.peripheral_type = MMC,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SDHC1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MMC1,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = {
.chnl_params = {
.watermark_level = MXC_SDHC_SD_WML,
.per_address =
MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS,
.peripheral_type = MMC,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SDHC1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MMC1,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = {
.chnl_params = {
.watermark_level = MXC_SDHC_MMC_WML,
.per_address =
MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS,
.peripheral_type = MMC,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SDHC2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MMC2,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = {
.chnl_params = {
.watermark_level = MXC_SDHC_SD_WML,
.per_address =
MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS,
.peripheral_type = MMC,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SDHC2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MMC2,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX2,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX2,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX2,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX2,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI1_RX2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI1_TX2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI1_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = trans_type,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = trans_type,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG,
.peripheral_type = SSI_SP,
.transfer_type = trans_type,
.event_id = DMA_REQ_SSI2_TX1,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX2,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = trans_type,
.event_id = DMA_REQ_SSI2_TX2,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX2,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = trans_type,
.event_id = DMA_REQ_SSI2_TX2,
.bd_number = 32,
.word_size = TRANSFER_16BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_RXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_SSI2_RX2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_RX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = {
.chnl_params = {
.watermark_level = MXC_SSI_TXFIFO_WML,
.per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG,
.peripheral_type = SSI_SP,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_SSI2_TX2,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_SSI2_TX,
.chnl_priority = 2,
};
static mxc_sdma_channel_params_t mxc_sdma_fir_rx_params = {
.chnl_params = {
.watermark_level = MXC_FIRI_WML,
.per_address = FIRI_BASE_ADDR,
.peripheral_type = FIRI,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_FIRI_RX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_FIR_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_fir_tx_params = {
.chnl_params = {
.watermark_level = MXC_FIRI_WML,
.per_address = FIRI_BASE_ADDR + MXC_FIRI_TXFIFO,
.peripheral_type = FIRI,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_FIRI_TX,
.bd_number = 32,
.word_size = TRANSFER_8BIT,
},
.channel_num = MXC_DMA_CHANNEL_FIR_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_memory_params = {
.chnl_params = {
.peripheral_type = MEMORY,
.transfer_type = emi_2_emi,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_MEMORY,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_fifo_memory_params = {
.chnl_params = {
.peripheral_type = FIFO_MEMORY,
.per_address = MXC_FIFO_MEM_DEST_FIXED,
.transfer_type = emi_2_emi,
.bd_number = 32,
.word_size = TRANSFER_32BIT,
.event_id = 0,
},
.channel_num = MXC_DMA_CHANNEL_FIFO_MEMORY,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = {
.chnl_params = {
.watermark_level = MXC_IDE_DMA_WATERMARK,
.per_address = ATA_DMA_BASE_ADDR,
.peripheral_type = ATA,
.transfer_type = per_2_emi,
.event_id = DMA_REQ_ATA_TX_END,
.event_id2 = DMA_REQ_ATA_RX,
.bd_number = MXC_IDE_DMA_BD_NR,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_ATA_RX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = {
.chnl_params = {
.watermark_level = MXC_IDE_DMA_WATERMARK,
.per_address = ATA_DMA_BASE_ADDR + 0x18,
.peripheral_type = ATA,
.transfer_type = emi_2_per,
.event_id = DMA_REQ_ATA_TX_END,
.event_id2 = DMA_REQ_ATA_TX,
.bd_number = MXC_IDE_DMA_BD_NR,
.word_size = TRANSFER_32BIT,
},
.channel_num = MXC_DMA_CHANNEL_ATA_TX,
.chnl_priority = MXC_SDMA_DEFAULT_PRIORITY,
};
static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = {
{MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params},
{MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params},
{MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params},
{MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params},
{MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params},
{MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params},
{MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params},
{MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params},
{MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params},
{MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params},
{MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params},
{MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params},
{MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params},
{MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params},
{MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params},
{MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params},
{MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params},
{MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params},
{MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params},
{MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params},
{MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params},
{MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params},
{MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params},
{MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params},
{MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params},
{MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params},
{MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params},
{MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params},
{MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params},
{MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params},
{MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params},
{MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params},
{MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params},
{MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params},
{MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params},
{MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params},
{MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params},
{MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params},
{MXC_DMA_FIR_RX, &mxc_sdma_fir_rx_params},
{MXC_DMA_FIR_TX, &mxc_sdma_fir_tx_params},
{MXC_DMA_MEMORY, &mxc_sdma_memory_params},
{MXC_DMA_FIFO_MEMORY, &mxc_sdma_fifo_memory_params},
{MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params},
{MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params},
};
static int mxc_sdma_info_entrys =
sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]);
/*!
* This functions Returns the SDMA paramaters associated for a module
*
* @param channel_id the ID of the module requesting DMA
* @return returns the sdma parameters structure for the device
*/
mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t
channel_id)
{
mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info;
int i;
for (i = 0; i < mxc_sdma_info_entrys; i++, p++) {
if (p->device == channel_id) {
return p->chnl_info;
}
}
return NULL;
}
/*!
* This functions marks the SDMA channels that are statically allocated
*
* @param chnl the channel array used to store channel information
*/
void mxc_get_static_channels(mxc_dma_channel_t * chnl)
{
#ifdef CONFIG_SDMA_IRAM
int i;
for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++)
chnl[i].dynamic = 0;
#endif /*CONFIG_SDMA_IRAM */
}
EXPORT_SYMBOL(mxc_sdma_get_channel_params);
EXPORT_SYMBOL(mxc_get_static_channels);

103
arch/arm/mach-mx3/dptc.c Normal file
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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file dptc.c
*
* @brief DPTC table for the Freescale Semiconductor MXC DPTC module.
*
* @ingroup PM
*/
#include <mach/hardware.h>
#include <mach/mxc_dptc.h>
struct dptc_wp dptc_wp_allfreq_26ckih[DPTC_WP_SUPPORTED] = {
/* 532MHz */
/* dcvr0 dcvr1 dcvr2 dcvr3 voltage */
/* wp0 */
{0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000, 1625},
{0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1600},
{0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1575},
{0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4, 1550},
{0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8, 1525},
/* wp5 */
{0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0, 1500},
{0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc, 1475},
{0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8, 1450},
{0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8, 1425},
{0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8, 1400},
/* wp10 */
{0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8, 1375},
{0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08, 1350},
{0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c, 1350},
{0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c, 1350},
{0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44, 1350},
/* wp15 */
{0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58, 1350},
{0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70, 1350},
};
struct dptc_wp dptc_wp_allfreq_26ckih_TO_2_0[DPTC_WP_SUPPORTED] = {
/* Mx31 TO 2.0 Offset table */
/* 532MHz */
/* dcvr0 dcvr1 dcvr2 dcvr3 voltage */
/* wp0 */
{0xffc00000, 0x9E265978, 0xffc00000, 0xE4371D9C, 1625},
{0xffc00000, 0x9E665978, 0xffc00000, 0xE4772D9C, 1600},
{0xffc00000, 0x9EA65978, 0xffc00000, 0xE4772DA0, 1575},
{0xffc00000, 0x9EE66978, 0xffc00000, 0xE4B73DA0, 1550},
{0xffc00000, 0x9F26697C, 0xffc00000, 0xE4F73DA0, 1525},
/* wp5 */
{0xffc00000, 0x9F66797C, 0xffc00000, 0xE5774DA4, 1500},
{0xffc00000, 0x9FE6797C, 0xffc00000, 0xE5F75DA4, 1475},
{0xffc00000, 0xA026897C, 0xffc00000, 0xE6776DA4, 1450},
{0xffc00000, 0xA0A6897C, 0xffc00000, 0xE6F77DA8, 1425},
{0xffc00000, 0xA0E69980, 0xffc00000, 0xE7B78DAC, 1400},
/* wp10 */
{0xffc00000, 0xA1669980, 0xffc00000, 0xE8379DAC, 1375},
{0xffc00000, 0xA1A6A980, 0xffc00000, 0xE8F7ADB0, 1350},
{0xffc00000, 0xA226B984, 0xffc00000, 0xE9F7CDB0, 1325},
{0xffc00000, 0xA2A6C984, 0xffc00000, 0xEAB7DDB4, 1300},
{0xffc00000, 0xA326C988, 0xffc00000, 0xEBB7FDB8, 1275},
/* wp15 */
{0xffc00000, 0xA3A6D988, 0xffc00000, 0xECB80DBC, 1250},
{0xffc00000, 0xA426E988, 0xffc00000, 0xEDB82DC0, 1225},
};
struct dptc_wp dptc_wp_allfreq_27ckih_TO_2_0[DPTC_WP_SUPPORTED] = {
/* Mx31 TO 2.0 Offset table */
/* 532MHz */
/* dcvr0 dcvr1 dcvr2 dcvr3 voltage */
/* wp0 */
{0xffc00000, 0x9864E920, 0xffc00000, 0xDBB50D1C, 1625},
{0xffc00000, 0x98A4E920, 0xffc00000, 0xDBF51D1C, 1600},
{0xffc00000, 0x98E4E920, 0xffc00000, 0xDBF51D20, 1575},
{0xffc00000, 0x9924F920, 0xffc00000, 0xDC352D20, 1550},
{0xffc00000, 0x9924F924, 0xffc00000, 0xDC752D20, 1525},
/* wp5 */
{0xffc00000, 0x99650924, 0xffc00000, 0xDCF53D24, 1500},
{0xffc00000, 0x99E50924, 0xffc00000, 0xDD754D24, 1475},
{0xffc00000, 0x9A251924, 0xffc00000, 0xDDF55D24, 1450},
{0xffc00000, 0x9AA51924, 0xffc00000, 0xDE756D28, 1425},
{0xffc00000, 0x9AE52928, 0xffc00000, 0xDF357D2C, 1400},
/* wp10 */
{0xffc00000, 0x9B652928, 0xffc00000, 0xDFB58D2C, 1375},
{0xffc00000, 0x9BA53928, 0xffc00000, 0xE0759D30, 1350},
{0xffc00000, 0x9C254928, 0xffc00000, 0xE135BD30, 1325},
{0xffc00000, 0x9CA55928, 0xffc00000, 0xE1F5CD34, 1300},
{0xffc00000, 0x9D25592C, 0xffc00000, 0xE2F5ED38, 1275},
/* wp15 */
{0xffc00000, 0x9DA5692C, 0xffc00000, 0xE3F5FD38, 1250},
{0xffc00000, 0x9E25792C, 0xffc00000, 0xE4F61D3C, 1225},
};

535
arch/arm/mach-mx3/dvfs_v2.c Normal file
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/*
* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file dvfs_v2.c
*
* @brief A simplied driver for the Freescale Semiconductor MXC DVFS module.
*
* Upon initialization, the DVFS driver initializes the DVFS hardware
* sets up driver nodes attaches to the DVFS interrupt and initializes internal
* data structures. When the DVFS interrupt occurs the driver checks the cause
* of the interrupt (lower frequency, increase frequency or emergency) and changes
* the CPU voltage according to translation table that is loaded into the driver.
*
* @ingroup PM
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/pmic_external.h>
#include <mach/pmic_power.h>
#include "iomux.h"
#include "crm_regs.h"
static int dvfs_is_active;
/* Used for tracking the number of interrupts */
static u32 dvfs_nr_up[4];
static u32 dvfs_nr_dn[4];
/*
* Clock structures
*/
static struct clk *cpu_clk;
static struct clk *ahb_clk;
enum {
FSVAI_FREQ_NOCHANGE = 0x0,
FSVAI_FREQ_INCREASE,
FSVAI_FREQ_DECREASE,
FSVAI_FREQ_EMERG,
};
/*
* Frequency increase threshold. Increase frequency change request
* will be sent if DVFS counter value will be more than this value.
*/
#define DVFS_UPTHR (30 << MXC_CCM_LTR0_UPTHR_OFFSET)
/*
* Frequency decrease threshold. Decrease frequency change request
* will be sent if DVFS counter value will be less than this value.
*/
#define DVFS_DNTHR (18 << MXC_CCM_LTR0_DNTHR_OFFSET)
/*
* With the ARM clocked at 532, this setting yields a DIV_3_CLK of 2.03 kHz.
*/
#define DVFS_DIV3CK (3 << MXC_CCM_LTR0_DIV3CK_OFFSET)
/*
* DNCNT defines the amount of times the down threshold should be exceeded
* before DVFS will trigger frequency decrease request.
*/
#define DVFS_DNCNT (0x33 << MXC_CCM_LTR1_DNCNT_OFFSET)
/*
* UPCNT defines the amount of times the up threshold should be exceeded
* before DVFS will trigger frequency increase request.
*/
#define DVFS_UPCNT (0x33 << MXC_CCM_LTR1_UPCNT_OFFSET)
/*
* Panic threshold. Panic frequency change request
* will be sent if DVFS counter value will be more than this value.
*/
#define DVFS_PNCTHR (63 << MXC_CCM_LTR1_PNCTHR_OFFSET)
/*
* Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add
*/
#define DVFS_LTBRSR (1 << MXC_CCM_LTR1_LTBRSR_OFFSET)
/* EMAC defines how many samples are included in EMA calculation */
#define DVFS_EMAC (0x20 << MXC_CCM_LTR2_EMAC_OFFSET)
const static u8 ltr_gp_weight[] = {
0, /* 0 */
0,
0,
0,
0,
0, /* 5 */
0,
0,
0,
0,
0, /* 10 */
0,
7,
7,
7,
7, /* 15 */
};
DEFINE_SPINLOCK(mxc_dvfs_lock);
/*!
* This function sets the weight of general purpose signals
* @param gp_id number of general purpose bit
* @param weight the weight of the general purpose bit
*/
static void set_gp_weight(int gp_id, u8 weight)
{
u32 reg;
if (gp_id < 9) {
reg = __raw_readl(MXC_CCM_LTR3);
reg = (reg & ~(MXC_CCM_LTR3_WSW_MASK(gp_id))) |
(weight << MXC_CCM_LTR3_WSW_OFFSET(gp_id));
__raw_writel(reg, MXC_CCM_LTR3);
} else if (gp_id < 16) {
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_WSW_MASK(gp_id))) |
(weight << MXC_CCM_LTR2_WSW_OFFSET(gp_id));
__raw_writel(reg, MXC_CCM_LTR2);
}
}
static int start_dvfs(void)
{
u32 reg;
unsigned long flags;
if (dvfs_is_active) {
return 0;
}
spin_lock_irqsave(&mxc_dvfs_lock, flags);
reg = __raw_readl(MXC_CCM_PMCR0);
/* enable dvfs and interrupt */
reg = (reg & ~MXC_CCM_PMCR0_FSVAIM) | MXC_CCM_PMCR0_DVFEN;
__raw_writel(reg, MXC_CCM_PMCR0);
dvfs_is_active = 1;
spin_unlock_irqrestore(&mxc_dvfs_lock, flags);
pr_info("DVFS is started\n");
return 0;
}
#define MXC_CCM_LTR0_CONFIG_MASK (MXC_CCM_LTR0_UPTHR_MASK | \
MXC_CCM_LTR0_DNTHR_MASK | \
MXC_CCM_LTR0_DIV3CK_MASK)
#define MXC_CCM_LTR0_CONFIG_VAL (DVFS_UPTHR | DVFS_DNTHR | DVFS_DIV3CK)
#define MXC_CCM_LTR1_CONFIG_MASK (MXC_CCM_LTR1_UPCNT_MASK | \
MXC_CCM_LTR1_DNCNT_MASK | \
MXC_CCM_LTR1_PNCTHR_MASK | \
MXC_CCM_LTR1_LTBRSR_MASK)
#define MXC_CCM_LTR1_CONFIG_VAL (DVFS_UPCNT | DVFS_DNCNT | \
DVFS_PNCTHR | DVFS_LTBRSR)
/*!
* This function is called for module initialization.
* It sets up the DVFS hardware.
* It sets default values for DVFS thresholds and counters. The default
* values was chosen from a set of different reasonable values. They was tested
* and the default values in the driver gave the best results.
* More work should be done to find optimal values.
*
* @return 0 if successful; non-zero otherwise.
*
*/
static int init_dvfs_controller(void)
{
u32 i, reg;
/* Configure 2 MC13783 DVFS pins */
mxc_request_iomux(MX31_PIN_DVFS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE);
mxc_request_iomux(MX31_PIN_DVFS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE);
/* Configure MC13783 voltage ready input pin */
mxc_request_iomux(MX31_PIN_GPIO1_5, OUTPUTCONFIG_GPIO,
INPUTCONFIG_FUNC);
/* setup LTR0 */
reg = __raw_readl(MXC_CCM_LTR0);
reg = (reg & ~(MXC_CCM_LTR0_CONFIG_MASK)) | MXC_CCM_LTR0_CONFIG_VAL;
__raw_writel(reg, MXC_CCM_LTR0);
/* set up LTR1 */
reg = __raw_readl(MXC_CCM_LTR1);
reg = (reg & ~(MXC_CCM_LTR1_CONFIG_MASK)) | MXC_CCM_LTR1_CONFIG_VAL;
__raw_writel(reg, MXC_CCM_LTR1);
/* setup LTR2 */
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC;
__raw_writel(reg, MXC_CCM_LTR2);
/* Set general purpose weights to 0 */
for (i = 0; i < 16; i++) {
set_gp_weight(i, ltr_gp_weight[i]);
}
/* ARM interrupt, mask load buf full interrupt */
reg = __raw_readl(MXC_CCM_PMCR0);
reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI;
__raw_writel(reg, MXC_CCM_PMCR0);
/* configuring EMI Handshake and PLL relock disable */
reg = __raw_readl(MXC_CCM_PMCR1);
reg |= MXC_CCM_PMCR1_PLLRDIS;
reg |= MXC_CCM_PMCR1_EMIRQ_EN;
__raw_writel(reg, MXC_CCM_PMCR1);
return 0;
}
static irqreturn_t dvfs_irq(int irq, void *dev_id)
{
u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >>
MXC_CCM_PMCR0_FSVAI_OFFSET;
u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >>
MXC_CCM_PMCR0_DVSUP_OFFSET;
u32 curr_ahb, curr_cpu, rate;
/* Should not be here if FSVAIM is set */
BUG_ON(pmcr0 & MXC_CCM_PMCR0_FSVAIM);
if (fsvai == FSVAI_FREQ_NOCHANGE) {
/* Do nothing. Freq change is not required */
printk(KERN_WARNING "fsvai should not be 0\n");
return IRQ_HANDLED;
}
if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) {
/* Do nothing. DVFS didn't finish previous flow update */
return IRQ_HANDLED;
}
if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) ||
((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) ||
(fsvai == FSVAI_FREQ_EMERG)))) {
/* Interrupt should be disabled in these cases according to
* the spec since DVFS is already at lowest (highest) state */
printk(KERN_WARNING "Something is wrong?\n");
return IRQ_HANDLED;
}
curr_ahb = clk_get_rate(ahb_clk);
if (fsvai == FSVAI_FREQ_DECREASE) {
curr_cpu = clk_get_rate(cpu_clk);
rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb;
if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) &&
((curr_cpu / curr_ahb) == 4)) {
rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb;
}
dvfs_nr_dn[dvsup]++;
} else {
rate = 4 * curr_ahb;
dvfs_nr_up[dvsup]++;
}
clk_set_rate(cpu_clk, rate);
return IRQ_HANDLED;
}
/*!
* This function disables the DVFS module.
*/
static void stop_dvfs(void)
{
u32 pmcr0, dvsup;
unsigned long flags;
u32 curr_ahb = clk_get_rate(ahb_clk);
if (dvfs_is_active) {
spin_lock_irqsave(&mxc_dvfs_lock, flags);
pmcr0 = __raw_readl(MXC_CCM_PMCR0);
dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >>
MXC_CCM_PMCR0_DVSUP_OFFSET;
if (dvsup != DVSUP_TURBO) {
/* Use sw delay to insure volt/freq change */
clk_set_rate(cpu_clk, (4 * curr_ahb));
udelay(200);
}
pmcr0 = __raw_readl(MXC_CCM_PMCR0);
/* disable dvfs and its interrupt */
pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVFEN) | MXC_CCM_PMCR0_FSVAIM;
__raw_writel(pmcr0, MXC_CCM_PMCR0);
dvfs_is_active = 0;
spin_unlock_irqrestore(&mxc_dvfs_lock, flags);
}
pr_info("DVFS is stopped\n");
}
void pmic_voltage_init(void)
{
t_regulator_voltage volt;
/* Enable 4 mc13783 output voltages */
pmic_write_reg(REG_ARBITRATION_SWITCHERS, (1 << 5), (1 << 5));
/* Set mc13783 DVS speed 25mV each 4us */
pmic_write_reg(REG_SWITCHERS_4, (0 << 6), (3 << 6));
if (cpu_is_mx31())
volt.sw1a = SW1A_1_625V;
else
volt.sw1a = SW1A_1_425V;
pmic_power_regulator_set_voltage(SW_SW1A, volt);
volt.sw1a = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1A, volt);
if (cpu_is_mx32()) {
volt.sw1a = SW1A_0_975V;
pmic_power_switcher_set_stby(SW_SW1A, volt);
}
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1B, volt);
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_stby(SW_SW1B, volt);
}
static ssize_t dvfs_enable_store(struct sys_device *dev, struct sysdev_attribute *attr,
const char *buf, size_t size)
{
if (strstr(buf, "1") != NULL) {
if (start_dvfs() != 0) {
printk(KERN_ERR "Failed to start DVFS\n");
}
} else if (strstr(buf, "0") != NULL) {
stop_dvfs();
}
return size;
}
static ssize_t dvfs_status_show(struct sys_device *dev, struct sysdev_attribute *attr,
char *buf)
{
int size = 0;
if (dvfs_is_active) {
size = sprintf(buf, "DVFS is enabled\n");
} else {
size = sprintf(buf, "DVFS is disabled\n");
}
size +=
sprintf((buf + size), "UP:\t%d\t%d\t%d\t%d\n", dvfs_nr_up[0],
dvfs_nr_up[1], dvfs_nr_up[2], dvfs_nr_up[3]);
size +=
sprintf((buf + size), "DOWN:\t%d\t%d\t%d\t%d\n\n", dvfs_nr_dn[0],
dvfs_nr_dn[1], dvfs_nr_dn[2], dvfs_nr_dn[3]);
return size;
}
static ssize_t dvfs_status_store(struct sys_device *dev, struct sysdev_attribute *attr,
const char *buf, size_t size)
{
if (strstr(buf, "reset") != NULL) {
int i;
for (i = 0; i < 4; i++) {
dvfs_nr_up[i] = 0;
dvfs_nr_dn[i] = 0;
}
}
return size;
}
static ssize_t dvfs_debug_show(struct sys_device *dev, struct sysdev_attribute *attr,
char *buf)
{
int size = 0;
u32 curr_ahb, curr_cpu;
curr_ahb = clk_get_rate(ahb_clk);
curr_cpu = clk_get_rate(cpu_clk);
pr_debug("ahb %d, cpu %d\n", curr_ahb, curr_cpu);
return size;
}
static ssize_t dvfs_debug_store(struct sys_device *dev, struct sysdev_attribute *attr,
const char *buf, size_t size)
{
u32 curr_ahb, curr_cpu, rate = 0;
curr_ahb = clk_get_rate(ahb_clk);
curr_cpu = clk_get_rate(cpu_clk);
if (strstr(buf, "inc") != NULL) {
rate = 4 * curr_ahb;
pr_debug("inc to %d\n", rate);
}
if (strstr(buf, "dec") != NULL) {
rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb;
if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) &&
((curr_cpu / curr_ahb) == 4))
rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb;
pr_debug("dec to %d\n", rate);
}
clk_set_rate(cpu_clk, rate);
return size;
}
static SYSDEV_ATTR(enable, 0200, NULL, dvfs_enable_store);
static SYSDEV_ATTR(status, 0644, dvfs_status_show, dvfs_status_store);
static SYSDEV_ATTR(debug, 0644, dvfs_debug_show, dvfs_debug_store);
static struct sysdev_class dvfs_sysclass = {
.name = "dvfs",
};
static struct sys_device dvfs_device = {
.id = 0,
.cls = &dvfs_sysclass,
};
static int dvfs_sysdev_ctrl_init(void)
{
int err;
err = sysdev_class_register(&dvfs_sysclass);
if (!err)
err = sysdev_register(&dvfs_device);
if (!err) {
err = sysdev_create_file(&dvfs_device, &attr_enable);
err = sysdev_create_file(&dvfs_device, &attr_status);
err = sysdev_create_file(&dvfs_device, &attr_debug);
}
return err;
}
static void dvfs_sysdev_ctrl_exit(void)
{
sysdev_remove_file(&dvfs_device, &attr_enable);
sysdev_remove_file(&dvfs_device, &attr_status);
sysdev_unregister(&dvfs_device);
sysdev_class_unregister(&dvfs_sysclass);
}
static int __init dvfs_init(void)
{
int err = 0;
pmic_voltage_init();
cpu_clk = clk_get(NULL, "cpu_clk");
ahb_clk = clk_get(NULL, "ahb_clk");
err = init_dvfs_controller();
if (err) {
printk(KERN_ERR "DVFS: Unable to initialize DVFS");
return err;
}
/* request the DVFS interrupt */
err = request_irq(MXC_INT_CCM_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL);
if (err) {
printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt");
}
err = dvfs_sysdev_ctrl_init();
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for dvfs");
return err;
}
return err;
}
static void __exit dvfs_cleanup(void)
{
stop_dvfs();
/* release the DVFS interrupt */
free_irq(MXC_INT_CCM_DVFS, NULL);
dvfs_sysdev_ctrl_exit();
clk_put(cpu_clk);
clk_put(ahb_clk);
}
module_init(dvfs_init);
module_exit(dvfs_cleanup);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("DVFS driver");
MODULE_LICENSE("GPL");

327
arch/arm/mach-mx3/iomux.c
View File

@@ -1,181 +1,260 @@
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @defgroup GPIO_MX31 Board GPIO and Muxing Setup
* @ingroup MSL_MX31
*/
/*!
* @file mach-mx3/iomux.c
*
* @brief I/O Muxing control functions
*
* @ingroup GPIO_MX31
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/iomux-mx3.h>
#include "iomux.h"
/*
/*!
* 4 control fields per MUX register
*/
#define MUX_CTL_FIELDS 4
/*!
* 3 control fields per PAD register
*/
#define PAD_CTL_FIELDS 3
/*!
* Maximum number of MUX pins
* Number of pins = (highest iomux reg - lowest iomux reg + 1) * (4 pins/reg)
*/
#define MUX_PIN_NUM_MAX \
(((u32 *)IOMUXSW_MUX_END - (u32 *)IOMUXSW_MUX_CTL + 1) * MUX_CTL_FIELDS)
/*!
* Number of pad controls =
* (highest pad ctl reg - lowest pad ctl reg + 1) * (3 pins/reg)
*/
#define PAD_CTL_NUM_MAX \
(((u32 *)IOMUXSW_PAD_END - (u32 *)IOMUXSW_PAD_CTL + 1) * PAD_CTL_FIELDS)
#define PIN_TO_IOMUX_INDEX(pin) ((pin >> MUX_I) & ((1 << (MUX_F - MUX_I)) - 1))
#define PIN_TO_IOMUX_FIELD(pin) ((pin >> MUX_F) & ((1 << (PAD_I - MUX_F)) - 1))
/*!
* 8 bits for each MUX control field
*/
#define MUX_CTL_BIT_LEN 8
/*!
* 10 bits for each PAD control field
*/
#define MUX_PAD_BIT_LEN 10
/*!
* IOMUX register (base) addresses
*/
#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
#define IOMUXGPR (IOMUX_BASE + 0x008)
#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
#define IOMUXGPR (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x008) /*!< General purpose */
#define IOMUXSW_MUX_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x00C) /*!< MUX control */
#define IOMUXSW_MUX_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x150) /*!< last MUX control register */
#define IOMUXSW_PAD_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x154) /*!< Pad control */
#define IOMUXSW_PAD_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x308) /*!< last Pad control register */
#define IOMUXINT_OBS1 (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x000) /*!< Observe interrupts 1 */
#define IOMUXINT_OBS2 (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004) /*!< Observe interrupts 2 */
/* len - mask bit length; fld - mask bit field. Example, to have the mask:
* 0xFF000000, use GET_FIELD_MASK(8, 3). Translate in plain language:
* "set the 3rd (0-based) 8-bit-long field to all 1's */
#define GET_FIELD_MASK(len, fld) (((1 << len) - 1) << (len * fld))
static DEFINE_SPINLOCK(gpio_mux_lock);
static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX];
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/*
* set the mode for a IOMUX pin.
/*!
* This function is used to configure a pin through the IOMUX module.
* FIXED ME: for backward compatible. Will be static function!
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_iomux_mode(unsigned int pin_mode)
int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in)
{
u32 field, l, mode, ret = 0;
void __iomem *reg;
u32 l, ret = 0;
u32 mux_index = PIN_TO_IOMUX_INDEX(pin);
u32 mux_field = PIN_TO_IOMUX_FIELD(pin);
u32 mux_mask = GET_FIELD_MASK(MUX_CTL_BIT_LEN, mux_field);
u8 *rp;
reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
field = pin_mode & 0x3;
mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
BUG_ON((mux_index > (MUX_PIN_NUM_MAX / MUX_CTL_FIELDS - 1)) ||
(mux_field >= MUX_CTL_FIELDS));
reg = IOMUXSW_MUX_CTL + (mux_index * 4);
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0xff << (field * 8));
l |= mode << (field * 8);
l = (l & (~mux_mask)) |
(((out << 4) | in) << (mux_field * MUX_CTL_BIT_LEN));
__raw_writel(l, reg);
/*
* Log a warning if a pin changes ownership
*/
rp = iomux_pin_res_table + mux_index * MUX_CTL_FIELDS + mux_field;
if (out & *rp && *rp != ((out << 4) | in)) {
/*
* Don't call printk if we're tweaking the console uart or
* we'll deadlock.
*/
if (pin != MX31_PIN_CTS1 &&
pin != MX31_PIN_RTS1 &&
pin != MX31_PIN_DCD_DCE1 &&
pin != MX31_PIN_DSR_DTE1 &&
pin != MX31_PIN_DTR_DTE1 &&
pin != MX31_PIN_RI_DCE1 &&
pin != MX31_PIN_DSR_DCE1 &&
pin != MX31_PIN_DTR_DCE1 &&
pin != MX31_PIN_RXD1 && pin != MX31_PIN_TXD1) {
printk(KERN_ERR "iomux_config_mux: Warning: iomux pin"
" config changed, index=%d field=%d, "
" prev=0x%x new=0x%x\n", mux_index, mux_field,
*rp, (out << 4) | in);
}
ret = -EINVAL;
}
*rp = (out << 4) | in;
spin_unlock(&gpio_mux_lock);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_mode);
/*
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in)
{
int ret = iomux_config_mux(pin, out, in);
if (out == OUTPUTCONFIG_GPIO && in == INPUTCONFIG_GPIO) {
ret |= gpio_request(IOMUX_TO_GPIO(pin), NULL);
}
return ret;
}
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in)
{
u32 mux_index = PIN_TO_IOMUX_INDEX(pin);
u32 mux_field = PIN_TO_IOMUX_FIELD(pin);
u8 *rp = iomux_pin_res_table + mux_index * MUX_CTL_FIELDS + mux_field;
BUG_ON((mux_index > (MUX_PIN_NUM_MAX / MUX_CTL_FIELDS - 1)) ||
(mux_field >= MUX_CTL_FIELDS));
*rp = 0;
if (out == OUTPUTCONFIG_GPIO && in == INPUTCONFIG_GPIO) {
gpio_free(IOMUX_TO_GPIO(pin));
}
}
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b #iomux_pad_config_t
*/
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
{
u32 field, l;
void __iomem *reg;
u32 l;
u32 pad_index = (pin >> PAD_I) & ((1 << (PAD_F - PAD_I)) - 1);
u32 pad_field = (pin >> PAD_F) & ((1 << (MUX_IO_I - PAD_F)) - 1);
u32 pad_mask = GET_FIELD_MASK(MUX_PAD_BIT_LEN, pad_field);
pin &= IOMUX_PADNUM_MASK;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
__func__, (pin + 2) / 3, field);
BUG_ON((pad_index > (PAD_CTL_NUM_MAX / PAD_CTL_FIELDS - 1)) ||
(pad_field >= PAD_CTL_FIELDS));
reg = IOMUXSW_PAD_CTL + (pad_index * 4);
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
l = (l & (~pad_mask)) | (config << (pad_field * MUX_PAD_BIT_LEN));
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);
/*
* allocs a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
* FIXED ME: for backward compatible. to be removed!
*/
int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
void iomux_config_pad(iomux_pin_name_t pin, u32 config)
{
unsigned pad = pin & IOMUX_PADNUM_MASK;
if (pad >= (PIN_MAX + 1)) {
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
pad, label ? label : "?");
return -EINVAL;
}
if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
pad, label ? label : "?");
return -EBUSY;
}
mxc_iomux_mode(pin);
return 0;
mxc_iomux_set_pad(pin, config);
}
EXPORT_SYMBOL(mxc_iomux_alloc_pin);
int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
const char *label)
{
unsigned int *p = pin_list;
int i;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
ret = mxc_iomux_alloc_pin(*p, label);
if (ret)
goto setup_error;
p++;
}
return 0;
setup_error:
mxc_iomux_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
void mxc_iomux_release_pin(const unsigned int pin)
{
unsigned pad = pin & IOMUX_PADNUM_MASK;
if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map);
}
EXPORT_SYMBOL(mxc_iomux_release_pin);
void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
{
unsigned int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_release_pin(*p);
p++;
}
}
EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
/*
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en)
{
u32 l;
spin_lock(&gpio_mux_lock);
l = __raw_readl(IOMUXGPR);
if (en)
if (en) {
l |= gp;
else
} else {
l &= ~gp;
}
__raw_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock);
}
/*!
* FIXED ME: for backward compatible. to be removed!
*/
void iomux_config_gpr(iomux_gp_func_t gp, bool en)
{
mxc_iomux_set_gpr(gp, en);
}
EXPORT_SYMBOL(mxc_request_iomux);
EXPORT_SYMBOL(mxc_free_iomux);
EXPORT_SYMBOL(mxc_iomux_set_pad);
EXPORT_SYMBOL(mxc_iomux_set_gpr);
EXPORT_SYMBOL(iomux_config_pad);
EXPORT_SYMBOL(iomux_config_gpr);
EXPORT_SYMBOL(iomux_config_mux);

186
arch/arm/mach-mx3/iomux.h Normal file
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@@ -0,0 +1,186 @@
/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_MX31_IOMUX_H__
#define __MACH_MX31_IOMUX_H__
#include <linux/types.h>
#include <mach/gpio.h>
#include "mx31_pins.h"
typedef unsigned int iomux_pin_name_t;
/*!
* @file mach-mx3/iomux.h
*
* @brief I/O Muxing control definitions and functions
*
* @ingroup GPIO_MX31
*/
/*!
* various IOMUX output functions
*/
typedef enum iomux_output_config {
OUTPUTCONFIG_GPIO = 0, /*!< used as GPIO */
OUTPUTCONFIG_FUNC, /*!< used as function */
OUTPUTCONFIG_ALT1, /*!< used as alternate function 1 */
OUTPUTCONFIG_ALT2, /*!< used as alternate function 2 */
OUTPUTCONFIG_ALT3, /*!< used as alternate function 3 */
OUTPUTCONFIG_ALT4, /*!< used as alternate function 4 */
OUTPUTCONFIG_ALT5, /*!< used as alternate function 5 */
OUTPUTCONFIG_ALT6 /*!< used as alternate function 6 */
} iomux_pin_ocfg_t;
/*!
* various IOMUX input functions
*/
typedef enum iomux_input_config {
INPUTCONFIG_NONE = 0, /*!< not configured for input */
INPUTCONFIG_GPIO = 1 << 0, /*!< used as GPIO */
INPUTCONFIG_FUNC = 1 << 1, /*!< used as function */
INPUTCONFIG_ALT1 = 1 << 2, /*!< used as alternate function 1 */
INPUTCONFIG_ALT2 = 1 << 3 /*!< used as alternate function 2 */
} iomux_pin_icfg_t;
/*!
* various IOMUX pad functions
*/
typedef enum iomux_pad_config {
PAD_CTL_NOLOOPBACK = 0x0 << 9,
PAD_CTL_LOOPBACK = 0x1 << 9,
PAD_CTL_PKE_NONE = 0x0 << 8,
PAD_CTL_PKE_ENABLE = 0x1 << 8,
PAD_CTL_PUE_KEEPER = 0x0 << 7,
PAD_CTL_PUE_PUD = 0x1 << 7,
PAD_CTL_100K_PD = 0x0 << 5,
PAD_CTL_100K_PU = 0x1 << 5,
PAD_CTL_47K_PU = 0x2 << 5,
PAD_CTL_22K_PU = 0x3 << 5,
PAD_CTL_HYS_CMOS = 0x0 << 4,
PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
PAD_CTL_ODE_CMOS = 0x0 << 3,
PAD_CTL_ODE_OpenDrain = 0x1 << 3,
PAD_CTL_DRV_NORMAL = 0x0 << 1,
PAD_CTL_DRV_HIGH = 0x1 << 1,
PAD_CTL_DRV_MAX = 0x2 << 1,
PAD_CTL_SRE_SLOW = 0x0 << 0,
PAD_CTL_SRE_FAST = 0x1 << 0
} iomux_pad_config_t;
/*!
* various IOMUX general purpose functions
*/
typedef enum iomux_gp_func {
MUX_PGP_FIRI = 0x1 << 0,
MUX_DDR_MODE = 0x1 << 1,
MUX_PGP_CSPI_BB = 0x1 << 2,
MUX_PGP_ATA_1 = 0x1 << 3,
MUX_PGP_ATA_2 = 0x1 << 4,
MUX_PGP_ATA_3 = 0x1 << 5,
MUX_PGP_ATA_4 = 0x1 << 6,
MUX_PGP_ATA_5 = 0x1 << 7,
MUX_PGP_ATA_6 = 0x1 << 8,
MUX_PGP_ATA_7 = 0x1 << 9,
MUX_PGP_ATA_8 = 0x1 << 10,
MUX_PGP_UH2 = 0x1 << 11,
MUX_SDCTL_CSD0_SEL = 0x1 << 12,
MUX_SDCTL_CSD1_SEL = 0x1 << 13,
MUX_CSPI1_UART3 = 0x1 << 14,
MUX_EXTDMAREQ2_MBX_SEL = 0x1 << 15,
MUX_TAMPER_DETECT_EN = 0x1 << 16,
MUX_PGP_USB_4WIRE = 0x1 << 17,
MUX_PGB_USB_COMMON = 0x1 << 18,
MUX_SDHC_MEMSTICK1 = 0x1 << 19,
MUX_SDHC_MEMSTICK2 = 0x1 << 20,
MUX_PGP_SPLL_BYP = 0x1 << 21,
MUX_PGP_UPLL_BYP = 0x1 << 22,
MUX_PGP_MSHC1_CLK_SEL = 0x1 << 23,
MUX_PGP_MSHC2_CLK_SEL = 0x1 << 24,
MUX_CSPI3_UART5_SEL = 0x1 << 25,
MUX_PGP_ATA_9 = 0x1 << 26,
MUX_PGP_USB_SUSPEND = 0x1 << 27,
MUX_PGP_USB_OTG_LOOPBACK = 0x1 << 28,
MUX_PGP_USB_HS1_LOOPBACK = 0x1 << 29,
MUX_PGP_USB_HS2_LOOPBACK = 0x1 << 30,
MUX_CLKO_DDR_MODE = 0x1 << 31,
} iomux_gp_func_t;
/*!
* This function is used to configure a pin through the IOMUX module.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
* @return 0 if successful; Non-zero otherwise
*/
int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pins
* @param config ORed value of elements defined in \b #iomux_pad_config_t
*/
void iomux_config_pad(iomux_pin_name_t pin, __u32 config);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void iomux_config_gpr(iomux_gp_func_t gp, bool en);
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in);
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param out an output function as defined in \b #iomux_pin_ocfg_t
* @param in an input function as defined in \b #iomux_pin_icfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out,
iomux_pin_icfg_t in);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b #iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
#endif

22
arch/arm/mach-mx3/mm.c
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@@ -30,7 +30,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
/*!
* @file mm.c
*
@@ -43,7 +42,7 @@
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
static struct map_desc mx31_io_desc[] __initdata = {
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
@@ -64,6 +63,16 @@ static struct map_desc mxc_io_desc[] __initdata = {
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX31_IRAM_BASE_ADDR_VIRT & 0xFFF00000,
.pfn = __phys_to_pfn(MX31_IRAM_BASE_ADDR & 0xFFF00000),
.length = SZ_1M,
.type = MT_DEVICE_NONSHARED
},
};
@@ -76,14 +85,7 @@ void __init mx31_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
void __init mx35_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
#ifdef CONFIG_CACHE_L2X0

429
arch/arm/mach-mx3/mx31_pins.h Normal file
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@@ -0,0 +1,429 @@
/*
* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_MX31_PINS_H__
#define __ASM_ARCH_MXC_MX31_PINS_H__
/*!
* @file arch-mxc/mx31_pins.h
*
* @brief MX31 I/O Pin List
*
* @ingroup GPIO_MX31
*/
#ifndef __ASSEMBLY__
/*!
* @name IOMUX/PAD Bit field definitions
*/
/*! @{ */
/*!
* In order to identify pins more effectively, each mux-controlled pin's
* enumerated value is constructed in the following way:
*
* -------------------------------------------------------------------
* 31-29 | 28 - 24 |23 - 21| 20 | 19 - 18 | 17 - 10| 9 - 8 | 7 - 0
* -------------------------------------------------------------------
* IO_P | IO_I | RSVD | PAD_F | PAD_I | MUX_F | MUX_I
* -------------------------------------------------------------------
*
* Bit 0 to 7 contains MUX_I used to identify the register
* offset (0-based. base is IOMUX_module_base + 0xC) defined in the Section
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Bit 8 to 9 is MUX_F which
* contains the offset value defined WITHIN the same register (each IOMUX
* control register contains four 8-bit fields for four different pins). The
* similar field definitions are used for the pad control register.
* For example, the MX31_PIN_A0 is defined in the enumeration:
* ( 73 << MUX_I) | (0 << MUX_F)|( 98 << PAD_I) | (0 << PAD_F)
* It means the mux control register is at register offset 73. So the absolute
* address is: 0xC+73*4=0x130 0 << MUX_F means the control bits are at the
* least significant bits within the register. The pad control register offset
* is: 0x154+98*4=0x2DC and also occupy the least significant bits within the
* register.
*/
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* MUX control register index (0-based)
*/
#define MUX_I 0
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* field within IOMUX control register for control bits
* (legal values are 0, 1, 2, 3)
*/
#define MUX_F 8
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* PAD control register index (0-based)
*/
#define PAD_I 10
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* field within PAD control register for control bits
* (legal values are 0, 1, 2)
*/
#define PAD_F 18
#define _MXC_BUILD_PIN(gp,gi,mi,mf,pi,pf) \
((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | ((mi) << MUX_I) | \
((mf) << MUX_F) | ((pi) << PAD_I) | ((pf) << PAD_F)
#define _MXC_BUILD_GPIO_PIN(gp,gi,mi,mf,pi,pf) \
_MXC_BUILD_PIN(gp,gi,mi,mf,pi,pf)
#define _MXC_BUILD_NON_GPIO_PIN(mi,mf,pi,pf) \
_MXC_BUILD_PIN(7,0,mi,mf,pi,pf)
/*!
* This enumeration is constructed based on the Section
* "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
* value is constructed based on the rules described above.
*/
enum iomux_pins {
MX31_PIN_CSPI3_MISO = _MXC_BUILD_NON_GPIO_PIN(0, 3, 1, 2),
MX31_PIN_CSPI3_SCLK = _MXC_BUILD_NON_GPIO_PIN(0, 2, 1, 1),
MX31_PIN_CSPI3_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(0, 1, 1, 0),
MX31_PIN_TTM_PAD = _MXC_BUILD_NON_GPIO_PIN(0, 0, 0, 2),
MX31_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(2, 31, 1, 3, 3, 0),
MX31_PIN_CE_CONTROL = _MXC_BUILD_NON_GPIO_PIN(1, 2, 2, 2),
MX31_PIN_CLKSS = _MXC_BUILD_NON_GPIO_PIN(1, 1, 2, 1),
MX31_PIN_CSPI3_MOSI = _MXC_BUILD_NON_GPIO_PIN(1, 0, 2, 0),
MX31_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(2, 27, 2, 3, 4, 1),
MX31_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(2, 28, 2, 2, 4, 0),
MX31_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(2, 29, 2, 1, 3, 2),
MX31_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(2, 30, 2, 0, 3, 1),
MX31_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 29, 3, 3, 5, 2),
MX31_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 30, 3, 2, 5, 1),
MX31_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 31, 3, 1, 5, 0),
MX31_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0, 4, 2),
MX31_PIN_D3_SPL = _MXC_BUILD_NON_GPIO_PIN(4, 3, 7, 0),
MX31_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 26, 4, 2, 6, 2),
MX31_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 27, 4, 1, 6, 1),
MX31_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 28, 4, 0, 6, 0),
MX31_PIN_VSYNC3 = _MXC_BUILD_NON_GPIO_PIN(5, 3, 8, 1),
MX31_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(5, 2, 8, 0),
MX31_PIN_D3_REV = _MXC_BUILD_NON_GPIO_PIN(5, 1, 7, 2),
MX31_PIN_D3_CLS = _MXC_BUILD_NON_GPIO_PIN(5, 0, 7, 1),
MX31_PIN_SER_RS = _MXC_BUILD_GPIO_PIN(2, 25, 6, 3, 9, 2),
MX31_PIN_PAR_RS = _MXC_BUILD_NON_GPIO_PIN(6, 2, 9, 1),
MX31_PIN_WRITE = _MXC_BUILD_NON_GPIO_PIN(6, 1, 9, 0),
MX31_PIN_READ = _MXC_BUILD_NON_GPIO_PIN(6, 0, 8, 2),
MX31_PIN_SD_D_IO = _MXC_BUILD_GPIO_PIN(2, 21, 7, 3, 11, 0),
MX31_PIN_SD_D_CLK = _MXC_BUILD_GPIO_PIN(2, 22, 7, 2, 10, 2),
MX31_PIN_LCS0 = _MXC_BUILD_GPIO_PIN(2, 23, 7, 1, 10, 1),
MX31_PIN_LCS1 = _MXC_BUILD_GPIO_PIN(2, 24, 7, 0, 10, 0),
MX31_PIN_HSYNC = _MXC_BUILD_NON_GPIO_PIN(8, 3, 12, 1),
MX31_PIN_FPSHIFT = _MXC_BUILD_NON_GPIO_PIN(8, 2, 12, 0),
MX31_PIN_DRDY0 = _MXC_BUILD_NON_GPIO_PIN(8, 1, 11, 2),
MX31_PIN_SD_D_I = _MXC_BUILD_GPIO_PIN(2, 20, 8, 0, 11, 1),
MX31_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(9, 3, 13, 2),
MX31_PIN_LD16 = _MXC_BUILD_NON_GPIO_PIN(9, 2, 13, 1),
MX31_PIN_LD17 = _MXC_BUILD_NON_GPIO_PIN(9, 1, 13, 0),
MX31_PIN_VSYNC0 = _MXC_BUILD_NON_GPIO_PIN(9, 0, 12, 2),
MX31_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(10, 3, 15, 0),
MX31_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(10, 2, 14, 2),
MX31_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(10, 1, 14, 1),
MX31_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(10, 0, 14, 0),
MX31_PIN_LD7 = _MXC_BUILD_NON_GPIO_PIN(11, 3, 16, 1),
MX31_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(11, 2, 16, 0),
MX31_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(11, 1, 15, 2),
MX31_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(11, 0, 15, 1),
MX31_PIN_LD3 = _MXC_BUILD_NON_GPIO_PIN(12, 3, 17, 2),
MX31_PIN_LD4 = _MXC_BUILD_NON_GPIO_PIN(12, 2, 17, 1),
MX31_PIN_LD5 = _MXC_BUILD_NON_GPIO_PIN(12, 1, 17, 0),
MX31_PIN_LD6 = _MXC_BUILD_NON_GPIO_PIN(12, 0, 16, 2),
MX31_PIN_USBH2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(13, 3, 19, 0),
MX31_PIN_LD0 = _MXC_BUILD_NON_GPIO_PIN(13, 2, 18, 2),
MX31_PIN_LD1 = _MXC_BUILD_NON_GPIO_PIN(13, 1, 18, 1),
MX31_PIN_LD2 = _MXC_BUILD_NON_GPIO_PIN(13, 0, 18, 0),
MX31_PIN_USBH2_DIR = _MXC_BUILD_NON_GPIO_PIN(14, 3, 20, 1),
MX31_PIN_USBH2_STP = _MXC_BUILD_NON_GPIO_PIN(14, 2, 20, 0),
MX31_PIN_USBH2_NXT = _MXC_BUILD_NON_GPIO_PIN(14, 1, 19, 2),
MX31_PIN_USBH2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(14, 0, 19, 1),
MX31_PIN_USBOTG_DATA5 = _MXC_BUILD_NON_GPIO_PIN(15, 3, 21, 2),
MX31_PIN_USBOTG_DATA6 = _MXC_BUILD_NON_GPIO_PIN(15, 2, 21, 1),
MX31_PIN_USBOTG_DATA7 = _MXC_BUILD_NON_GPIO_PIN(15, 1, 21, 0),
MX31_PIN_USBH2_CLK = _MXC_BUILD_NON_GPIO_PIN(15, 0, 20, 2),
MX31_PIN_USBOTG_DATA1 = _MXC_BUILD_NON_GPIO_PIN(16, 3, 23, 0),
MX31_PIN_USBOTG_DATA2 = _MXC_BUILD_NON_GPIO_PIN(16, 2, 22, 2),
MX31_PIN_USBOTG_DATA3 = _MXC_BUILD_NON_GPIO_PIN(16, 1, 22, 1),
MX31_PIN_USBOTG_DATA4 = _MXC_BUILD_NON_GPIO_PIN(16, 0, 22, 0),
MX31_PIN_USBOTG_DIR = _MXC_BUILD_NON_GPIO_PIN(17, 3, 24, 1),
MX31_PIN_USBOTG_STP = _MXC_BUILD_NON_GPIO_PIN(17, 2, 24, 0),
MX31_PIN_USBOTG_NXT = _MXC_BUILD_NON_GPIO_PIN(17, 1, 23, 2),
MX31_PIN_USBOTG_DATA0 = _MXC_BUILD_NON_GPIO_PIN(17, 0, 23, 1),
MX31_PIN_USB_PWR = _MXC_BUILD_GPIO_PIN(0, 29, 18, 3, 25, 2),
MX31_PIN_USB_OC = _MXC_BUILD_GPIO_PIN(0, 30, 18, 2, 25, 1),
MX31_PIN_USB_BYP = _MXC_BUILD_GPIO_PIN(0, 31, 18, 1, 25, 0),
MX31_PIN_USBOTG_CLK = _MXC_BUILD_NON_GPIO_PIN(18, 0, 24, 2),
MX31_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(19, 3, 27, 0),
MX31_PIN_TRSTB = _MXC_BUILD_NON_GPIO_PIN(19, 2, 26, 2),
MX31_PIN_DE_B = _MXC_BUILD_NON_GPIO_PIN(19, 1, 26, 1),
MX31_PIN_SJC_MOD = _MXC_BUILD_NON_GPIO_PIN(19, 0, 26, 0),
MX31_PIN_RTCK = _MXC_BUILD_NON_GPIO_PIN(20, 3, 28, 1),
MX31_PIN_TCK = _MXC_BUILD_NON_GPIO_PIN(20, 2, 28, 0),
MX31_PIN_TMS = _MXC_BUILD_NON_GPIO_PIN(20, 1, 27, 2),
MX31_PIN_TDI = _MXC_BUILD_NON_GPIO_PIN(20, 0, 27, 1),
MX31_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(1, 22, 21, 3, 29, 2),
MX31_PIN_KEY_COL5 = _MXC_BUILD_GPIO_PIN(1, 23, 21, 2, 29, 1),
MX31_PIN_KEY_COL6 = _MXC_BUILD_GPIO_PIN(1, 24, 21, 1, 29, 0),
MX31_PIN_KEY_COL7 = _MXC_BUILD_GPIO_PIN(1, 25, 21, 0, 28, 2),
MX31_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(22, 3, 31, 0),
MX31_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(22, 2, 30, 2),
MX31_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(22, 1, 30, 1),
MX31_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(22, 0, 30, 0),
MX31_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(1, 18, 23, 3, 32, 1),
MX31_PIN_KEY_ROW5 = _MXC_BUILD_GPIO_PIN(1, 19, 23, 2, 32, 0),
MX31_PIN_KEY_ROW6 = _MXC_BUILD_GPIO_PIN(1, 20, 23, 1, 31, 2),
MX31_PIN_KEY_ROW7 = _MXC_BUILD_GPIO_PIN(1, 21, 23, 0, 31, 1),
MX31_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(24, 3, 33, 2),
MX31_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(24, 2, 33, 1),
MX31_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(24, 1, 33, 0),
MX31_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(24, 0, 32, 2),
MX31_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(0, 28, 25, 3, 35, 0),
MX31_PIN_RTS2 = _MXC_BUILD_NON_GPIO_PIN(25, 2, 34, 2),
MX31_PIN_CTS2 = _MXC_BUILD_NON_GPIO_PIN(25, 1, 34, 1),
MX31_PIN_BATT_LINE = _MXC_BUILD_GPIO_PIN(1, 17, 25, 0, 34, 0),
MX31_PIN_RI_DTE1 = _MXC_BUILD_GPIO_PIN(1, 14, 26, 3, 36, 1),
MX31_PIN_DCD_DTE1 = _MXC_BUILD_GPIO_PIN(1, 15, 26, 2, 36, 0),
MX31_PIN_DTR_DCE2 = _MXC_BUILD_GPIO_PIN(1, 16, 26, 1, 35, 2),
MX31_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(0, 27, 26, 0, 35, 1),
MX31_PIN_RI_DCE1 = _MXC_BUILD_GPIO_PIN(1, 10, 27, 3, 37, 2),
MX31_PIN_DCD_DCE1 = _MXC_BUILD_GPIO_PIN(1, 11, 27, 2, 37, 1),
MX31_PIN_DTR_DTE1 = _MXC_BUILD_GPIO_PIN(1, 12, 27, 1, 37, 0),
MX31_PIN_DSR_DTE1 = _MXC_BUILD_GPIO_PIN(1, 13, 27, 0, 36, 2),
MX31_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(1, 6, 28, 3, 39, 0),
MX31_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(1, 7, 28, 2, 38, 2),
MX31_PIN_DTR_DCE1 = _MXC_BUILD_GPIO_PIN(1, 8, 28, 1, 38, 1),
MX31_PIN_DSR_DCE1 = _MXC_BUILD_GPIO_PIN(1, 9, 28, 0, 38, 0),
MX31_PIN_CSPI2_SCLK = _MXC_BUILD_NON_GPIO_PIN(29, 3, 40, 1),
MX31_PIN_CSPI2_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(29, 2, 40, 0),
MX31_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(1, 4, 29, 1, 39, 2),
MX31_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(1, 5, 29, 0, 39, 1),
MX31_PIN_CSPI2_MISO = _MXC_BUILD_NON_GPIO_PIN(30, 3, 41, 2),
MX31_PIN_CSPI2_SS0 = _MXC_BUILD_NON_GPIO_PIN(30, 2, 41, 1),
MX31_PIN_CSPI2_SS1 = _MXC_BUILD_NON_GPIO_PIN(30, 1, 41, 0),
MX31_PIN_CSPI2_SS2 = _MXC_BUILD_NON_GPIO_PIN(30, 0, 40, 2),
MX31_PIN_CSPI1_SS2 = _MXC_BUILD_NON_GPIO_PIN(31, 3, 43, 0),
MX31_PIN_CSPI1_SCLK = _MXC_BUILD_NON_GPIO_PIN(31, 2, 42, 2),
MX31_PIN_CSPI1_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(31, 1, 42, 1),
MX31_PIN_CSPI2_MOSI = _MXC_BUILD_NON_GPIO_PIN(31, 0, 42, 0),
MX31_PIN_CSPI1_MOSI = _MXC_BUILD_NON_GPIO_PIN(32, 3, 44, 1),
MX31_PIN_CSPI1_MISO = _MXC_BUILD_NON_GPIO_PIN(32, 2, 44, 0),
MX31_PIN_CSPI1_SS0 = _MXC_BUILD_NON_GPIO_PIN(32, 1, 43, 2),
MX31_PIN_CSPI1_SS1 = _MXC_BUILD_NON_GPIO_PIN(32, 0, 43, 1),
MX31_PIN_STXD6 = _MXC_BUILD_GPIO_PIN(0, 23, 33, 3, 45, 2),
MX31_PIN_SRXD6 = _MXC_BUILD_GPIO_PIN(0, 24, 33, 2, 45, 1),
MX31_PIN_SCK6 = _MXC_BUILD_GPIO_PIN(0, 25, 33, 1, 45, 0),
MX31_PIN_SFS6 = _MXC_BUILD_GPIO_PIN(0, 26, 33, 0, 44, 2),
MX31_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 21, 34, 3, 47, 0),
MX31_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 22, 34, 2, 46, 2),
MX31_PIN_SCK5 = _MXC_BUILD_NON_GPIO_PIN(34, 1, 46, 1),
MX31_PIN_SFS5 = _MXC_BUILD_NON_GPIO_PIN(34, 0, 46, 0),
MX31_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(0, 19, 35, 3, 48, 1),
MX31_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(0, 20, 35, 2, 48, 0),
MX31_PIN_SCK4 = _MXC_BUILD_NON_GPIO_PIN(35, 1, 47, 2),
MX31_PIN_SFS4 = _MXC_BUILD_NON_GPIO_PIN(35, 0, 47, 1),
MX31_PIN_STXD3 = _MXC_BUILD_GPIO_PIN(0, 17, 36, 3, 49, 2),
MX31_PIN_SRXD3 = _MXC_BUILD_GPIO_PIN(0, 18, 36, 2, 49, 1),
MX31_PIN_SCK3 = _MXC_BUILD_NON_GPIO_PIN(36, 1, 49, 0),
MX31_PIN_SFS3 = _MXC_BUILD_NON_GPIO_PIN(36, 0, 48, 2),
MX31_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(2, 18, 37, 3, 51, 0),
MX31_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(2, 19, 37, 2, 50, 2),
MX31_PIN_I2C_CLK = _MXC_BUILD_NON_GPIO_PIN(37, 1, 50, 1),
MX31_PIN_I2C_DAT = _MXC_BUILD_NON_GPIO_PIN(37, 0, 50, 0),
MX31_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(2, 14, 38, 3, 52, 1),
MX31_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(2, 15, 38, 2, 52, 0),
MX31_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(2, 16, 38, 1, 51, 2),
MX31_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(2, 17, 38, 0, 51, 1),
MX31_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(2, 10, 39, 3, 53, 2),
MX31_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(2, 11, 39, 2, 53, 1),
MX31_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(2, 12, 39, 1, 53, 0),
MX31_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(2, 13, 39, 0, 52, 2),
MX31_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(2, 6, 40, 3, 55, 0),
MX31_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(2, 7, 40, 2, 54, 2),
MX31_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(2, 8, 40, 1, 54, 1),
MX31_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(2, 9, 40, 0, 54, 0),
MX31_PIN_M_REQUEST = _MXC_BUILD_NON_GPIO_PIN(41, 3, 56, 1),
MX31_PIN_M_GRANT = _MXC_BUILD_NON_GPIO_PIN(41, 2, 56, 0),
MX31_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(2, 4, 41, 1, 55, 2),
MX31_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(2, 5, 41, 0, 55, 1),
MX31_PIN_PC_RST = _MXC_BUILD_NON_GPIO_PIN(42, 3, 57, 2),
MX31_PIN_IOIS16 = _MXC_BUILD_NON_GPIO_PIN(42, 2, 57, 1),
MX31_PIN_PC_RW_B = _MXC_BUILD_NON_GPIO_PIN(42, 1, 57, 0),
MX31_PIN_PC_POE = _MXC_BUILD_NON_GPIO_PIN(42, 0, 56, 2),
MX31_PIN_PC_VS1 = _MXC_BUILD_NON_GPIO_PIN(43, 3, 59, 0),
MX31_PIN_PC_VS2 = _MXC_BUILD_NON_GPIO_PIN(43, 2, 58, 2),
MX31_PIN_PC_BVD1 = _MXC_BUILD_NON_GPIO_PIN(43, 1, 58, 1),
MX31_PIN_PC_BVD2 = _MXC_BUILD_NON_GPIO_PIN(43, 0, 58, 0),
MX31_PIN_PC_CD2_B = _MXC_BUILD_NON_GPIO_PIN(44, 3, 60, 1),
MX31_PIN_PC_WAIT_B = _MXC_BUILD_NON_GPIO_PIN(44, 2, 60, 0),
MX31_PIN_PC_READY = _MXC_BUILD_NON_GPIO_PIN(44, 1, 59, 2),
MX31_PIN_PC_PWRON = _MXC_BUILD_NON_GPIO_PIN(44, 0, 59, 1),
MX31_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(45, 3, 61, 2),
MX31_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(45, 2, 61, 1),
MX31_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(45, 1, 61, 0),
MX31_PIN_PC_CD1_B = _MXC_BUILD_NON_GPIO_PIN(45, 0, 60, 2),
MX31_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(46, 3, 63, 0),
MX31_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(46, 2, 62, 2),
MX31_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(46, 1, 62, 1),
MX31_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(46, 0, 62, 0),
MX31_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(47, 3, 64, 1),
MX31_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(47, 2, 64, 0),
MX31_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(47, 1, 63, 2),
MX31_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(47, 0, 63, 1),
MX31_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(48, 3, 65, 2),
MX31_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(48, 2, 65, 1),
MX31_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(48, 1, 65, 0),
MX31_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(48, 0, 64, 2),
MX31_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 14, 49, 3, 67, 0),
MX31_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 15, 49, 2, 66, 2),
MX31_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 16, 49, 1, 66, 1),
MX31_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(49, 0, 66, 0),
MX31_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 10, 50, 3, 68, 1),
MX31_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 11, 50, 2, 68, 0),
MX31_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 12, 50, 1, 67, 2),
MX31_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 13, 50, 0, 67, 1),
MX31_PIN_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(51, 3, 69, 2),
MX31_PIN_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(51, 2, 69, 1),
MX31_PIN_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(51, 1, 69, 0),
MX31_PIN_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(51, 0, 68, 2),
MX31_PIN_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(52, 3, 71, 0),
MX31_PIN_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(52, 2, 70, 2),
MX31_PIN_SDCLK = _MXC_BUILD_NON_GPIO_PIN(52, 1, 70, 1),
MX31_PIN_SDCLK_B = _MXC_BUILD_NON_GPIO_PIN(52, 0, 70, 0),
MX31_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(53, 3, 72, 1),
MX31_PIN_RAS = _MXC_BUILD_NON_GPIO_PIN(53, 2, 72, 0),
MX31_PIN_CAS = _MXC_BUILD_NON_GPIO_PIN(53, 1, 71, 2),
MX31_PIN_SDWE = _MXC_BUILD_NON_GPIO_PIN(53, 0, 71, 1),
MX31_PIN_CS5 = _MXC_BUILD_NON_GPIO_PIN(54, 3, 73, 2),
MX31_PIN_ECB = _MXC_BUILD_NON_GPIO_PIN(54, 2, 73, 1),
MX31_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(54, 1, 73, 0),
MX31_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(54, 0, 72, 2),
MX31_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(55, 3, 75, 0),
MX31_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(55, 2, 74, 2),
MX31_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(55, 1, 74, 1),
MX31_PIN_CS4 = _MXC_BUILD_NON_GPIO_PIN(55, 0, 74, 0),
MX31_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(56, 3, 76, 1),
MX31_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(56, 2, 76, 0),
MX31_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(56, 1, 75, 2),
MX31_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(56, 0, 75, 1),
MX31_PIN_DQM0 = _MXC_BUILD_NON_GPIO_PIN(57, 3, 77, 2),
MX31_PIN_DQM1 = _MXC_BUILD_NON_GPIO_PIN(57, 2, 77, 1),
MX31_PIN_DQM2 = _MXC_BUILD_NON_GPIO_PIN(57, 1, 77, 0),
MX31_PIN_DQM3 = _MXC_BUILD_NON_GPIO_PIN(57, 0, 76, 2),
MX31_PIN_SD28 = _MXC_BUILD_NON_GPIO_PIN(58, 3, 79, 0),
MX31_PIN_SD29 = _MXC_BUILD_NON_GPIO_PIN(58, 2, 78, 2),
MX31_PIN_SD30 = _MXC_BUILD_NON_GPIO_PIN(58, 1, 78, 1),
MX31_PIN_SD31 = _MXC_BUILD_NON_GPIO_PIN(58, 0, 78, 0),
MX31_PIN_SD24 = _MXC_BUILD_NON_GPIO_PIN(59, 3, 80, 1),
MX31_PIN_SD25 = _MXC_BUILD_NON_GPIO_PIN(59, 2, 80, 0),
MX31_PIN_SD26 = _MXC_BUILD_NON_GPIO_PIN(59, 1, 79, 2),
MX31_PIN_SD27 = _MXC_BUILD_NON_GPIO_PIN(59, 0, 79, 1),
MX31_PIN_SD20 = _MXC_BUILD_NON_GPIO_PIN(60, 3, 81, 2),
MX31_PIN_SD21 = _MXC_BUILD_NON_GPIO_PIN(60, 2, 81, 1),
MX31_PIN_SD22 = _MXC_BUILD_NON_GPIO_PIN(60, 1, 81, 0),
MX31_PIN_SD23 = _MXC_BUILD_NON_GPIO_PIN(60, 0, 80, 2),
MX31_PIN_SD16 = _MXC_BUILD_NON_GPIO_PIN(61, 3, 83, 0),
MX31_PIN_SD17 = _MXC_BUILD_NON_GPIO_PIN(61, 2, 82, 2),
MX31_PIN_SD18 = _MXC_BUILD_NON_GPIO_PIN(61, 1, 82, 1),
MX31_PIN_SD19 = _MXC_BUILD_NON_GPIO_PIN(61, 0, 82, 0),
MX31_PIN_SD12 = _MXC_BUILD_NON_GPIO_PIN(62, 3, 84, 1),
MX31_PIN_SD13 = _MXC_BUILD_NON_GPIO_PIN(62, 2, 84, 0),
MX31_PIN_SD14 = _MXC_BUILD_NON_GPIO_PIN(62, 1, 83, 2),
MX31_PIN_SD15 = _MXC_BUILD_NON_GPIO_PIN(62, 0, 83, 1),
MX31_PIN_SD8 = _MXC_BUILD_NON_GPIO_PIN(63, 3, 85, 2),
MX31_PIN_SD9 = _MXC_BUILD_NON_GPIO_PIN(63, 2, 85, 1),
MX31_PIN_SD10 = _MXC_BUILD_NON_GPIO_PIN(63, 1, 85, 0),
MX31_PIN_SD11 = _MXC_BUILD_NON_GPIO_PIN(63, 0, 84, 2),
MX31_PIN_SD4 = _MXC_BUILD_NON_GPIO_PIN(64, 3, 87, 0),
MX31_PIN_SD5 = _MXC_BUILD_NON_GPIO_PIN(64, 2, 86, 2),
MX31_PIN_SD6 = _MXC_BUILD_NON_GPIO_PIN(64, 1, 86, 1),
MX31_PIN_SD7 = _MXC_BUILD_NON_GPIO_PIN(64, 0, 86, 0),
MX31_PIN_SD0 = _MXC_BUILD_NON_GPIO_PIN(65, 3, 88, 1),
MX31_PIN_SD1 = _MXC_BUILD_NON_GPIO_PIN(65, 2, 88, 0),
MX31_PIN_SD2 = _MXC_BUILD_NON_GPIO_PIN(65, 1, 87, 2),
MX31_PIN_SD3 = _MXC_BUILD_NON_GPIO_PIN(65, 0, 87, 1),
MX31_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(66, 3, 89, 2),
MX31_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(66, 2, 89, 1),
MX31_PIN_SDBA1 = _MXC_BUILD_NON_GPIO_PIN(66, 1, 89, 0),
MX31_PIN_SDBA0 = _MXC_BUILD_NON_GPIO_PIN(66, 0, 88, 2),
MX31_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(67, 3, 91, 0),
MX31_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(67, 2, 90, 2),
MX31_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(67, 1, 90, 1),
MX31_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(67, 0, 90, 0),
MX31_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(68, 3, 92, 1),
MX31_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(68, 2, 92, 0),
MX31_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(68, 1, 91, 2),
MX31_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(68, 0, 91, 1),
MX31_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(69, 3, 93, 2),
MX31_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(69, 2, 93, 1),
MX31_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(69, 1, 93, 0),
MX31_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(69, 0, 92, 2),
MX31_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(70, 3, 95, 0),
MX31_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(70, 2, 94, 2),
MX31_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(70, 1, 94, 1),
MX31_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(70, 0, 94, 0),
MX31_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(71, 3, 96, 1),
MX31_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(71, 2, 96, 0),
MX31_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(71, 1, 95, 2),
MX31_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(71, 0, 95, 1),
MX31_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(72, 3, 97, 2),
MX31_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(72, 2, 97, 1),
MX31_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(72, 1, 97, 0),
MX31_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(72, 0, 96, 2),
MX31_PIN_DVFS1 = _MXC_BUILD_NON_GPIO_PIN(73, 3, 99, 0),
MX31_PIN_VPG0 = _MXC_BUILD_NON_GPIO_PIN(73, 2, 98, 2),
MX31_PIN_VPG1 = _MXC_BUILD_NON_GPIO_PIN(73, 1, 98, 1),
MX31_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(73, 0, 98, 0),
MX31_PIN_CKIL = _MXC_BUILD_NON_GPIO_PIN(74, 3, 100, 1),
MX31_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(74, 2, 100, 0),
MX31_PIN_VSTBY = _MXC_BUILD_NON_GPIO_PIN(74, 1, 99, 2),
MX31_PIN_DVFS0 = _MXC_BUILD_NON_GPIO_PIN(74, 0, 99, 1),
MX31_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(75, 3, 101, 2),
MX31_PIN_BOOT_MODE2 = _MXC_BUILD_NON_GPIO_PIN(75, 2, 101, 1),
MX31_PIN_BOOT_MODE3 = _MXC_BUILD_NON_GPIO_PIN(75, 1, 101, 0),
MX31_PIN_BOOT_MODE4 = _MXC_BUILD_NON_GPIO_PIN(75, 0, 100, 2),
MX31_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(76, 3, 103, 0),
MX31_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(76, 2, 102, 2),
MX31_PIN_CLKO = _MXC_BUILD_NON_GPIO_PIN(76, 1, 102, 1),
MX31_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(76, 0, 102, 0),
MX31_PIN_STX0 = _MXC_BUILD_GPIO_PIN(1, 1, 77, 3, 104, 1),
MX31_PIN_SRX0 = _MXC_BUILD_GPIO_PIN(1, 2, 77, 2, 104, 0),
MX31_PIN_SIMPD0 = _MXC_BUILD_GPIO_PIN(1, 3, 77, 1, 103, 2),
MX31_PIN_CKIH = _MXC_BUILD_NON_GPIO_PIN(77, 0, 103, 1),
MX31_PIN_GPIO3_1 = _MXC_BUILD_GPIO_PIN(2, 1, 78, 3, 105, 2),
MX31_PIN_SCLK0 = _MXC_BUILD_GPIO_PIN(2, 2, 78, 2, 105, 1),
MX31_PIN_SRST0 = _MXC_BUILD_GPIO_PIN(2, 3, 78, 1, 105, 0),
MX31_PIN_SVEN0 = _MXC_BUILD_GPIO_PIN(1, 0, 78, 0, 104, 2),
MX31_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 79, 3, 107, 0),
MX31_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 79, 2, 106, 2),
MX31_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 79, 1, 106, 1),
MX31_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 0, 79, 0, 106, 0),
MX31_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 80, 3, 108, 1),
MX31_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 80, 2, 108, 0),
MX31_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 80, 1, 107, 2),
MX31_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 80, 0, 107, 1),
MX31_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 7, 81, 3, 109, 2),
MX31_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 8, 81, 2, 109, 1),
MX31_PIN_WATCHDOG_RST = _MXC_BUILD_NON_GPIO_PIN(81, 1, 109, 0),
MX31_PIN_PWMO = _MXC_BUILD_GPIO_PIN(0, 9, 81, 0, 108, 2),
};
#endif
#endif

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arch/arm/mach-mx3/mx31ads.c
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arch/arm/mach-mx3/mx31ads_gpio.c Normal file
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arch/arm/mach-mx3/mx3_3stack.c Normal file
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arch/arm/mach-mx3/mx3_3stack_gpio.c Normal file
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arch/arm/mach-mx3/mx3_3stack_pmic_mc13783.c Normal file
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/*
* mx3-3stack-pmic-mc13783.c -- i.MX3 3STACK Driver for Atlas MC13783 PMIC
*/
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/pmic_external.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc13783/core.h>
#include <mach/irqs.h>
#include "iomux.h"
/*
* Convenience conversion.
* Here atm, maybe there is somewhere better for this.
*/
#define mV_to_uV(mV) (mV * 1000)
struct mc13783;
static struct regulator_init_data violo_init = {
.constraints = {
.min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */
.max_uV = mV_to_uV(1800), /* mc13783 allows max of 1800. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vdig_init = {
.constraints = {
.min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */
.max_uV = mV_to_uV(1800), /* mc13783 allows max of 1800. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vgen_init = {
.constraints = {
.min_uV = mV_to_uV(1100), /* mc13783 allows min of 1100. */
.max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vrfdig_init = {
.constraints = {
.min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */
.max_uV = mV_to_uV(1875), /* mc13783 allows max of 1875. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vrfref_init = {
.constraints = {
.min_uV = mV_to_uV(2475), /* mc13783 allows min of 2475. */
.max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vrfcp_init = {
.constraints = {
.min_uV = mV_to_uV(2700), /* mc13783 allows min of 2700. */
.max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vsim_init = {
.constraints = {
.min_uV = mV_to_uV(1800), /* mc13783 allows min of 1800. */
.max_uV = mV_to_uV(2900), /* mc13783 allows max of 2900. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vesim_init = {
.constraints = {
.min_uV = mV_to_uV(1800), /* mc13783 allows min of 1800. */
.max_uV = mV_to_uV(2900), /* mc13783 allows max of 2900. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vcam_init = {
.constraints = {
.min_uV = mV_to_uV(1500), /* mc13783 allows min of 1500. */
.max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vvib_init = {
.constraints = {
.min_uV = mV_to_uV(1300), /* mc13783 allows min of 1300. */
.max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vrf_init = {
.constraints = {
.min_uV = mV_to_uV(1500), /* mc13783 allows min of 1500. */
.max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vmmc_init = {
.constraints = {
.min_uV = mV_to_uV(1600), /* mc13783 allows min of 1600. */
.max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data sw3_init = {
.constraints = {
.min_uV = mV_to_uV(5000), /* mc13783 allows min of 5000. */
.max_uV = mV_to_uV(5500), /* mc13783 allows max of 5500. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data sw1_init = {
.constraints = {
.min_uV = mV_to_uV(1200), /* mc13783 allows min of 900. */
.max_uV = mV_to_uV(1600), /* mc13783 allows max of 2200. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_FAST
| REGULATOR_MODE_NORMAL
| REGULATOR_MODE_IDLE
| REGULATOR_MODE_STANDBY,
.always_on = 1,
.boot_on = 1,
.initial_state = PM_SUSPEND_MEM,
.state_mem = {
.uV = mV_to_uV(1250),
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
}
};
static struct regulator_init_data sw_init = {
.constraints = {
.min_uV = mV_to_uV(1200), /* mc13783 allows min of 900. */
.max_uV = mV_to_uV(2200), /* mc13783 allows max of 2200. */
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vaudio_init = {
.constraints = {
.boot_on = 1,
}
};
static struct regulator_init_data viohi_init = {
.constraints = {
.boot_on = 1,
}
};
static struct regulator_init_data gpo1_init = {
.constraints = {
.boot_on = 1,
}
};
static struct regulator_init_data gpo4_init = {
.constraints = {
},
};
static struct regulator_init_data gpo_init = {
.constraints = {
},
};
static int mc13783_regulator_init(void *data)
{
struct mc13783 *mc13783 = data;
unsigned int value;
/*most regulators are controled by standby signal*/
/*except violo*/
pmic_read_reg(REG_REGULATOR_MODE_0, &value, 0xffffff);
value |= 0x492412;
pmic_write_reg(REG_REGULATOR_MODE_0, value, 0xffffff);
pmic_read_reg(REG_REGULATOR_MODE_1, &value, 0xffffff);
value |= 0x492492;
pmic_write_reg(REG_REGULATOR_MODE_1, value, 0xffffff);
/*also sw3 is controled by standby signal*/
pmic_read_reg(REG_SWITCHERS_5, &value, 0xffffff);
value |= 0x200000;
pmic_write_reg(REG_SWITCHERS_5, value, 0xffffff);
mc13783_register_regulator(mc13783, MC13783_SW1A, &sw1_init);
mc13783_register_regulator(mc13783, MC13783_SW1B, &sw_init);
mc13783_register_regulator(mc13783, MC13783_SW2A, &sw_init);
mc13783_register_regulator(mc13783, MC13783_SW2B, &sw_init);
mc13783_register_regulator(mc13783, MC13783_SW3, &sw3_init);
mc13783_register_regulator(mc13783, MC13783_VMMC1, &vmmc_init);
mc13783_register_regulator(mc13783, MC13783_VMMC2, &vmmc_init);
mc13783_register_regulator(mc13783, MC13783_VVIB, &vvib_init);
mc13783_register_regulator(mc13783, MC13783_VIOHI, &viohi_init);
mc13783_register_regulator(mc13783, MC13783_VIOLO, &violo_init);
mc13783_register_regulator(mc13783, MC13783_VDIG, &vdig_init);
mc13783_register_regulator(mc13783, MC13783_VRFDIG, &vrfdig_init);
mc13783_register_regulator(mc13783, MC13783_VRFREF, &vrfref_init);
mc13783_register_regulator(mc13783, MC13783_VRFCP, &vrfcp_init);
mc13783_register_regulator(mc13783, MC13783_VRF1, &vrf_init);
mc13783_register_regulator(mc13783, MC13783_VRF2, &vrf_init);
mc13783_register_regulator(mc13783, MC13783_VAUDIO, &vaudio_init);
mc13783_register_regulator(mc13783, MC13783_VCAM, &vcam_init);
mc13783_register_regulator(mc13783, MC13783_VGEN, &vgen_init);
mc13783_register_regulator(mc13783, MC13783_VSIM, &vsim_init);
mc13783_register_regulator(mc13783, MC13783_VESIM, &vesim_init);
mc13783_register_regulator(mc13783, MC13783_GPO1, &gpo1_init);
gpo_init.supply_regulator_dev = &(mc13783->pmic.pdev[MC13783_GPO1]->dev);
mc13783_register_regulator(mc13783, MC13783_GPO2, &gpo_init);
mc13783_register_regulator(mc13783, MC13783_GPO3, &gpo_init);
mc13783_register_regulator(mc13783, MC13783_GPO4, &gpo4_init);
return 0;
}
static struct pmic_platform_data mc13783_plat = {
.init = mc13783_regulator_init,
.power_key_irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
};
static struct spi_board_info __initdata mc13783_spi_device = {
.modalias = "pmic_spi",
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
.max_speed_hz = 4000000,
.bus_num = 2,
.platform_data = &mc13783_plat,
.chip_select = 2,
};
int __init mx3_3stack_init_mc13783(void)
{
return spi_register_board_info(&mc13783_spi_device, 1);
}

440
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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @defgroup DPM_MX31 Power Management
* @ingroup MSL_MX31
*/
/*!
* @file mach-mx3/mxc_pm.c
*
* @brief This file provides all the kernel level and user level API
* definitions for the CRM_MCU and DPLL in mx3.
*
* @ingroup DPM_MX31
*/
/*
* Include Files
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/system.h>
#include <mach/mxc_pm.h>
#include <asm/cacheflush.h>
#include <asm/irq.h>
#include <mach/common.h>
#include <asm/hardware/cache-l2x0.h>
#include "crm_regs.h"
/* Local defines */
#define FREQ_COMP_TOLERANCE 200 /* tolerance percentage times 100 */
#define MCU_PLL_MAX_FREQ 600000000 /* Maximum frequency MCU PLL clock */
#define MCU_PLL_MIN_FREQ 160000000 /* Minimum frequency MCU PLL clock */
#define NFC_MAX_FREQ 20000000 /* Maximum frequency NFC clock */
#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
static struct clk *mcu_pll_clk;
static struct clk *cpu_clk;
static struct clk *ahb_clk;
static struct clk *ipg_clk;
/*!
* Spinlock to protect CRM register accesses
*/
static DEFINE_SPINLOCK(mxc_crm_lock);
/*!
* This function is called to modify the contents of a CCM_MCU register
*
* @param reg_offset the CCM_MCU register that will read
* @param mask the mask to be used to clear the bits that are to be modified
* @param data the data that should be written to the register
*/
void mxc_ccm_modify_reg(void *reg_offset, unsigned int mask,
unsigned int data)
{
unsigned long flags;
unsigned long reg;
spin_lock_irqsave(&mxc_crm_lock, flags);
reg = __raw_readl(reg_offset);
reg = (reg & (~mask)) | data;
__raw_writel(reg, reg_offset);
spin_unlock_irqrestore(&mxc_crm_lock, flags);
}
/*!
* Compare two frequences using allowable tolerance
*
* The MX3 PLL can generate many frequencies. This function
* compares the generated frequency to the requested frequency
* and determines it they are within and acceptable tolerance.
*
* @param freq1 desired frequency
* @param freq2 generated frequency
*
* @return Returns 0 is frequencies are within talerance
* and non-zero is they are not.
*/
static int freq_equal(unsigned long freq1, unsigned long freq2)
{
if (freq1 > freq2) {
return (freq1 - freq2) <= (freq1 / FREQ_COMP_TOLERANCE);
}
return (freq2 - freq1) <= (freq1 / FREQ_COMP_TOLERANCE);
}
/*!
* Calculate new MCU clock dividers for the PDR0 regiser.
*
* @param mcu_main_clk PLL output frequency (Hz)
* @param arm_freq desired ARM frequency (Hz)
* @param max_freq desired MAX frequency (Hz)
* @param ip_freq desired IP frequency (Hz)
* @param mask were to return PDR0 mask
* @param value were to return PDR0 value
*
* @return Returns 0 on success or
* Returns non zero if error
* PLL_LESS_ARM_ERR if pll frequency is less than
* desired core frequency
* FREQ_OUT_OF_RANGE if desided frequencies ar not
* possible with the current mcu pll frequency.
*/
static int
cal_pdr0_value(unsigned long mcu_main_clk,
long arm_freq,
long max_freq,
long ip_freq, unsigned long *mask, unsigned long *value)
{
unsigned long arm_div; /* ARM core clock divider */
unsigned long max_div; /* MAX clock divider */
unsigned long ipg_div; /* IPG clock divider */
unsigned long nfc_div; /* NFC (Nand Flash Controller) clock divider */
unsigned long hsp_div; /* HSP clock divider */
if (arm_freq > mcu_main_clk) {
return -PLL_LESS_ARM_ERR;
}
arm_div = mcu_main_clk / arm_freq;
if ((arm_div == 0) || !freq_equal(arm_freq, mcu_main_clk / arm_div)) {
return FREQ_OUT_OF_RANGE;
}
max_div = mcu_main_clk / max_freq;
if ((max_div == 0) || !freq_equal(max_freq, mcu_main_clk / max_div)) {
return FREQ_OUT_OF_RANGE;
}
hsp_div = max_div;
ipg_div = max_freq / ip_freq;
if ((ipg_div == 0) || !freq_equal(ip_freq, max_freq / ipg_div)) {
return FREQ_OUT_OF_RANGE;
}
nfc_div = ((max_freq - 1000000) / NFC_MAX_FREQ) + 1;
/* All of the divider values have been calculated.
* Now change the hardware register. */
*mask = MXC_CCM_PDR0_HSP_PODF_MASK |
MXC_CCM_PDR0_NFC_PODF_MASK |
MXC_CCM_PDR0_IPG_PODF_MASK |
MXC_CCM_PDR0_MAX_PODF_MASK | MXC_CCM_PDR0_MCU_PODF_MASK;
*value = ((hsp_div - 1) << MXC_CCM_PDR0_HSP_PODF_OFFSET) |
((nfc_div - 1) << MXC_CCM_PDR0_NFC_PODF_OFFSET) |
((ipg_div - 1) << MXC_CCM_PDR0_IPG_PODF_OFFSET) |
((max_div - 1) << MXC_CCM_PDR0_MAX_PODF_OFFSET) |
((arm_div - 1) << MXC_CCM_PDR0_MCU_PODF_OFFSET);
return 0;
}
/*!
* Integer clock scaling
*
* Change main arm clock frequencies without changing the PLL.
* The integer dividers are changed to produce the desired
* frequencies. The number of valid frequency are limited and
* are determined by the current MCU PLL frequency
*
* @param arm_freq desired ARM frequency (Hz)
* @param max_freq desired MAX frequency (Hz)
* @param ip_freq desired IP frequency (Hz)
*
* @return Returns 0 on success or
* Returns non zero if error
* PLL_LESS_ARM_ERR if pll frequency is less than
* desired core frequency
* FREQ_OUT_OF_RANGE if desided frequencies ar not
* possible with the current mcu pll frequency.
*/
int mxc_pm_intscale(long arm_freq, long max_freq, long ip_freq)
{
unsigned long mcu_main_clk; /* mcu clock domain main clock */
unsigned long mask;
unsigned long value;
int ret_value;
printk(KERN_INFO "arm_freq=%ld, max_freq=%ld, ip_freq=%ld\n",
arm_freq, max_freq, ip_freq);
//print_frequencies(); /* debug */
mcu_main_clk = clk_get_rate(mcu_pll_clk);
ret_value = cal_pdr0_value(mcu_main_clk, arm_freq, max_freq, ip_freq,
&mask, &value);
if ((arm_freq != clk_round_rate(cpu_clk, arm_freq)) ||
(max_freq != clk_round_rate(ahb_clk, max_freq)) ||
(ip_freq != clk_round_rate(ipg_clk, ip_freq))) {
return -EINVAL;
}
if ((max_freq != clk_get_rate(ahb_clk)) ||
(ip_freq != clk_get_rate(ipg_clk))) {
return -EINVAL;
}
if (arm_freq != clk_get_rate(cpu_clk)) {
ret_value = clk_set_rate(cpu_clk, arm_freq);
}
return ret_value;
}
/*!
* PLL clock scaling
*
* Change MCU PLL frequency and adjust derived clocks. Integer
* dividers are used generate the derived clocks so changed to produce
* the desired the valid frequencies are limited by the desired ARM
* frequency.
*
* The clock source for the MCU is set to the MCU PLL.
*
* @param arm_freq desired ARM frequency (Hz)
* @param max_freq desired MAX frequency (Hz)
* @param ip_freq desired IP frequency (Hz)
*
* @return Returns 0 on success or
* Returns non zero if error
* PLL_LESS_ARM_ERR if pll frequency is less than
* desired core frequency
* FREQ_OUT_OF_RANGE if desided frequencies ar not
* possible with the current mcu pll frequency.
*/
int mxc_pm_pllscale(long arm_freq, long max_freq, long ip_freq)
{
signed long pll_freq = 0; /* target pll frequency */
unsigned long old_pll;
unsigned long mask;
unsigned long value;
int ret_value;
printk(KERN_INFO "arm_freq=%ld, max_freq=%ld, ip_freq=%ld\n",
arm_freq, max_freq, ip_freq);
//print_frequencies();
do {
pll_freq += arm_freq;
if ((pll_freq > MCU_PLL_MAX_FREQ) || (pll_freq / 8 > arm_freq)) {
return FREQ_OUT_OF_RANGE;
}
if (pll_freq < MCU_PLL_MIN_FREQ) {
ret_value = 111;
} else {
ret_value =
cal_pdr0_value(pll_freq, arm_freq, max_freq,
ip_freq, &mask, &value);
}
} while (ret_value != 0);
old_pll = clk_get_rate(mcu_pll_clk);
if (pll_freq > old_pll) {
/* if pll freq is increasing then change dividers first */
mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value);
ret_value = clk_set_rate(mcu_pll_clk, pll_freq);
} else {
/* if pll freq is decreasing then change pll first */
ret_value = clk_set_rate(mcu_pll_clk, pll_freq);
mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value);
}
//print_frequencies();
return ret_value;
}
/*!
* Implementing steps required to transition to low-power modes
*
* @param mode The desired low-power mode. Possible values are,
* WAIT_MODE, DOZE_MODE, STOP_MODE or DSM_MODE
*
*/
void mxc_pm_lowpower(int mode)
{
unsigned int lpm;
int enable_flag;
unsigned long reg;
local_irq_disable();
enable_flag = 0;
switch (mode) {
case STOP_MODE:
/* State Retention mode */
lpm = 2;
/* Disable timer interrupt */
disable_irq(MXC_INT_GPT);
enable_flag = 1;
/* Enable Well Bias and set VSTBY
* VSTBY pin will be asserted during SR mode. This asks the
* PM IC to set the core voltage to the standby voltage
* Must clear the MXC_CCM_CCMR_SBYCS bit as well */
mxc_ccm_modify_reg(MXC_CCM_CCMR,
MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY |
MXC_CCM_CCMR_SBYCS,
MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY |
MXC_CCM_CCMR_SBYCS);
mxc_ccm_modify_reg(MXC_CCM_CCMR,
MXC_CCM_CCMR_LPM_MASK,
lpm << MXC_CCM_CCMR_LPM_OFFSET);
cpu_do_idle();
break;
case DSM_MODE:
/* Deep Sleep Mode */
lpm = 3;
/* Disable timer interrupt */
disable_irq(MXC_INT_GPT);
enable_flag = 1;
/* Enabled Well Bias
* SBYCS = 0, MCU clock source is disabled*/
mxc_ccm_modify_reg(MXC_CCM_CCMR,
MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY |
MXC_CCM_CCMR_SBYCS | MXC_CCM_CCMR_LPM_MASK,
MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY |
MXC_CCM_CCMR_SBYCS |
(lpm << MXC_CCM_CCMR_LPM_OFFSET));
/* wake up by keypad */
reg = __raw_readl(MXC_CCM_WIMR);
reg &= ~(1 << 18);
__raw_writel(reg, MXC_CCM_WIMR);
flush_cache_all();
l2x0_disable();
mxc_pm_arch_entry(IO_ADDRESS(MX31_NFC_BASE_ADDR), 2048);
printk(KERN_INFO "Resume from DSM\n");
l2x0_enable();
mxc_init_irq();
break;
default:
case WAIT_MODE:
/* Wait is the default mode used when idle. */
reg = __raw_readl(MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
__raw_writel(reg, MXC_CCM_CCMR);
break;
}
if (enable_flag) {
/* Enable timer interrupt */
enable_irq(MXC_INT_GPT);
}
local_irq_enable();
}
#ifdef CONFIG_MXC_DVFS
/*!
* Changes MCU frequencies using dvfs.
*
* @param armfreq desired ARM frequency in Hz
* @param ahbfreq desired AHB frequency in Hz
* @param ipfreq desired IP frequency in Hz
*
* @return Returns 0 on success, non-zero on error
*/
int mxc_pm_dvfs(unsigned long armfreq, long ahbfreq, long ipfreq)
{
int ret_value;
int i;
if (ahbfreq != 133000000) {
return FREQ_OUT_OF_RANGE;
}
if (ipfreq != 66500000) {
return FREQ_OUT_OF_RANGE;
}
ret_value = FREQ_OUT_OF_RANGE;
for (i = 0; i < dvfs_states_tbl->num_of_states; i++) {
if (dvfs_states_tbl->freqs[i] == armfreq) {
ret_value = dvfs_set_state(i);
break;
}
}
return ret_value;
}
#endif /* CONFIG_MXC_DVFS */
/*!
* This function is used to load the module.
*
* @return Returns an Integer on success
*/
static int __init mxc_pm_init_module(void)
{
printk(KERN_INFO "Low-Level PM Driver module loaded\n");
mcu_pll_clk = clk_get(NULL, "mcu_pll");
cpu_clk = clk_get(NULL, "cpu_clk");
ahb_clk = clk_get(NULL, "ahb_clk");
ipg_clk = clk_get(NULL, "ipg_clk");
return 0;
}
/*!
* This function is used to unload the module
*/
static void __exit mxc_pm_cleanup_module(void)
{
clk_put(mcu_pll_clk);
clk_put(cpu_clk);
clk_put(ahb_clk);
clk_put(ipg_clk);
printk(KERN_INFO "Low-Level PM Driver module Unloaded\n");
}
module_init(mxc_pm_init_module);
module_exit(mxc_pm_cleanup_module);
EXPORT_SYMBOL(mxc_pm_intscale);
EXPORT_SYMBOL(mxc_pm_pllscale);
EXPORT_SYMBOL(mxc_pm_lowpower);
#ifdef CONFIG_MXC_DVFS
EXPORT_SYMBOL(mxc_pm_dvfs);
#endif
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("MX3 Low-level Power Management Driver");
MODULE_LICENSE("GPL");

103
arch/arm/mach-mx3/pm.c Normal file
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/*
* linux/arch/arm/mach-mx3/pm.c
*
* MX3 Power Management Routines
*
* Original code for the SA11x0:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Modified for the PXA250 by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* Modified for the OMAP1510 by David Singleton:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
*
* Modified for the MX31
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/suspend.h>
#include <linux/regulator/machine.h>
#include <mach/mxc_pm.h>
/*
* TODO: whatta save?
*/
static int mx31_suspend_enter(suspend_state_t state)
{
printk(KERN_INFO "Hi, from mx31_pm_enter\n");
switch (state) {
case PM_SUSPEND_MEM:
mxc_pm_lowpower(DSM_MODE);
break;
case PM_SUSPEND_STANDBY:
mxc_pm_lowpower(STOP_MODE);
break;
default:
return -1;
}
return 0;
}
/*
* Called after processes are frozen, but before we shut down devices.
*/
static int mx31_suspend_prepare(void)
{
return 0;
}
/*
* Called after devices are re-setup, but before processes are thawed.
*/
static void mx31_suspend_finish(void)
{
return;
}
static int mx31_pm_valid(suspend_state_t state)
{
return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
}
struct platform_suspend_ops mx31_suspend_ops = {
.valid = mx31_pm_valid,
.prepare = mx31_suspend_prepare,
.enter = mx31_suspend_enter,
.finish = mx31_suspend_finish,
};
static int __init mx31_pm_init(void)
{
printk(KERN_INFO "Power Management for Freescale MX31\n");
suspend_set_ops(&mx31_suspend_ops);
return 0;
}
late_initcall(mx31_pm_init);

581
arch/arm/mach-mx3/sdma_script_code.h Normal file
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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __SDMA_SCRIPT_CODE_H__
#define __SDMA_SCRIPT_CODE_H__
/*!
* Following define start address of start script
*/
#define start_ADDR 0
/*!
* Following define size of start script
*/
#define start_SIZE 21
/*!
* Following define start address of core script
*/
#define core_ADDR 80
/*!
* Following define size of core script
*/
#define core_SIZE 152
/*!
* Following define start address of common script
*/
#define common_ADDR 232
/*!
* Following define size of common script
*/
#define common_SIZE 191
/*!
* Following define start address of burst_copy script
*/
#define burst_copy_ADDR 423
/*!
* Following define size of burst_copy script
*/
#define burst_copy_SIZE 87
/*!
* Following define start address of dsp_2_burst script
*/
#define dsp_2_burst_ADDR 510
/*!
* Following define size of dsp_2_burst script
*/
#define dsp_2_burst_SIZE 24
/*!
* Following define start address of burst_2_dsp script
*/
#define burst_2_dsp_ADDR 534
/*!
* Following define size of burst_2_dsp script
*/
#define burst_2_dsp_SIZE 24
/*!
* Following define start address of dsp_copy script
*/
#define dsp_copy_ADDR 558
/*!
* Following define size of dsp_copy script
*/
#define dsp_copy_SIZE 86
/*!
* Following define start address of mcu_2_mcu script
*/
#define mcu_2_mcu_ADDR 644
/*!
* Following define size of mcu_2_mcu script
*/
#define mcu_2_mcu_SIZE 79
/*!
* Following define start address of mcu_2_per script
*/
#define mcu_2_per_ADDR 723
/*!
* Following define size of mcu_2_per script
*/
#define mcu_2_per_SIZE 88
/*!
* Following define start address of test script
*/
#define test_ADDR 811
/*!
* Following define size of test script
*/
#define test_SIZE 63
/*!
* Following define start address of mcu_2_dsp script
*/
#define mcu_2_dsp_ADDR 874
/*!
* Following define size of mcu_2_dsp script
*/
#define mcu_2_dsp_SIZE 30
/*!
* Following define start address of mcu_2_dsp_2buf script
*/
#define mcu_2_dsp_2buf_ADDR 904
/*!
* Following define size of mcu_2_dsp_2buf script
*/
#define mcu_2_dsp_2buf_SIZE 113
/*!
* Following define start address of dsp_2_mcu script
*/
#define dsp_2_mcu_ADDR 1017
/*!
* Following define size of dsp_2_mcu script
*/
#define dsp_2_mcu_SIZE 30
/*!
* Following define start address of dsp_2_mcu_2buf script
*/
#define dsp_2_mcu_2buf_ADDR 1047
/*!
* Following define size of dsp_2_mcu_2buf script
*/
#define dsp_2_mcu_2buf_SIZE 113
/*!
* Following define start address of dsp_2_dsp script
*/
#define dsp_2_dsp_ADDR 1160
/*!
* Following define size of dsp_2_dsp script
*/
#define dsp_2_dsp_SIZE 64
/*!
* Following define start address of per_2_mcu script
*/
#define per_2_mcu_ADDR 1224
/*!
* Following define size of per_2_mcu script
*/
#define per_2_mcu_SIZE 121
/*!
* Following define start address of dsp_2_per_2buf script
*/
#define dsp_2_per_2buf_ADDR 1345
/*!
* Following define size of dsp_2_per_2buf script
*/
#define dsp_2_per_2buf_SIZE 164
/*!
* Following define start address of per_2_dsp_2buf script
*/
#define per_2_dsp_2buf_ADDR 1509
/*!
* Following define size of per_2_dsp_2buf script
*/
#define per_2_dsp_2buf_SIZE 168
/*!
* Following define start address of per_2_per script
*/
#define per_2_per_ADDR 1677
/*!
* Following define size of per_2_per script
*/
#define per_2_per_SIZE 67
/*!
* Following define start address of error_dsp script
*/
#define error_dsp_ADDR 1744
/*!
* Following define size of error_dsp script
*/
#define error_dsp_SIZE 34
/*!
* Following define start address of ap_2_ap script
*/
#define ap_2_ap_ADDR 6144
/*!
* Following define size of ap_2_ap script
*/
#define ap_2_ap_SIZE 294
/*!
* Following define start address of app_2_mcu script
*/
#define app_2_mcu_ADDR 6438
/*!
* Following define size of app_2_mcu script
*/
#define app_2_mcu_SIZE 101
/*!
* Following define start address of ata_2_mcu script
*/
#define ata_2_mcu_ADDR 6539
/*!
* Following define size of ata_2_mcu script
*/
#define ata_2_mcu_SIZE 110
/*!
* Following define start address of dptc_dvfs script
*/
#define dptc_dvfs_ADDR 6649
/*!
* Following define size of dptc_dvfs script
*/
#define dptc_dvfs_SIZE 274
/*!
* Following define start address of error script
*/
#define error_ADDR 6923
/*!
* Following define size of error script
*/
#define error_SIZE 73
/*!
* Following define start address of firi_2_mcu script
*/
#define firi_2_mcu_ADDR 6996
/*!
* Following define size of firi_2_mcu script
*/
#define firi_2_mcu_SIZE 114
/*!
* Following define start address of mcu_2_app script
*/
#define mcu_2_app_ADDR 7110
/*!
* Following define size of mcu_2_app script
*/
#define mcu_2_app_SIZE 127
/*!
* Following define start address of mcu_2_ata script
*/
#define mcu_2_ata_ADDR 7237
/*!
* Following define size of mcu_2_ata script
*/
#define mcu_2_ata_SIZE 87
/*!
* Following define start address of mcu_2_firi script
*/
#define mcu_2_firi_ADDR 7324
/*!
* Following define size of mcu_2_firi script
*/
#define mcu_2_firi_SIZE 77
/*!
* Following define start address of mcu_2_mshc script
*/
#define mcu_2_mshc_ADDR 7401
/*!
* Following define size of mcu_2_mshc script
*/
#define mcu_2_mshc_SIZE 48
/*!
* Following define start address of mcu_2_shp script
*/
#define mcu_2_shp_ADDR 7449
/*!
* Following define size of mcu_2_shp script
*/
#define mcu_2_shp_SIZE 123
/*!
* Following define start address of mshc_2_mcu script
*/
#define mshc_2_mcu_ADDR 7572
/*!
* Following define size of mshc_2_mcu script
*/
#define mshc_2_mcu_SIZE 60
/*!
* Following define start address of shp_2_mcu script
*/
#define shp_2_mcu_ADDR 7632
/*!
* Following define size of shp_2_mcu script
*/
#define shp_2_mcu_SIZE 101
/*!
* Following define start address of uart_2_mcu script
*/
#define uart_2_mcu_ADDR 7733
/*!
* Following define size of uart_2_mcu script
*/
#define uart_2_mcu_SIZE 105
/*!
* Following define start address of uartsh_2_mcu script
*/
#define uartsh_2_mcu_ADDR 7838
/*!
* Following define size of uartsh_2_mcu script
*/
#define uartsh_2_mcu_SIZE 98
/*!
* Following define the start address of sdma ram
*/
#define RAM_CODE_START_ADDR 6144
/*!
* Following define the size of sdma ram
*/
#define RAM_CODE_SIZE 1792
/*!
* This function returns buffer that holds the image of SDMA RAM.
* This is required to start on a 4-byte aligned boundary on some platforms
* for SDMA to work properly.
*
* @return pointer to buffer that holds the image of SDMA RAM
*/
__attribute__ ((__aligned__(4)))
#ifndef CONFIG_XIP_KERNEL
const
#endif
static short sdma_code[] = {
0xc0ec, 0x7d59, 0x0970, 0x0111, 0x5111, 0x5ad1, 0x5bd9, 0xc0fe,
0x5ce1, 0x7d02, 0x0200, 0x9806, 0x08ff, 0x0011, 0x28ff, 0x00bc,
0x05df, 0x7d4b, 0x06df, 0x7d2f, 0x6dc5, 0x6ed5, 0x5ef1, 0x0288,
0xd81a, 0x9854, 0x0b04, 0x00d3, 0x7d20, 0x06a5, 0x3e03, 0x3d03,
0x03a5, 0x3b03, 0x008b, 0x058b, 0x7802, 0x63d8, 0x0000, 0x7e72,
0x63ff, 0x7e70, 0x02a5, 0x008a, 0x4e00, 0x7d01, 0x983d, 0x6dcf,
0x6edf, 0x0015, 0x0015, 0x7802, 0x63d8, 0x0000, 0x7e63, 0x63ff,
0x7e61, 0x3a03, 0x008a, 0x6dcd, 0x6edd, 0x7801, 0x63d8, 0x7e5a,
0x63ff, 0x7e58, 0x0006, 0x6dc5, 0x6e07, 0x5ef1, 0x0288, 0xd8f7,
0x7e02, 0x7f04, 0x9854, 0x0007, 0x68cc, 0x6b28, 0x54e1, 0x0089,
0xdb13, 0x0188, 0x5ce1, 0x9854, 0x52d1, 0x53d9, 0x54e1, 0xc10d,
0x7dad, 0x0200, 0x9800, 0x0200, 0x9800, 0x06df, 0x7d06, 0x6d23,
0x6ed5, 0x5ef1, 0x0288, 0xd8cd, 0x9854, 0x5ef1, 0x6e07, 0x6d03,
0x0b04, 0x00d3, 0x7d59, 0x06a5, 0x3e03, 0x3d03, 0x4d00, 0x7d09,
0x03a5, 0x00a3, 0x0588, 0x008b, 0xd8c9, 0x7ed8, 0x620c, 0x7ed6,
0x008d, 0x4e00, 0x7c25, 0x0a20, 0x00da, 0x7c22, 0x6503, 0x3d1f,
0x02a5, 0x00a2, 0x0215, 0x0215, 0x6a18, 0x6a28, 0x7fc7, 0x0a20,
0x0b08, 0x00da, 0x7c06, 0x6b18, 0x6b28, 0x7fc0, 0x0000, 0x2020,
0x9889, 0x0688, 0x0015, 0x0015, 0x6818, 0x6828, 0x7fb7, 0x98c2,
0x0007, 0x6a0c, 0x54e1, 0x0089, 0xdb0f, 0x0188, 0x5ce1, 0x9854,
0x0b04, 0x00d3, 0x7d21, 0x0389, 0x1b12, 0x048b, 0x0688, 0x0015,
0x0015, 0x0588, 0x038c, 0x0a08, 0x05da, 0x008d, 0x7c01, 0x008a,
0x05a0, 0x7803, 0x620b, 0x5a03, 0x1b01, 0x7e98, 0x008b, 0x00a4,
0x038c, 0x7803, 0x5203, 0x6a0b, 0x1b01, 0x6a28, 0x7f8f, 0x0000,
0x4d00, 0x7ce8, 0x008e, 0x3803, 0xd8c9, 0x7e88, 0x620c, 0x7e86,
0x9854, 0x7802, 0x6209, 0x6a29, 0x0006, 0x3e03, 0x4e00, 0x7d11,
0x0b04, 0x03a6, 0x02db, 0x7d01, 0x038a, 0x02a3, 0x048a, 0x008b,
0x7802, 0x6329, 0x6bc8, 0x7ebc, 0x63c8, 0x7ebc, 0x008c, 0x4800,
0x7d15, 0x0488, 0x0015, 0x0015, 0x6edf, 0x7803, 0x632b, 0x6bc8,
0x0000, 0x7eae, 0x63c8, 0x7eae, 0x008c, 0x3803, 0x6edd, 0x7803,
0x6329, 0x6bc8, 0x0000, 0x7ea4, 0x63c8, 0x7ea4, 0x0006, 0x3d03,
0x4d00, 0x7d0e, 0x0b04, 0x03a5, 0x02db, 0x7d01, 0x038a, 0x02a3,
0x048a, 0x008b, 0x7802, 0x63c8, 0x6b09, 0x7e1e, 0x7f1e, 0x008c,
0x0488, 0x0015, 0x0015, 0x6dcf, 0x0288, 0x008a, 0x0d08, 0x02dd,
0x7c01, 0x008d, 0x7802, 0x63c8, 0x6b0b, 0x7e0e, 0x6b28, 0x7f0d,
0x0000, 0x02dd, 0x7c02, 0x2208, 0x990d, 0x008c, 0x3803, 0x65c0,
0x6dc5, 0x7802, 0x63c8, 0x6b09, 0x6b28, 0x0006, 0x0870, 0x0011,
0x5010, 0xc0ec, 0x7d5e, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
0x7d02, 0x0200, 0x992c, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511,
0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0b70, 0x0311, 0x522b, 0x5313,
0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, 0x993c, 0x008f,
0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210,
0x4a00, 0x7d1c, 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311,
0x53eb, 0x62c8, 0x7e24, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09,
0x7f1e, 0x0212, 0x6a09, 0x7f1b, 0x0212, 0x6a09, 0x7f18, 0x2003,
0x4800, 0x7cef, 0x0b70, 0x0311, 0x5313, 0x997d, 0x0015, 0x0015,
0x7802, 0x62c8, 0x6a0b, 0x997c, 0x0015, 0x7802, 0x62c8, 0x6a0a,
0x997c, 0x7802, 0x62c8, 0x6a09, 0x7c02, 0x0000, 0x993a, 0xdb13,
0x6a28, 0x7ffd, 0x008b, 0x52c3, 0x53cb, 0xc10d, 0x7da5, 0x0200,
0x992c, 0x0200, 0x9929, 0xc19d, 0xc0ec, 0x7d69, 0x0c70, 0x0411,
0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02,
0x0200, 0x9994, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff,
0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, 0x0211, 0x552a,
0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9, 0x4d00, 0x7c13,
0x6928, 0x7f2d, 0x0400, 0x99a5, 0x008f, 0x0015, 0x04d8, 0x7d01,
0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e29, 0x6d28,
0x7f1e, 0x0000, 0x99a3, 0x1e20, 0x5506, 0x2620, 0x008d, 0x0560,
0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a, 0x7f10, 0x4c00,
0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802,
0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000, 0x99ec, 0x0007,
0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28, 0x0007, 0x680c,
0x0007, 0x54d2, 0x0454, 0x99ef, 0x6928, 0x7ff1, 0x54d2, 0x008a,
0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200, 0x9994, 0x0200,
0x998c, 0xc0ec, 0x7d72, 0x0800, 0x0970, 0x0111, 0x5111, 0x5ac1,
0x5bc9, 0x028e, 0xc0fe, 0x068a, 0x7c6a, 0x5dd9, 0x5ce1, 0x0bff,
0x0311, 0x1bff, 0x03bc, 0x5bd1, 0x1a5c, 0x6ac3, 0x63c8, 0x0363,
0x7c05, 0x036f, 0x7d27, 0x0374, 0x7c7a, 0x9a71, 0xdb04, 0x3c06,
0x4c00, 0x7df7, 0x028f, 0x1a04, 0x6a23, 0x620b, 0x6f23, 0x301f,
0x00aa, 0x0462, 0x7c04, 0x4a00, 0x7d0b, 0x2001, 0x9a30, 0x048a,
0x620b, 0x2201, 0x1c01, 0x1801, 0x02dc, 0x7d02, 0x301f, 0x00aa,
0x048f, 0x1c04, 0x6c07, 0x0488, 0x3c1f, 0x6c2b, 0x0045, 0x028e,
0x1a5c, 0x9a11, 0x058f, 0x1d0c, 0x6d23, 0x650b, 0x007d, 0x7c01,
0x1d08, 0x007c, 0x7c01, 0x1d04, 0x6d23, 0x650b, 0x0488, 0x3c1f,
0x0417, 0x0417, 0x0417, 0x0417, 0x059c, 0x6d23, 0x028e, 0x1a34,
0x6ad7, 0x0488, 0x0804, 0x7802, 0x650b, 0x6dc8, 0x008c, 0x1a28,
0x6ad7, 0x63c8, 0x034c, 0x6bc8, 0x54d1, 0x4c00, 0x7d06, 0x0065,
0x7c02, 0x0101, 0x0025, 0x0400, 0x9a0d, 0x52c1, 0x53c9, 0x54e1,
0x0453, 0xc10d, 0x7d95, 0x0200, 0x9a00, 0x0200, 0x99f9, 0x0200,
0x9a00, 0x55d9, 0x6d07, 0x54d1, 0x058a, 0x2508, 0x6dc7, 0x0373,
0x7c03, 0x65c8, 0x6d0b, 0x2408, 0x0372, 0x7c04, 0x65c8, 0x6d0b,
0x2408, 0x9a86, 0x6cce, 0x65c8, 0x6d0a, 0x2404, 0x6d28, 0x6507,
0x5dd9, 0x5cd1, 0x6ad7, 0x6ae3, 0x63c8, 0x0334, 0x6bc8, 0x0370,
0x7ca9, 0x0c60, 0x0411, 0x04bb, 0x4c00, 0x7da4, 0x0410, 0x1c30,
0x0410, 0x04bb, 0x046d, 0x7d0a, 0x047d, 0x7c03, 0x047c, 0x7c01,
0x9a3a, 0x003b, 0x003a, 0x0039, 0x0058, 0x9ab5, 0x047d, 0x7d03,
0x047c, 0x7d01, 0x9a3a, 0x005b, 0xdaf9, 0x1d18, 0x6d23, 0x650b,
0x0510, 0x003a, 0x0039, 0x0038, 0x00ad, 0xdb04, 0x0c30, 0x0410,
0x04bb, 0x003c, 0x003d, 0x00ac, 0xdaf9, 0x007b, 0x7c04, 0x003d,
0x003c, 0x1d0c, 0x9ad6, 0x048f, 0x1c14, 0x6c23, 0x640b, 0x4401,
0x7d04, 0x005d, 0x005c, 0x1d0c, 0x9ad6, 0x0310, 0x3b30, 0x4b30,
0x7d01, 0x1b10, 0x0310, 0x003d, 0x003c, 0x00ab, 0x6ad7, 0x63c8,
0x6d23, 0x650b, 0x0560, 0x7d03, 0x005e, 0xdaed, 0x9a3a, 0x003e,
0x0c80, 0x0410, 0x0394, 0xdaed, 0x640b, 0x037f, 0x7d02, 0x1a14,
0x9aea, 0x1a0c, 0x6ad7, 0x6cc8, 0x9a3a, 0x0c7f, 0x0410, 0x03b4,
0x04b8, 0x03ac, 0x640b, 0x6bc8, 0x028e, 0x1a04, 0x6ad7, 0x6cc8,
0x0006, 0x058f, 0x1d08, 0x6d23, 0x650b, 0x007d, 0x7c01, 0x1d38,
0x007c, 0x7c01, 0x1d1c, 0x0006, 0x048b, 0x042c, 0x0454, 0x042b,
0x6ad7, 0x6cc8, 0x0006, 0x0007, 0x684c, 0x6144, 0x9b1c, 0x0007,
0x68cc, 0x61d0, 0x9b1c, 0x0007, 0x680c, 0x680c, 0x6107, 0x6907,
0x692b, 0x6928, 0x0007, 0x680c, 0x0d70, 0x0511, 0x5515, 0x55f5,
0x01a5, 0x0dff, 0x0512, 0x1dff, 0x0512, 0x04bd, 0x0499, 0x0454,
0x0006, 0x08ff, 0x0011, 0x28ff, 0x0006, 0x038c, 0x0eff, 0x0611,
0x2eff, 0x03b6, 0x0006, 0x53d6, 0x0398, 0x5bd6, 0x53ee, 0x0398,
0x5bee, 0x0006, 0x52de, 0x53e6, 0x54ee, 0x0498, 0x0454, 0x0006,
0x50f6, 0x52c6, 0x53ce, 0x54d6, 0x0498, 0x0454, 0x0006, 0x6207,
0x0b70, 0x0311, 0x5013, 0x55f0, 0x02a5, 0x0bff, 0x0312, 0x1bff,
0x0312, 0x04bb, 0x049a, 0x0006, 0x1e10, 0x0870, 0x0011, 0x5010,
0xc0ec, 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
0x0200, 0x9b5b, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70,
0x0311, 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9b6a, 0x0212,
0x3aff, 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8,
0xdba5, 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xdbbd, 0x52c0,
0x53c8, 0xc10d, 0x7dd0, 0x0200, 0x9b5b, 0x008f, 0x00d5, 0x7d01,
0x008d, 0xdba5, 0x9b68, 0x0200, 0x9b58, 0x0007, 0x68cc, 0x6a28,
0x7f01, 0x9ba3, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b,
0x6a28, 0x0007, 0x680c, 0x0454, 0x9b81, 0x05a0, 0x1e08, 0x6ec3,
0x0388, 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5,
0x6a28, 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09,
0x7edc, 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5,
0x0dff, 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0870, 0x0011,
0x5010, 0xc0ec, 0x7d78, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
0x7d02, 0x0200, 0x9bcc, 0x6d03, 0x6ed3, 0x0dff, 0x0511, 0x1dff,
0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b, 0x5313,
0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9bdc, 0x008f,
0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc,
0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a,
0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25, 0x620a,
0x7e23, 0x9c06, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512,
0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70, 0x0311,
0x5313, 0x9c21, 0x7802, 0x6209, 0x6ac8, 0x9c20, 0x0015, 0x7802,
0x620a, 0x6ac8, 0x9c20, 0x0015, 0x0015, 0x7802, 0x620b, 0x6ac8,
0x7c03, 0x0000, 0x55db, 0x9bda, 0x0007, 0x68cc, 0x680c, 0x55d3,
0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9c2f, 0x0017, 0x0017, 0x55db,
0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8,
0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x008b, 0x52c0, 0x53c8, 0xc10d,
0x7d8b, 0x0200, 0x9bcc, 0x0200, 0x9bc9, 0xc19d, 0xc0ec, 0x7d52,
0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe,
0x56fa, 0x7d02, 0x0200, 0x9c4e, 0x6d03, 0x5bca, 0x5cd2, 0x0bff,
0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x0a70, 0x0211, 0x4c00,
0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02, 0x0400, 0x9c61, 0x4c01,
0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01, 0x008c, 0x0020, 0x04a0,
0x0015, 0x7802, 0x650b, 0x5d06, 0x0000, 0x7e0c, 0x7f0d, 0x9c5f,
0x650a, 0x7e08, 0x008d, 0x0011, 0x0010, 0x05a8, 0x065f, 0x5d06,
0x063f, 0x7f02, 0x0007, 0x680c, 0x0007, 0x5012, 0x54d0, 0x0454,
0x9c8b, 0x5012, 0x54d0, 0x0473, 0x7c06, 0x552a, 0x05b9, 0x4d00,
0x7c02, 0x0400, 0x9c8d, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7db6,
0x0200, 0x9c4e, 0x0200, 0x9c46, 0x0870, 0x0011, 0x5010, 0xc0ec,
0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x9ca2, 0x0b70, 0x0311, 0x6ed3, 0x6d03, 0x0dff, 0x0511, 0x1dff,
0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x62c8,
0x7e1f, 0x0400, 0x9cb3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0,
0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16, 0x6ac8, 0x7f11, 0x0015,
0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e, 0x6ac8, 0x7f09, 0x6edf,
0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000, 0x7e05, 0x7f01, 0x9cb1,
0x0007, 0x68cc, 0x9cdd, 0x0007, 0x6a0c, 0x0454, 0x62c8, 0x7ef8,
0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd, 0x0200, 0x9ca2, 0x0200,
0x9c9f, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d29, 0x5010, 0x5ac0,
0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9cf0, 0x0870, 0x0011,
0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d12, 0x5228,
0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9cff, 0x620b, 0x7e06, 0x5a06,
0x7f06, 0x0000, 0x2504, 0x7d05, 0x9cff, 0x0007, 0x680c, 0x0007,
0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb, 0x0200, 0x9cf0, 0x0200,
0x9cec, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d74, 0x5010, 0x5ac0,
0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9d20, 0x6d03,
0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff,
0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70, 0x0211, 0x532a, 0x5212,
0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9d34, 0x008f, 0x05d8, 0x7d01,
0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d27, 0x4d02, 0x7d20,
0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea, 0x0260, 0x7d05, 0x6509,
0x7e25, 0x630a, 0x7e23, 0x9d58, 0x630a, 0x7e20, 0x6509, 0x7e1e,
0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19, 0x2003, 0x4800, 0x7ced,
0x0a70, 0x0211, 0x5212, 0x9d73, 0x7802, 0x6309, 0x5b06, 0x9d72,
0x0015, 0x7802, 0x630a, 0x5b06, 0x9d72, 0x0015, 0x0015, 0x7802,
0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000, 0x9d32, 0x0007, 0x680c,
0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9d80, 0x0017, 0x0017,
0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010,
0x04b8, 0x04ad, 0x0454, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x7d90,
0x0200, 0x9d20, 0x0200, 0x9d1c, 0xc19d, 0x0870, 0x0011, 0xc0ec,
0x7d35, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x9d9b, 0x0870, 0x0011, 0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d1c, 0x5228, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b,
0x0400, 0x9daa, 0x5206, 0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000,
0x2504, 0x7d0c, 0x9daa, 0x0007, 0x680c, 0x680c, 0x6207, 0x6a07,
0x6a2b, 0x6a28, 0x0007, 0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3,
0x5010, 0x52c0, 0xc10d, 0x7dcf, 0x0200, 0x9d9b, 0x0200, 0x9d97,
0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d5e, 0x5010, 0x5ac0, 0x5bc8,
0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9dd7, 0x6d07, 0x5df0,
0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0a70, 0x0211,
0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, 0x6a28, 0x7f3a, 0x0400,
0x9de6, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312,
0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, 0x7d20, 0x4b01, 0x7d23,
0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e24, 0x0260, 0x7d02, 0x0310,
0x0312, 0x6b09, 0x7f1e, 0x0312, 0x6b09, 0x7f1b, 0x0312, 0x6b09,
0x7f18, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9e27,
0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, 0x9e26, 0x0015, 0x7802,
0x5306, 0x6b0a, 0x9e26, 0x7802, 0x5306, 0x6b09, 0x7c02, 0x0000,
0x9de4, 0xdb13, 0x6928, 0x7ffd, 0x008a, 0x52c0, 0x53c8, 0xc10d,
0x7da6, 0x0200, 0x9dd7, 0x0200, 0x9dd3, 0x0870, 0x0011, 0x5010,
0xc0ec, 0x7d5b, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
0x0200, 0x9e3b, 0x0b70, 0x0311, 0x6ec3, 0x6d07, 0x5df0, 0x0dff,
0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3d, 0x522b, 0x02b9, 0x4a00,
0x7c04, 0x6a28, 0x7f33, 0x0400, 0x9e4d, 0x028e, 0x1a94, 0x6ac3,
0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, 0x6ed3, 0x62c8, 0x0248,
0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, 0x7d31, 0x6a09, 0x7f1e,
0x2501, 0x4d00, 0x7d1f, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3,
0x0260, 0x7df1, 0x6a28, 0x7f12, 0xdb47, 0x9e8c, 0x6ee3, 0x008f,
0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d17,
0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9e4b, 0x0289, 0xdb13,
0x018a, 0x9e9b, 0x6a28, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0,
0x53c8, 0xc10d, 0x7da8, 0x0200, 0x9e3b, 0x0200, 0x9e38, 0x6a28,
0x7fed, 0xdb47, 0x9e9b, 0x0458, 0x0454, 0x9e8c, 0xc19d, 0x0870,
0x0011, 0xc0ec, 0x7d54, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
0x56f8, 0x7d02, 0x0200, 0x9ea5, 0x0b70, 0x0311, 0x6d07, 0x5df0,
0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d36, 0x522b, 0x02b9,
0x4a00, 0x7c04, 0x6928, 0x7f2c, 0x0400, 0x9eb6, 0x028e, 0x1a94,
0x5202, 0x0269, 0x7d16, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694,
0x5206, 0x026e, 0x7d2e, 0x6a09, 0x7f1b, 0x2501, 0x4d00, 0x7d1c,
0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6a28, 0x7f11, 0xdb47,
0x9eee, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206,
0x026e, 0x7d17, 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9eb4,
0x0289, 0xdb13, 0x018a, 0x9efd, 0x6928, 0x7ffa, 0x0b70, 0x0311,
0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7db0, 0x0200, 0x9ea5, 0x0200,
0x9ea1, 0x6a28, 0x7fed, 0xdb47, 0x9efd, 0x0458, 0x0454, 0x9eee,
0x9eee
};
#endif

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arch/arm/mach-mx3/sdma_script_code_pass2.h Normal file
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/*
* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
/*!
* @file sdma_script_code.h
* @brief This file contains functions of SDMA scripts code initialization
*
* The file was generated automatically. Based on sdma scripts library.
*
* @ingroup SDMA
*/
/*******************************************************************************
SDMA RELEASE LABEL: "SS15_MX31"
*******************************************************************************/
#ifndef __SDMA_SCRIPT_CODE_PASS2_H__
#define __SDMA_SCRIPT_CODE_PASS2_H__
/*!
* SDMA ROM scripts start addresses and sizes
*/
#define start_ADDR_2 0
#define start_SIZE_2 20
#define core_ADDR_2 80
#define core_SIZE_2 152
#define common_ADDR_2 232
#define common_SIZE_2 191
#define ap_2_ap_ADDR_2 423
#define ap_2_ap_SIZE_2 294
#define bp_2_bp_ADDR_2 717
#define bp_2_bp_SIZE_2 112
#define ap_2_bp_ADDR_2 829
#define ap_2_bp_SIZE_2 200
#define bp_2_ap_ADDR_2 1029
#define bp_2_ap_SIZE_2 223
#define app_2_mcu_ADDR_2 1252
#define app_2_mcu_SIZE_2 101
#define mcu_2_app_ADDR_2 1353
#define mcu_2_app_SIZE_2 127
#define uart_2_mcu_ADDR_2 1480
#define uart_2_mcu_SIZE_2 105
#define uartsh_2_mcu_ADDR_2 1585
#define uartsh_2_mcu_SIZE_2 98
#define mcu_2_shp_ADDR_2 1683
#define mcu_2_shp_SIZE_2 123
#define shp_2_mcu_ADDR_2 1806
#define shp_2_mcu_SIZE_2 101
#define error_ADDR_2 1907
#define error_SIZE_2 73
#define test_ADDR_2 1980
#define test_SIZE_2 63
#define signature_ADDR_2 1023
#define signature_SIZE_2 1
/*!
* SDMA RAM scripts start addresses and sizes
*/
#define ap_2_ap_fixed_addr_ADDR_2 6144
#define ap_2_ap_fixed_addr_SIZE_2 68
#define app_2_mcu_patched_ADDR_2 6212
#define app_2_mcu_patched_SIZE_2 104
#undef app_2_mcu_ADDR_2
#undef app_2_mcu_SIZE_2
/*mapping the app_2_mcu start address to the patched(RAM)script start address*/
#define app_2_mcu_ADDR_2 app_2_mcu_patched_ADDR_2
#define app_2_mcu_SIZE_2 app_2_mcu_patched_SIZE_2
#define app_2_per_ADDR_2 6316
#define app_2_per_SIZE_2 105
#define ata_2_mcu_ADDR_2 6421
#define ata_2_mcu_SIZE_2 110
#define firi_2_mcu_ADDR_2 6531
#define firi_2_mcu_SIZE_2 114
#define loop_DMAs_fixed_addr_ADDR_2 6645
#define loop_DMAs_fixed_addr_SIZE_2 90
#define mcu_2_app_patched_ADDR_2 6735
#define mcu_2_app_patched_SIZE_2 129
#undef mcu_2_app_ADDR_2
#undef mcu_2_app_SIZE_2
/*mapping the mcu_2_app start address to the patched(RAM)script start address*/
#define mcu_2_app_ADDR_2 mcu_2_app_patched_ADDR_2
#define mcu_2_app_SIZE_2 mcu_2_app_patched_SIZE_2
#define mcu_2_ata_ADDR_2 6864
#define mcu_2_ata_SIZE_2 87
#define mcu_2_firi_ADDR_2 6951
#define mcu_2_firi_SIZE_2 77
#define mcu_2_mshc_ADDR_2 7028
#define mcu_2_mshc_SIZE_2 48
#define mcu_2_shp_patched_ADDR_2 7076
#define mcu_2_shp_patched_SIZE_2 125
#undef mcu_2_shp_ADDR_2
#undef mcu_2_shp_SIZE_2
/*mapping the mcu_2_shp start address to the patched(RAM)script start address*/
#define mcu_2_shp_ADDR_2 mcu_2_shp_patched_ADDR_2
#define mcu_2_shp_SIZE_2 mcu_2_shp_patched_SIZE_2
#define mshc_2_mcu_ADDR_2 7201
#define mshc_2_mcu_SIZE_2 60
#define per_2_app_ADDR_2 7261
#define per_2_app_SIZE_2 131
#define per_2_shp_ADDR_2 7392
#define per_2_shp_SIZE_2 131
#define shp_2_mcu_patched_ADDR_2 7523
#define shp_2_mcu_patched_SIZE_2 104
#undef shp_2_mcu_ADDR_2
#undef shp_2_mcu_SIZE_2
/*mapping the shp_2_mcu start address to the patched(RAM)script start address*/
#define shp_2_mcu_ADDR_2 shp_2_mcu_patched_ADDR_2
#define shp_2_mcu_SIZE_2 shp_2_mcu_patched_SIZE_2
#define shp_2_per_ADDR_2 7627
#define shp_2_per_SIZE_2 109
#define uart_2_mcu_patched_ADDR_2 7736
#define uart_2_mcu_patched_SIZE_2 106
#undef uart_2_mcu_ADDR_2
#undef uart_2_mcu_SIZE_2
/*mapping the uart_2_mcu start address to the patched(RAM)script start address*/
#define uart_2_mcu_ADDR_2 uart_2_mcu_patched_ADDR_2
#define uart_2_mcu_SIZE_2 uart_2_mcu_patched_SIZE_2
#define uartsh_2_mcu_patched_ADDR_2 7842
#define uartsh_2_mcu_patched_SIZE_2 99
#undef uartsh_2_mcu_ADDR_2
#undef uartsh_2_mcu_SIZE_2
/*
* mapping the uartsh_2_mcu start address to the patched(RAM)script
* start address
*/
#define uartsh_2_mcu_ADDR_2 uartsh_2_mcu_patched_ADDR_2
#define uartsh_2_mcu_SIZE_2 uartsh_2_mcu_patched_SIZE_2
/*!
* SDMA RAM image start address and size
*/
#define RAM_CODE_START_ADDR_2 6144
#define RAM_CODE_SIZE_2 1797
/*!
* Buffer that holds the SDMA RAM image
*/
__attribute__ ((__aligned__(4)))
#ifndef CONFIG_XIP_KERNEL
const
#endif
static const short sdma_code_2[] = {
0x0970, 0x0111, 0x5111, 0x5ef9, 0xc0ec, 0x7d23, 0x5ad1, 0x5bd9,
0xc0fe, 0x7c1f, 0x5ce1, 0x5de9, 0x5ef1, 0x08ff, 0x0011, 0x28ff,
0x00bc, 0x048e, 0x56f9, 0x0660, 0x7d05, 0x0661, 0x7c2b, 0x6c07,
0x6d13, 0x9821, 0x0661, 0x7d26, 0x6c17, 0x6d03, 0x028d, 0x058c,
0x048a, 0xd9f5, 0x7e08, 0x7f07, 0x54e1, 0x52d1, 0x53d9, 0xc10d,
0x7dde, 0x0200, 0x9804, 0x0660, 0x7d03, 0x6007, 0x52f1, 0x9832,
0x6003, 0x52e9, 0x00a2, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07,
0x6a2b, 0x6a28, 0x0007, 0x6a0c, 0x54e1, 0xc795, 0x048b, 0x0498,
0x0454, 0x9825, 0x0800, 0x983c, 0x0870, 0x0011, 0x5010, 0xc0ec,
0x7d61, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x984a, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d45, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00,
0x7c04, 0x6a28, 0x7f3b, 0x0400, 0x985a, 0x008f, 0x00d5, 0x7d01,
0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d1c,
0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311, 0x53eb, 0x62c8,
0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f1f, 0x0212,
0x6a09, 0x7f1c, 0x0212, 0x6a09, 0x7f19, 0x2003, 0x4800, 0x7cef,
0x0b70, 0x0311, 0x5313, 0x989b, 0x0015, 0x0015, 0x7802, 0x62c8,
0x6a0b, 0x989a, 0x0015, 0x7802, 0x62c8, 0x6a0a, 0x989a, 0x7802,
0x62c8, 0x6a09, 0x7c03, 0x6a28, 0x0000, 0x9858, 0xc77b, 0x6a28,
0x7ffd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da2,
0x0200, 0x984a, 0x0200, 0x9847, 0x0870, 0x0011, 0x5010, 0xc0ec,
0x7d62, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x98b2, 0x6ec3, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d46, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00,
0x7c04, 0x62ff, 0x7e3c, 0x0400, 0x98c2, 0x008f, 0x00d5, 0x7d01,
0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d28,
0x4a02, 0x7d20, 0x4a01, 0x7d19, 0x6ddd, 0x0b70, 0x0311, 0x53eb,
0x62c8, 0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6ac8, 0x7f1f,
0x0212, 0x6ac8, 0x7f1c, 0x0212, 0x6ac8, 0x7f19, 0x2003, 0x4800,
0x7cef, 0x0b70, 0x0311, 0x5313, 0x9905, 0x6ddd, 0x7802, 0x62c8,
0x6ac8, 0x9904, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8, 0x9904,
0x0015, 0x0015, 0x7801, 0x62d8, 0x7c02, 0x0000, 0x98c0, 0xc777,
0x62ff, 0x7efd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d,
0x7da1, 0x0200, 0x98b2, 0x0200, 0x98af, 0xc19d, 0xc0ec, 0x7d69,
0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe,
0x56fa, 0x7d02, 0x0200, 0x991e, 0x6d07, 0x5bca, 0x5cd2, 0x0bff,
0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70,
0x0211, 0x552a, 0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9,
0x4d00, 0x7c13, 0x6928, 0x7f2d, 0x0400, 0x992f, 0x008f, 0x0015,
0x04d8, 0x7d01, 0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b,
0x7e29, 0x6d28, 0x7f1e, 0x0000, 0x992d, 0x1e20, 0x5506, 0x2620,
0x008d, 0x0560, 0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a,
0x7f10, 0x4c00, 0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0,
0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000,
0x9976, 0x0007, 0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28,
0x0007, 0x680c, 0x0007, 0x54d2, 0x0454, 0x9979, 0x6928, 0x7ff1,
0x54d2, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200,
0x991e, 0x0200, 0x9916, 0x1e10, 0x0870, 0x0011, 0x5010, 0xc0ec,
0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x998a, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00,
0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70, 0x0311,
0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9999, 0x0212, 0x3aff,
0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8, 0xd9d4,
0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xd9ec, 0x52c0, 0x53c8,
0xc10d, 0x7dd0, 0x0200, 0x998a, 0x008f, 0x00d5, 0x7d01, 0x008d,
0xd9d4, 0x9997, 0x0200, 0x9987, 0x0007, 0x68cc, 0x6a28, 0x7f01,
0x99d2, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b, 0x6a28,
0x0007, 0x680c, 0x0454, 0x99b0, 0x05a0, 0x1e08, 0x6ec3, 0x0388,
0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5, 0x6a28,
0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09, 0x7edc,
0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5, 0x0dff,
0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0388, 0x028d, 0x3a03,
0x4a00, 0x7c33, 0x028c, 0x3a03, 0x4a00, 0x7d0c, 0x0804, 0x00a2,
0x00db, 0x7d24, 0x03a0, 0x0498, 0x7802, 0x6209, 0x6a29, 0x7e24,
0x620c, 0x7e22, 0x0804, 0x03d0, 0x7d19, 0x0820, 0x028c, 0x3a1f,
0x00a2, 0x03d0, 0x7c02, 0x008b, 0x3003, 0x03a0, 0x0015, 0x0015,
0x6818, 0x7e12, 0x6828, 0x7f10, 0x0000, 0x0820, 0x03d8, 0x7df5,
0x0804, 0x03d0, 0x7d03, 0x008b, 0x3003, 0x9a15, 0x008b, 0x7802,
0x6209, 0x6a29, 0x7e01, 0x620c, 0x0006, 0x0804, 0x03d0, 0x7df6,
0x048b, 0x3403, 0x03a4, 0x0415, 0x0415, 0x0d0f, 0x0511, 0x1df0,
0x0808, 0x04d0, 0x7c01, 0x008c, 0x58c1, 0x04a0, 0x7803, 0x620b,
0x5a05, 0x1d01, 0x7ee9, 0x50c1, 0x05a0, 0x7803, 0x5205, 0x6a0b,
0x1d01, 0x6a28, 0x7fe1, 0x0000, 0x4c00, 0x7ce7, 0x9a26, 0x0870,
0x0011, 0x5010, 0xc0ec, 0x7d7a, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
0x56f8, 0x7d02, 0x0200, 0x9a55, 0x6d03, 0x6ed3, 0x0dff, 0x0511,
0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b,
0x5313, 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9a65,
0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512,
0x05bc, 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01,
0x7d1a, 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25,
0x620a, 0x7e23, 0x9a8f, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512,
0x0512, 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70,
0x0311, 0x5313, 0x9aaa, 0x7802, 0x6209, 0x6ac8, 0x9aa9, 0x0015,
0x7802, 0x620a, 0x6ac8, 0x9aa9, 0x0015, 0x0015, 0x7802, 0x620b,
0x6ac8, 0x7c03, 0x0000, 0x55db, 0x9a63, 0x0007, 0x68cc, 0x680c,
0x55d3, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9ab8, 0x0017, 0x0017,
0x55db, 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010,
0x04b8, 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x0870, 0x0011, 0x5010,
0x52c0, 0x53c8, 0xc10d, 0x7d89, 0x0200, 0x9a55, 0x0200, 0x9a52,
0xc19d, 0xc0ec, 0x7d52, 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c,
0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, 0x0200, 0x9ad9, 0x6d03,
0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da,
0x0a70, 0x0211, 0x4c00, 0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02,
0x0400, 0x9aec, 0x4c01, 0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01,
0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, 0x650b, 0x5d06, 0x0000,
0x7e0c, 0x7f0d, 0x9aea, 0x650a, 0x7e08, 0x008d, 0x0011, 0x0010,
0x05a8, 0x065f, 0x5d06, 0x063f, 0x7f02, 0x0007, 0x680c, 0x0007,
0x5012, 0x54d0, 0x0454, 0x9b16, 0x5012, 0x54d0, 0x0473, 0x7c06,
0x552a, 0x05b9, 0x4d00, 0x7c02, 0x0400, 0x9b18, 0x52c0, 0x53c8,
0xc10d, 0x0288, 0x7db6, 0x0200, 0x9ad9, 0x0200, 0x9ad1, 0x0870,
0x0011, 0x5010, 0xc0ec, 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
0x56f8, 0x7d02, 0x0200, 0x9b2d, 0x0b70, 0x0311, 0x6ed3, 0x6d03,
0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9,
0x4a00, 0x7c04, 0x62c8, 0x7e1f, 0x0400, 0x9b3e, 0x008f, 0x00d5,
0x7d01, 0x008d, 0x05a0, 0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16,
0x6ac8, 0x7f11, 0x0015, 0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e,
0x6ac8, 0x7f09, 0x6edf, 0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000,
0x7e05, 0x7f01, 0x9b3c, 0x0007, 0x68cc, 0x9b68, 0x0007, 0x6a0c,
0x0454, 0x62c8, 0x7ef8, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd,
0x0200, 0x9b2d, 0x0200, 0x9b2a, 0xc19d, 0x0870, 0x0011, 0xc0ec,
0x7d29, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x9b7b, 0x0870, 0x0011, 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d12, 0x5228, 0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9b8a,
0x620b, 0x7e06, 0x5a06, 0x7f06, 0x0000, 0x2504, 0x7d05, 0x9b8a,
0x0007, 0x680c, 0x0007, 0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb,
0x0200, 0x9b7b, 0x0200, 0x9b77, 0xc19d, 0x0870, 0x0011, 0xc0ec,
0x7d76, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
0x0200, 0x9bab, 0x6d03, 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0,
0x0dff, 0x0511, 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70,
0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9bbf,
0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00,
0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea,
0x0260, 0x7d05, 0x6509, 0x7e25, 0x630a, 0x7e23, 0x9be3, 0x630a,
0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19,
0x2003, 0x4800, 0x7ced, 0x0a70, 0x0211, 0x5212, 0x9bfe, 0x7802,
0x6309, 0x5b06, 0x9bfd, 0x0015, 0x7802, 0x630a, 0x5b06, 0x9bfd,
0x0015, 0x0015, 0x7802, 0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000,
0x9bbd, 0x0007, 0x680c, 0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02,
0x9c0b, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff,
0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454, 0x0870, 0x0011,
0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d8e, 0x0200, 0x9bab, 0x0200,
0x9ba7, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d35, 0x5010, 0x5ac0,
0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9c28, 0x0870, 0x0011,
0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d1c, 0x5228,
0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b, 0x0400, 0x9c37, 0x5206,
0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000, 0x2504, 0x7d0c, 0x9c37,
0x0007, 0x680c, 0x680c, 0x6207, 0x6a07, 0x6a2b, 0x6a28, 0x0007,
0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3, 0x5010, 0x52c0, 0xc10d,
0x7dcf, 0x0200, 0x9c28, 0x0200, 0x9c24, 0x0870, 0x0011, 0x5010,
0xc0ec, 0x7d7c, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
0x0200, 0x9c63, 0x6ed3, 0x6dc5, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x5df8, 0x4d00, 0x7d60, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9,
0x4a00, 0x7c02, 0x0400, 0x9c73, 0x008f, 0x00d5, 0x7d01, 0x008d,
0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd3, 0x4d00,
0x7d2c, 0x4d02, 0x7d24, 0x4d01, 0x7d1e, 0x59e3, 0x0b70, 0x0311,
0x53eb, 0x61c8, 0x7e2b, 0x62c8, 0x7e29, 0x65c8, 0x7e27, 0x0360,
0x7d03, 0x0112, 0x0112, 0x9c9e, 0x0512, 0x0512, 0x0211, 0x02a9,
0x02ad, 0x6ac8, 0x7f1b, 0x2003, 0x4800, 0x7ceb, 0x0b70, 0x0311,
0x5313, 0x51e3, 0x9cbb, 0x7802, 0x62c8, 0x6ac8, 0x9cba, 0x6dce,
0x0015, 0x7802, 0x62c8, 0x6ac8, 0x9cba, 0x6dcf, 0x0015, 0x0015,
0x7801, 0x62d8, 0x7c03, 0x0000, 0x55db, 0x9c71, 0x0007, 0x68ff,
0x55d3, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9cc8, 0x0017, 0x0017,
0x55db, 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010,
0x04b8, 0x04ad, 0x0454, 0x62c8, 0x7ee9, 0x0870, 0x0011, 0x5010,
0x52c0, 0x53c8, 0xc10d, 0x7d87, 0x0200, 0x9c63, 0x0200, 0x9c60,
0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d7c, 0x5010, 0x5ac0, 0x5bc8,
0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9ce7, 0x6dc5, 0x0d03,
0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x5df8, 0x4d00, 0x7d5d, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9,
0x4b00, 0x7c02, 0x0400, 0x9cfb, 0x008f, 0x05d8, 0x7d01, 0x008d,
0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d2c, 0x4d02, 0x7d24, 0x4d01,
0x7d1e, 0x59e2, 0x0a70, 0x0211, 0x52ea, 0x61c8, 0x7e2c, 0x63c8,
0x7e2a, 0x65c8, 0x7e28, 0x0260, 0x7d03, 0x0112, 0x0112, 0x9d22,
0x0512, 0x0512, 0x0311, 0x03a9, 0x03ad, 0x5b06, 0x7f1c, 0x2003,
0x4800, 0x7ceb, 0x0a70, 0x0211, 0x5212, 0x51e2, 0x9d40, 0x7802,
0x63c8, 0x5b06, 0x9d3f, 0x6dce, 0x0015, 0x7802, 0x63c8, 0x5b06,
0x9d3f, 0x6dcf, 0x0015, 0x0015, 0x7802, 0x63c8, 0x5b06, 0x7c03,
0x55da, 0x0000, 0x9cf9, 0x0007, 0x68ff, 0x55d2, 0x4d00, 0x7d03,
0x4d02, 0x7d02, 0x9d4d, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa,
0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454,
0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d88, 0x0200,
0x9ce7, 0x0200, 0x9ce3, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d61,
0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x9d6a, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00,
0x7d45, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04,
0x6a28, 0x7f3b, 0x0400, 0x9d79, 0x008f, 0x05d8, 0x7d01, 0x008d,
0x05a0, 0x0b03, 0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02,
0x7d20, 0x4b01, 0x7d23, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e25,
0x0260, 0x7d02, 0x0310, 0x0312, 0x6b09, 0x7f1f, 0x0312, 0x6b09,
0x7f1c, 0x0312, 0x6b09, 0x7f19, 0x2003, 0x4800, 0x7cef, 0x0a70,
0x0211, 0x5212, 0x9dba, 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b,
0x9db9, 0x0015, 0x7802, 0x5306, 0x6b0a, 0x9db9, 0x7802, 0x5306,
0x6b09, 0x7c03, 0x6b28, 0x0000, 0x9d77, 0xc77b, 0x6928, 0x7ffd,
0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da3, 0x0200,
0x9d6a, 0x0200, 0x9d66, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d60,
0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
0x9dd2, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00,
0x7d46, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02,
0x0400, 0x9de1, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03,
0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d28, 0x4b02, 0x7d20, 0x4b01,
0x7d19, 0x6ddd, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e27, 0x0260,
0x7d02, 0x0310, 0x0312, 0x6bc8, 0x7f21, 0x0312, 0x6bc8, 0x7f1e,
0x0312, 0x6bc8, 0x7f1b, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211,
0x5212, 0x9e23, 0x6ddd, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x6dde,
0x0015, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x0015, 0x0015, 0x7802,
0x5306, 0x6bc8, 0x7c03, 0x0000, 0xde32, 0x9ddf, 0xc777, 0x0870,
0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da4, 0x0200, 0x9dd2,
0x0200, 0x9dce, 0x63ff, 0x0368, 0x7d02, 0x0369, 0x7def, 0x0006,
0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d5c, 0x5ac0, 0x5bc8, 0x5ef8,
0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9e3e, 0x0b70, 0x0311, 0x6ec3,
0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3e,
0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f34, 0x0400, 0x9e50,
0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3,
0x6ed3, 0x62c8, 0x0248, 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e,
0x7d32, 0x6a09, 0x7f1f, 0x2501, 0x4d00, 0x7d20, 0x028e, 0x1a98,
0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x6a28, 0x7f13, 0xc7af,
0x9e90, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0,
0x62c8, 0x026e, 0x7d18, 0x6a09, 0x7f05, 0x2001, 0x7cf9, 0x6a28,
0x0000, 0x9e4e, 0x0289, 0xc77b, 0x018a, 0x9e9f, 0x6a28, 0x7ffa,
0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7da7, 0x0200,
0x9e3e, 0x0200, 0x9e3b, 0x6a28, 0x7fed, 0xc7af, 0x9e9f, 0x0458,
0x0454, 0x9e90, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d55, 0x5010,
0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9ea9,
0x0b70, 0x0311, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
0x4d00, 0x7d37, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f2d,
0x0400, 0x9eba, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d16, 0x1e94,
0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d2f, 0x6a09,
0x7f1c, 0x2501, 0x4d00, 0x7d1d, 0x028e, 0x1a98, 0x5202, 0x0260,
0x7df3, 0x6a28, 0x7f12, 0xc7af, 0x9ef3, 0x008f, 0x2001, 0x00d5,
0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d18, 0x6a09, 0x7f05,
0x2001, 0x7cf9, 0x6a28, 0x0000, 0x9eb8, 0x0289, 0xc77b, 0x018a,
0x9f02, 0x6928, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8,
0xc10d, 0x7daf, 0x0200, 0x9ea9, 0x0200, 0x9ea5, 0x6a28, 0x7fed,
0xc7af, 0x9f02, 0x0458, 0x0454, 0x9ef3
};
#endif

267
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/*
* Copyright 2006-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx3/serial.c
*
* @brief This file contains the UART initiliazation.
*
* @ingroup MSL_MX31
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <mach/hardware.h>
#include <mach/mxc_uart.h>
#include <mach/spba.h>
#include "serial.h"
#include "board-mx31ads.h"
#include "board-mx3_3stack.h"
#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
/*!
* This is an array where each element holds information about a UART port,
* like base address of the UART, interrupt numbers etc. This structure is
* passed to the serial_core.c file. Based on which UART is used, the core file
* passes back the appropriate port structure as an argument to the control
* functions.
*/
static uart_mxc_port mxc_ports[MXC_UART_NR] = {
[0] = {
.port = {
.membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
.mapbase = UART1_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART1_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.ints_muxed = UART1_MUX_INTS,
.irqs = {UART1_INT2, UART1_INT3},
.mode = UART1_MODE,
.ir_mode = UART1_IR,
.enabled = UART1_ENABLED,
.hardware_flow = UART1_HW_FLOW,
.cts_threshold = UART1_UCR4_CTSTL,
.dma_enabled = UART1_DMA_ENABLE,
.dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
.rx_threshold = UART1_UFCR_RXTL,
.tx_threshold = UART1_UFCR_TXTL,
.shared = UART1_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART1_TX,
.dma_rx_id = MXC_DMA_UART1_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
[1] = {
.port = {
.membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
.mapbase = UART2_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART2_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 1,
},
.ints_muxed = UART2_MUX_INTS,
.irqs = {UART2_INT2, UART2_INT3},
.mode = UART2_MODE,
.ir_mode = UART2_IR,
.enabled = UART2_ENABLED,
.hardware_flow = UART2_HW_FLOW,
.cts_threshold = UART2_UCR4_CTSTL,
.dma_enabled = UART2_DMA_ENABLE,
.dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
.rx_threshold = UART2_UFCR_RXTL,
.tx_threshold = UART2_UFCR_TXTL,
.shared = UART2_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART2_TX,
.dma_rx_id = MXC_DMA_UART2_RX,
.rxd_mux = MXC_UART_IR_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#if UART3_ENABLED == 1
[2] = {
.port = {
.membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
.mapbase = UART3_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART3_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 2,
},
.ints_muxed = UART3_MUX_INTS,
.irqs = {UART3_INT2, UART3_INT3},
.mode = UART3_MODE,
.ir_mode = UART3_IR,
.enabled = UART3_ENABLED,
.hardware_flow = UART3_HW_FLOW,
.cts_threshold = UART3_UCR4_CTSTL,
.dma_enabled = UART3_DMA_ENABLE,
.dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
.rx_threshold = UART3_UFCR_RXTL,
.tx_threshold = UART3_UFCR_TXTL,
.shared = UART3_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART3_TX,
.dma_rx_id = MXC_DMA_UART3_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#endif
#if UART4_ENABLED == 1
[3] = {
.port = {
.membase = (void *)IO_ADDRESS(UART4_BASE_ADDR),
.mapbase = UART4_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART4_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 3,
},
.ints_muxed = UART4_MUX_INTS,
.irqs = {UART4_INT2, UART4_INT3},
.mode = UART4_MODE,
.ir_mode = UART4_IR,
.enabled = UART4_ENABLED,
.hardware_flow = UART4_HW_FLOW,
.cts_threshold = UART4_UCR4_CTSTL,
.dma_enabled = UART4_DMA_ENABLE,
.dma_rxbuf_size = UART4_DMA_RXBUFSIZE,
.rx_threshold = UART4_UFCR_RXTL,
.tx_threshold = UART4_UFCR_TXTL,
.shared = UART4_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART4_TX,
.dma_rx_id = MXC_DMA_UART4_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#endif
#if UART5_ENABLED == 1
[4] = {
.port = {
.membase = (void *)IO_ADDRESS(UART5_BASE_ADDR),
.mapbase = UART5_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART5_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 4,
},
.ints_muxed = UART5_MUX_INTS,
.irqs = {UART5_INT2, UART5_INT3},
.mode = UART5_MODE,
.ir_mode = UART5_IR,
.enabled = UART5_ENABLED,
.hardware_flow = UART5_HW_FLOW,
.cts_threshold = UART5_UCR4_CTSTL,
.dma_enabled = UART5_DMA_ENABLE,
.dma_rxbuf_size = UART5_DMA_RXBUFSIZE,
.rx_threshold = UART5_UFCR_RXTL,
.tx_threshold = UART5_UFCR_TXTL,
.shared = UART5_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART5_TX,
.dma_rx_id = MXC_DMA_UART5_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#endif
};
static struct platform_device mxc_uart_device1 = {
.name = "mxcintuart",
.id = 0,
.dev = {
.platform_data = &mxc_ports[0],
},
};
static struct platform_device mxc_uart_device2 = {
.name = "mxcintuart",
.id = 1,
.dev = {
.platform_data = &mxc_ports[1],
},
};
#if UART3_ENABLED == 1
static struct platform_device mxc_uart_device3 = {
.name = "mxcintuart",
.id = 2,
.dev = {
.platform_data = &mxc_ports[2],
},
};
#endif
#if UART4_ENABLED == 1
static struct platform_device mxc_uart_device4 = {
.name = "mxcintuart",
.id = 3,
.dev = {
.platform_data = &mxc_ports[3],
},
};
#endif
#if UART5_ENABLED == 1
static struct platform_device mxc_uart_device5 = {
.name = "mxcintuart",
.id = 4,
.dev = {
.platform_data = &mxc_ports[4],
},
};
#endif
static int __init mxc_init_uart(void)
{
/* Register all the MXC UART platform device structures */
platform_device_register(&mxc_uart_device1);
platform_device_register(&mxc_uart_device2);
/* Grab ownership of shared UARTs 3 and 4, only when enabled */
#if UART3_ENABLED == 1
#if UART3_DMA_ENABLE == 1
spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C));
#else
spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A);
#endif /* UART3_DMA_ENABLE */
platform_device_register(&mxc_uart_device3);
#endif /* UART3_ENABLED */
#if UART4_ENABLED == 1
platform_device_register(&mxc_uart_device4);
#endif /* UART4_ENABLED */
#if UART5_ENABLED == 1
platform_device_register(&mxc_uart_device5);
#endif /* UART5_ENABLED */
return 0;
}
#else
static int __init mxc_init_uart(void)
{
return 0;
}
#endif
arch_initcall(mxc_init_uart);

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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX3_SERIAL_H__
#define __ARCH_ARM_MACH_MX3_SERIAL_H__
/*!
* @file mach-mx3/serial.h
*
* @ingroup MSL_MX31
*/
#include <mach/mxc_uart.h>
/*
* UART Chip level Configuration that a user may not have to edit. These
* configuration vary depending on how the UART module is integrated with
* the ARM core
*/
#define MXC_UART_NR 5
/*!
* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
* Certain platforms need this bit to be set in order to receive Irda data.
*/
#define MXC_UART_IR_RXDMUX 0x0004
/*!
* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
* Certain platforms need this bit to be set in order to receive UART data.
*/
#define MXC_UART_RXDMUX 0x0004
/* UART 1 configuration */
/*!
* This option allows to choose either an interrupt-driven software controlled
* hardware flow control (set this option to 0) or hardware-driven hardware
* flow control (set this option to 1).
*/
/* UART used as wakeup source */
#define UART1_HW_FLOW 0
/*!
* This specifies the threshold at which the CTS pin is deasserted by the
* RXFIFO. Set this value in Decimal to anything from 0 to 32 for
* hardware-driven hardware flow control. Read the HW spec while specifying
* this value. When using interrupt-driven software controlled hardware
* flow control set this option to -1.
*/
#define UART1_UCR4_CTSTL 16
/*!
* This is option to enable (set this option to 1) or disable DMA data transfer
*/
#define UART1_DMA_ENABLE 0
/*!
* Specify the size of the DMA receive buffer. The minimum buffer size is 512
* bytes. The buffer size should be a multiple of 256.
*/
#define UART1_DMA_RXBUFSIZE 1024
/*!
* Specify the MXC UART's Receive Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the RxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_RXTL 16
/*!
* Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the TxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_TXTL 16
/* UART 2 configuration */
#define UART2_HW_FLOW 0
#define UART2_UCR4_CTSTL -1
#define UART2_DMA_ENABLE 0
#define UART2_DMA_RXBUFSIZE 512
#define UART2_UFCR_RXTL 16
#define UART2_UFCR_TXTL 16
/* UART 3 configuration */
#define UART3_HW_FLOW 1
#define UART3_UCR4_CTSTL 16
#define UART3_DMA_ENABLE 1
#define UART3_DMA_RXBUFSIZE 1024
#define UART3_UFCR_RXTL 16
#define UART3_UFCR_TXTL 16
/* UART 4 configuration */
#define UART4_HW_FLOW 1
#define UART4_UCR4_CTSTL 16
#define UART4_DMA_ENABLE 0
#define UART4_DMA_RXBUFSIZE 512
#define UART4_UFCR_RXTL 16
#define UART4_UFCR_TXTL 16
/* UART 5 configuration */
#define UART5_HW_FLOW 1
#define UART5_UCR4_CTSTL 16
#define UART5_DMA_ENABLE 0
#define UART5_DMA_RXBUFSIZE 512
#define UART5_UFCR_RXTL 16
#define UART5_UFCR_TXTL 16
/*
* UART Chip level Configuration that a user may not have to edit. These
* configuration vary depending on how the UART module is integrated with
* the ARM core
*/
/*
* Is the MUXED interrupt output sent to the ARM core
*/
#define INTS_NOTMUXED 0
#define INTS_MUXED 1
/* UART 1 configuration */
/*!
* This define specifies whether the muxed ANDed interrupt line or the
* individual interrupts from the UART port is integrated with the ARM core.
* There exists a define like this for each UART port. Valid values that can
* be used are \b INTS_NOTMUXED or \b INTS_MUXED.
*/
#define UART1_MUX_INTS INTS_MUXED
/*!
* This define specifies the transmitter interrupt number or the interrupt
* number of the ANDed interrupt in case the interrupts are muxed. There exists
* a define like this for each UART port.
*/
#define UART1_INT1 MXC_INT_UART1
/*!
* This define specifies the receiver interrupt number. If the interrupts of
* the UART are muxed, then we specify here a dummy value -1. There exists a
* define like this for each UART port.
*/
#define UART1_INT2 -1
/*!
* This specifies the master interrupt number. If the interrupts of the UART
* are muxed, then we specify here a dummy value of -1. There exists a define
* like this for each UART port.
*/
#define UART1_INT3 -1
/*!
* This specifies if the UART is a shared peripheral. It holds the shared
* peripheral number if it is shared or -1 if it is not shared. There exists
* a define like this for each UART port.
*/
#define UART1_SHARED_PERI -1
/* UART 2 configuration */
#define UART2_MUX_INTS INTS_MUXED
#define UART2_INT1 MXC_INT_UART2
#define UART2_INT2 -1
#define UART2_INT3 -1
#define UART2_SHARED_PERI -1
/* UART 3 configuration */
#define UART3_MUX_INTS INTS_MUXED
#define UART3_INT1 MXC_INT_UART3
#define UART3_INT2 -1
#define UART3_INT3 -1
#define UART3_SHARED_PERI SPBA_UART3
/* UART 4 configuration */
#define UART4_MUX_INTS INTS_MUXED
#define UART4_INT1 MXC_INT_UART4
#define UART4_INT2 -1
#define UART4_INT3 -1
#define UART4_SHARED_PERI -1
/* UART 5 configuration */
#define UART5_MUX_INTS INTS_MUXED
#define UART5_INT1 MXC_INT_UART5
#define UART5_INT2 -1
#define UART5_INT3 -1
#define UART5_SHARED_PERI -1
#endif /* __ARCH_ARM_MACH_MX3_SERIAL_H__ */

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/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/proc-fns.h>
#include <asm/system.h>
#include <mach/clock.h>
#include "crm_regs.h"
/*!
* @defgroup MSL_MX31 i.MX31 Machine Specific Layer (MSL)
*/
/*!
* @file mach-mx3/system.c
* @brief This file contains idle and reset functions.
*
* @ingroup MSL_MX31
*/
static int clks_initialized = 0;
static struct clk *sdma_clk, *mbx_clk, *ipu_clk, *mpeg_clk, *vpu_clk, *usb_clk,
*rtic_clk, *nfc_clk, *emi_clk;
extern int mxc_jtag_enabled;
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
int emi_gated_off = 0;
/*
* This should do all the clock switching
* and wait for interrupt tricks.
*/
if (!mxc_jtag_enabled) {
if (clks_initialized == 0) {
clks_initialized = 1;
sdma_clk = clk_get(NULL, "sdma_ahb_clk");
ipu_clk = clk_get(NULL, "ipu_clk");
if (cpu_is_mx31()) {
mpeg_clk = clk_get(NULL, "mpeg4_clk");
mbx_clk = clk_get(NULL, "mbx_clk");
} else {
vpu_clk = clk_get(NULL, "vpu_clk");
}
usb_clk = clk_get(NULL, "usb_ahb_clk");
rtic_clk = clk_get(NULL, "rtic_clk");
nfc_clk = clk_get(NULL, "nfc_clk");
emi_clk = clk_get(NULL, "emi_clk");
}
if ((clk_get_usecount(sdma_clk) == 0)
&& (clk_get_usecount(ipu_clk) <= 1)
&& (clk_get_usecount(usb_clk) == 0)
&& (clk_get_usecount(rtic_clk) == 0)
&& (clk_get_usecount(mpeg_clk) == 0)
&& (clk_get_usecount(mbx_clk) == 0)
&& (clk_get_usecount(nfc_clk) == 0)
&& (clk_get_usecount(vpu_clk) == 0)) {
emi_gated_off = 1;
clk_disable(emi_clk);
}
cpu_do_idle();
if (emi_gated_off == 1) {
clk_enable(emi_clk);
}
}
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
void arch_reset(char mode)
{
/* Assert SRS signal */
mxc_wd_reset();
}

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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
extern int usbotg_init(struct platform_device *pdev);
extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
extern int gpio_usbotg_fs_active(void);
extern void gpio_usbotg_fs_inactive(void);
extern int gpio_usbotg_hs_active(void);
extern void gpio_usbotg_hs_inactive(void);
extern struct platform_device *host_pdev_register(struct resource *res,
int n_res, struct fsl_usb2_platform_data *config);
extern int fsl_usb_host_init(struct platform_device *pdev);
extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
extern int gpio_usbh1_active(void);
extern void gpio_usbh1_inactive(void);
extern int gpio_usbh2_active(void);
extern void gpio_usbh2_inactive(void);
/*
* Determine which platform_data struct to use for the DR controller,
* based on which transceiver is configured.
* PDATA is a pointer to it.
*/
#if defined(CONFIG_ISP1504_MXC)
static struct fsl_usb2_platform_data __maybe_unused dr_1504_config;
#define PDATA (&dr_1504_config)
#elif defined(CONFIG_ISP1301_MXC)
static struct fsl_usb2_platform_data __maybe_unused dr_1301_config;
#define PDATA (&dr_1301_config)
#elif defined(CONFIG_MC13783_MXC)
static struct fsl_usb2_platform_data __maybe_unused dr_13783_config;
#define PDATA (&dr_13783_config)
#endif
/*
* Used to set pdata->operating_mode before registering the platform_device.
* If OTG is configured, the controller operates in OTG mode,
* otherwise it's either host or device.
*/
#ifdef CONFIG_USB_OTG
#define DR_UDC_MODE FSL_USB2_DR_OTG
#define DR_HOST_MODE FSL_USB2_DR_OTG
#else
#define DR_UDC_MODE FSL_USB2_DR_DEVICE
#define DR_HOST_MODE FSL_USB2_DR_HOST
#endif
#ifdef CONFIG_USB_EHCI_ARC_OTG
static inline void dr_register_host(struct resource *r, int rs)
{
PDATA->operating_mode = DR_HOST_MODE;
host_pdev_register(r, rs, PDATA);
}
#else
static inline void dr_register_host(struct resource *r, int rs)
{
}
#endif
#ifdef CONFIG_USB_GADGET_ARC
static struct platform_device dr_udc_device;
static inline void dr_register_udc(void)
{
PDATA->operating_mode = DR_UDC_MODE;
dr_udc_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_udc_device))
printk(KERN_ERR "usb: can't register DR gadget\n");
else
printk(KERN_INFO "usb: DR gadget (%s) registered\n",
PDATA->transceiver);
}
#else
static inline void dr_register_udc(void)
{
}
#endif
#ifdef CONFIG_USB_OTG
static struct platform_device dr_otg_device;
/*
* set the proper operating_mode and
* platform_data pointer, then register the
* device.
*/
static inline void dr_register_otg(void)
{
PDATA->operating_mode = FSL_USB2_DR_OTG;
dr_otg_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_otg_device))
printk(KERN_ERR "usb: can't register otg device\n");
else
printk(KERN_INFO "usb: DR OTG registered\n");
}
#else
static inline void dr_register_otg(void)
{
}
#endif

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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
/*
* platform data structs
* - Which one to use is determined by CONFIG options in usb.h
* - operating_mode plugged at run time
*/
static struct fsl_usb2_platform_data __maybe_unused dr_13783_config = {
.name = "DR",
.platform_init = usbotg_init,
.platform_uninit = usbotg_uninit,
.phy_mode = FSL_USB2_PHY_SERIAL,
.power_budget = 500, /* 500 mA max power */
.gpio_usb_active = gpio_usbotg_fs_active,
.gpio_usb_inactive = gpio_usbotg_fs_inactive,
.transceiver = "mc13783",
};
static struct fsl_usb2_platform_data __maybe_unused dr_1301_config = {
.name = "DR",
.platform_init = usbotg_init,
.platform_uninit = usbotg_uninit,
.phy_mode = FSL_USB2_PHY_SERIAL,
.power_budget = 150, /* 150 mA max power */
.gpio_usb_active = gpio_usbotg_fs_active,
.gpio_usb_inactive = gpio_usbotg_fs_inactive,
.transceiver = "isp1301",
};
static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = {
.name = "DR",
.platform_init = usbotg_init,
.platform_uninit = usbotg_uninit,
.phy_mode = FSL_USB2_PHY_ULPI,
.power_budget = 150, /* 150 mA max power */
.gpio_usb_active = gpio_usbotg_hs_active,
.gpio_usb_inactive = gpio_usbotg_hs_inactive,
.transceiver = "isp1504",
};
/*
* resources
*/
static struct resource otg_resources[] = {
[0] = {
.start = (u32)(USB_OTGREGS_BASE),
.end = (u32)(USB_OTGREGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 dr_udc_dmamask = ~(u32) 0;
static void dr_udc_release(struct device *dev)
{
}
static u64 dr_otg_dmamask = ~(u32) 0;
static void dr_otg_release(struct device *dev)
{
}
/*
* platform device structs
* dev.platform_data field plugged at run time
*/
static struct platform_device __maybe_unused dr_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.release = dr_udc_release,
.dma_mask = &dr_udc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static struct platform_device __maybe_unused dr_otg_device = {
.name = "fsl-usb2-otg",
.id = -1,
.dev = {
.release = dr_otg_release,
.dma_mask = &dr_otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static int __init usb_dr_init(void)
{
pr_debug("%s: \n", __func__);
dr_register_otg();
dr_register_host(otg_resources, ARRAY_SIZE(otg_resources));
dr_register_udc();
#ifdef CONFIG_USB_GADGET_WAKE_UP
/* set udc may and should wakeup */
device_init_wakeup(&(dr_udc_device.dev), 1);
#endif
return 0;
}
module_init(usb_dr_init);

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arch/arm/mach-mx3/usb_h1.c Normal file
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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <mach/arc_otg.h>
#include <mach/hardware.h>
#include "usb.h"
static struct fsl_usb2_platform_data usbh1_config = {
.name = "Host 1",
.platform_init = fsl_usb_host_init,
.platform_uninit = fsl_usb_host_uninit,
.operating_mode = FSL_USB2_MPH_HOST,
.phy_mode = FSL_USB2_PHY_SERIAL,
.power_budget = 500, /* 500 mA max power */
.gpio_usb_active = gpio_usbh1_active,
.gpio_usb_inactive = gpio_usbh1_inactive,
.transceiver = "serial",
};
static struct resource usbh1_resources[] = {
[0] = {
.start = (u32) (USB_H1REGS_BASE),
.end = (u32) (USB_H1REGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
static int __init usbh1_init(void)
{
pr_debug("%s: \n", __func__);
host_pdev_register(usbh1_resources, ARRAY_SIZE(usbh1_resources),
&usbh1_config);
return 0;
}
module_init(usbh1_init);

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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/mach-types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/usb/fsl_xcvr.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
static struct fsl_usb2_platform_data usbh2_config = {
.name = "Host 2",
.platform_init = fsl_usb_host_init,
.platform_uninit = fsl_usb_host_uninit,
.operating_mode = FSL_USB2_MPH_HOST,
.phy_mode = FSL_USB2_PHY_ULPI,
.power_budget = 500, /* 500 mA max power */
.gpio_usb_active = gpio_usbh2_active,
.gpio_usb_inactive = gpio_usbh2_inactive,
.transceiver = "isp1504",
};
static struct resource usbh2_resources[] = {
[0] = {
.start = (u32) (USB_H2REGS_BASE),
.end = (u32) (USB_H2REGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
static int __init usbh2_init(void)
{
pr_debug("%s: \n", __func__);
if (machine_is_mx31_3ds()) {
struct regulator *usbh2_regux;
usbh2_config.xcvr_pwr =
kmalloc(sizeof(struct fsl_xcvr_power), GFP_KERNEL);
if (!(usbh2_config.xcvr_pwr))
return -ENOMEM;
usbh2_regux = regulator_get(NULL, "GPO1");
usbh2_config.xcvr_pwr->regu1 = usbh2_regux;
usbh2_regux = regulator_get(NULL, "GPO3");
usbh2_config.xcvr_pwr->regu2 = usbh2_regux;
}
host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
&usbh2_config);
return 0;
}
module_init(usbh2_init);

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menu "MX35 Options"
depends on ARCH_MX35
config FORCE_MAX_ZONEORDER
int "MAX_ORDER"
default "13"
config MX35_OPTIONS
bool
default y
select CPU_V6
select ARM_ERRATA_364296
select ARM_ERRATA_411920
select CACHE_L2X0
select OUTER_CACHE
select USB_ARCH_HAS_EHCI
select ARCH_HAS_EVTMON
select ARCH_HAS_RNGC
config MACH_MX35_3DS
bool "Support MX35 3STACK platforms"
default y
select MXC_PSEUDO_IRQS if MXC_PMIC_MC9SDZ60
help
Include support for MX35 3STACK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX35EVB
bool "Support MX35EVB platforms"
default n
help
Include support for MX35EVB platform. This includes specific
configurations for the board and its peripherals.
config MX35_DOZE_DURING_IDLE
bool "Enter Doze mode during idle"
help
Turning on this option will put the CPU into Doze mode during idle.
The default is to enter Wait mode during idle. Doze mode during
idle will save additional power over Wait mode.
config MXC_SDMA_API
bool "Use SDMA API"
default y
help
This selects the Freescale MXC SDMA API.
If unsure, say N.
menu "SDMA options"
depends on MXC_SDMA_API
config SDMA_IRAM
bool "Use Internal RAM for SDMA transfer"
default n
help
Support Internal RAM as SDMA buffer or control structures
config SDMA_IRAM_SIZE
hex "Reserved bytes of IRAM for SDMA (0x800-0x1000)"
range 0x800 0x1000
depends on SDMA_IRAM
default "0x1000"
help
Set the size of IRAM for SDMA. It must be a multiple of 512bytes.
endmenu
config ARCH_MXC_HAS_NFC_V2
bool "MXC NFC Hardware Version 2"
depends on ARCH_MX35
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 3
If unsure, say N.
config ARCH_MXC_HAS_NFC_V2_1
bool "MXC NFC Hardware Version 2.1"
depends on ARCH_MXC_HAS_NFC_V2
default y
help
This selects the Freescale MXC Nand Flash Controller Hardware Version 2.1
If unsure, say N.
menu "Device options"
config I2C_MXC_SELECT1
bool "Enable I2C1 module"
default y
depends on I2C_MXC
help
Enable MX35 I2C1 module.
config I2C_MXC_SELECT2
bool "Enable I2C2 module"
default n
depends on I2C_MXC
help
Enable MX35 I2C2 module.
config I2C_MXC_SELECT3
bool "Enable I2C3 module"
default n
depends on I2C_MXC
help
Enable MX35 I2C3 module.
endmenu
config MXC_PSEUDO_IRQS
bool
endmenu

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arch/arm/mach-mx35/Makefile Normal file
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#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o
obj-$(CONFIG_MXC_SDMA_API) += dma.o
obj-$(CONFIG_MACH_MX35_3DS) += mx35_3stack.o mx35_3stack_gpio.o mx35_3stack_cpld.o dvfs.o mx35_3stack_pmic_mc13892.o mx35_3stack_pmic_mc9s08dz60.o
obj-$(CONFIG_MACH_MX35EVB) += mx35evb.o mx35evb_cpld.o mx35evb_gpio.o
obj-$(CONFIG_MXC_PSEUDO_IRQS) += mx35_3stack_irq.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o
ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
obj-y += usb_dr.o
endif

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arch/arm/mach-mx35/Makefile.boot Normal file
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ifeq ($(CONFIG_MACH_MX35EVB), y)
zreladdr-y := 0x90008000
params_phys-y := 0x90000100
initrd_phys-y := 0x90800000
else
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
endif

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arch/arm/mach-mx35/board-mx35_3stack.h Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__
#define __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__
#ifdef CONFIG_MACH_MX35_3DS
/*!
* @defgroup BRDCFG_MX35 Board Configuration Options
* @ingroup MSL_MX35
*/
/*!
* @file mach-mx35/board-mx35_3stack.h
*
* @brief This file contains all the board level configuration options.
*
* It currently hold the options defined for MX35 3STACK Platform.
*
* @ingroup BRDCFG_MX35
*/
/*
* Include Files
*/
#include <mach/mxc_uart.h>
/*!
* @name MXC UART EVB board level configurations
*/
/*! @{ */
/*!
* Specifies if the Irda transmit path is inverting
*/
#define MXC_IRDA_TX_INV 0
/*!
* Specifies if the Irda receive path is inverting
*/
#define MXC_IRDA_RX_INV 0
/* UART 1 configuration */
/*!
* This define specifies if the UART port is configured to be in DTE or
* DCE mode. There exists a define like this for each UART port. Valid
* values that can be used are \b MODE_DTE or \b MODE_DCE.
*/
#define UART1_MODE MODE_DCE
/*!
* This define specifies if the UART is to be used for IRDA. There exists a
* define like this for each UART port. Valid values that can be used are
* \b IRDA or \b NO_IRDA.
*/
#define UART1_IR NO_IRDA
/*!
* This define is used to enable or disable a particular UART port. If
* disabled, the UART will not be registered in the file system and the user
* will not be able to access it. There exists a define like this for each UART
* port. Specify a value of 1 to enable the UART and 0 to disable it.
*/
#define UART1_ENABLED 1
/*! @} */
/* UART 2 configuration */
#define UART2_MODE MODE_DTE
#define UART2_IR NO_IRDA
#define UART2_ENABLED 1
/* UART 3 configuration */
#define UART3_MODE MODE_DTE
#define UART3_IR NO_IRDA
#define UART3_ENABLED 1
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#define MXC_PSEUDO_PARENT MXC_INT_FORCE
enum {
MCU_INT_HEADPHONE = 0,
MCU_INT_GPS,
MCU_INT_SD1_CD,
MCU_INT_SD1_WP,
MCU_INT_SD2_CD,
MCU_INT_SD2_WP,
MCU_INT_POWER_KEY,
MCU_INT_RTC,
MCU_INT_TS_ADC,
MCU_INT_KEYPAD,
};
#define MXC_PSEUDO_IRQ_HEADPHONE (MXC_PSEUDO_IO_BASE + MCU_INT_HEADPHONE)
#define MXC_PSEUDO_IRQ_GPS (MXC_PSEUDO_IO_BASE + MCU_INT_GPS)
#define MXC_PSEUDO_IRQ_SD1_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_CD)
#define MXC_PSEUDO_IRQ_SD1_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_WP)
#define MXC_PSEUDO_IRQ_SD2_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_CD)
#define MXC_PSEUDO_IRQ_SD2_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_WP)
#define MXC_PSEUDO_IRQ_POWER_KEY (MXC_PSEUDO_IO_BASE + MCU_INT_POWER_KEY)
#define MXC_PSEUDO_IRQ_KEYPAD (MXC_PSEUDO_IO_BASE + MCU_INT_KEYPAD)
#define MXC_PSEUDO_IRQ_RTC (MXC_PSEUDO_IO_BASE + MCU_INT_RTC)
#define MXC_PSEUDO_IRQ_TS_ADC (MXC_PSEUDO_IO_BASE + MCU_INT_TS_ADC)
/*!
* @name debug board parameters
*/
/*! @{ */
/*!
* Base address of debug board
*/
#define DEBUG_BASE_ADDRESS CS5_BASE_ADDR
/* External ethernet LAN9217 base address */
#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS
/* External UART */
#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x08000)
#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000)
#define BOARD_IO_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
/* LED switchs */
#define LED_SWITCH_REG 0x00
/* buttons */
#define SWITCH_BUTTON_REG 0x08
/* status, interrupt */
#define INTR_STATUS_REG 0x10
#define INTR_RESET_REG 0x20
/*CPLD configuration*/
#define CONFIG1_REG 0x28
#define CONFIG2_REG 0x30
/*interrupt mask */
#define INTR_MASK_REG 0x38
/* magic word for debug CPLD */
#define MAGIC_NUMBER1_REG 0x40
#define MAGIC_NUMBER2_REG 0x48
/* CPLD code version */
#define CPLD_CODE_VER_REG 0x50
/* magic word for debug CPLD */
#define MAGIC3_NUMBER3_REG 0x58
/* module reset register*/
#define CONTROL_REG 0x60
/* CPU ID and Personality ID*/
#define IDENT_REG 0x68
/* For interrupts like xuart, enet etc */
#define EXPIO_PARENT_INT MX35_PIN_GPIO1_1
#define EXPIO_INT_ENET_INT (MXC_BOARD_IRQ_START + 0)
#define EXPIO_INT_XUARTA_INT (MXC_BOARD_IRQ_START + 1)
#define EXPIO_INT_XUARTB_INT (MXC_BOARD_IRQ_START + 2)
#define EXPIO_INT_BUTTONA_INT (MXC_BOARD_IRQ_START + 3)
#define EXPIO_INT_BUTTONB_INT (MXC_BOARD_IRQ_START + 4)
/*! This is System IRQ used by LAN9217 for interrupt generation taken
* from platform.h
*/
#define LAN9217_IRQ EXPIO_INT_ENET_INT
/*! This is base virtual address of debug board*/
extern unsigned int mx35_3stack_board_io;
#define MXC_BD_LED1 (1)
#define MXC_BD_LED2 (1 << 1)
#define MXC_BD_LED3 (1 << 2)
#define MXC_BD_LED4 (1 << 3)
#define MXC_BD_LED5 (1 << 4)
#define MXC_BD_LED6 (1 << 5)
#define MXC_BD_LED7 (1 << 6)
#define MXC_BD_LED8 (1 << 7)
#define MXC_BD_LED_ON(led)
#define MXC_BD_LED_OFF(led)
/*! @} */
#define AHB_FREQ 133000000
#define IPG_FREQ 66500000
extern void mx35_3stack_gpio_init(void) __init;
extern void gpio_tsc_active(void);
extern void gpio_tsc_inactive(void);
extern unsigned int sdhc_get_card_det_status(struct device *dev);
extern int sdhc_write_protect(struct device *dev);
extern void gpio_can_active(int id);
extern void gpio_can_inactive(int id);
extern struct flexcan_platform_data flexcan_data[];
extern int __init mx35_3stack_init_mc13892(void);
extern int __init mx35_3stack_init_mc9s08dz60(void);
#endif /* CONFIG_MACH_MX35_3DS */
#endif /* __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__ */

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arch/arm/mach-mx35/cpu.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx35/cpu.c
*
* @brief This file contains the CPU initialization code.
*
* @ingroup MSL_MX35
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <asm/hardware/cache-l2x0.h>
/*!
* CPU initialization. It is called by fixup_mxc_board()
*/
void __init mxc_cpu_init(void)
{
/* Setup Peripheral Port Remap register for AVIC */
asm("ldr r0, =0xC0000015 \n\
mcr p15, 0, r0, c15, c2, 4");
/*TODO:Add code to check chip version */
if (!system_rev)
mxc_set_system_rev(0x35, CHIP_REV_1_0);
}
/*!
* Post CPU init code
*
* @return 0 always
*/
static int __init post_cpu_init(void)
{
void *l2_base;
unsigned long aips_reg;
/* Initialize L2 cache */
l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
if (l2_base)
l2x0_init(l2_base, 0x00030024, 0x00000000);
/*
* S/W workaround: Clear the off platform peripheral modules
* Supervisor Protect bit for SDMA to access them.
*/
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
return 0;
}
postcore_initcall(post_cpu_init);

430
arch/arm/mach-mx35/crm_regs.h Normal file
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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX35_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX35_CRM_REGS_H__
#define CKIH_CLK_FREQ 24000000
#define CKIE_CLK_FREQ 24576000
#define CKIL_CLK_FREQ 32000
#define CKIL_EXT_FREQ 32768
#define MXC_CCM_BASE ((char *)IO_ADDRESS(CCM_BASE_ADDR))
/* Register addresses */
#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x0C)
#define MXC_CCM_PDR3 (MXC_CCM_BASE + 0x10)
#define MXC_CCM_PDR4 (MXC_CCM_BASE + 0x14)
#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x18)
#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x1C)
#define MXC_CCM_PPCTL (MXC_CCM_BASE + 0x20)
#define MXC_CCM_ACMR (MXC_CCM_BASE + 0x24)
#define MXC_CCM_COSR (MXC_CCM_BASE + 0x28)
#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x2C)
#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x30)
#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x34)
#define MXC_CCM_CGR3 (MXC_CCM_BASE + 0x38)
#define MXC_CCM_RESV (MXC_CCM_BASE + 0x3C)
#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x40)
#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x44)
#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x48)
#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x4C)
#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x50)
#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x54)
#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x58)
#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x5C)
#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x60)
#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x64)
#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x68)
#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x6C)
#define MXC_CCM_PMCR2 (MXC_CCM_BASE + 0x70)
/* Register bit definitions */
#define MXC_CCM_CCMR_WFI (1 << 30)
#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
#define MXC_CCM_CCMR_VSTBY (1 << 28)
#define MXC_CCM_CCMR_WBEN (1 << 27)
#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
#define MXC_CCM_CCMR_ROMW_OFFSET 18
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
#define MXC_CCM_CCMR_RAMW_OFFSET 21
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
#define MXC_CCM_CCMR_LPM_OFFSET 14
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
#define MXC_CCM_CCMR_UPE (1 << 9)
#define MXC_CCM_CCMR_MPE (1 << 3)
#define MXC_CCM_PDR0_PER_SEL (1 << 26)
#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
#define MXC_CCM_PDR0_AUTO_CON 0x1
#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
/* Extra definitions for Chip Version 2*/
#define MXC_CCM_PDR2_CSI_PODF_MASK_V2 (0x3F << 16)
#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR3_UART_M_U (1 << 15)
#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
/* Extra definitions for Chip Version 2 */
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK_V2 (0x3F << 16)
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK_V2 (0x3F << 8)
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK_V2 0x3F
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
/* Extra definitions for Chip Version 2 */
#define MXC_CCM_PDR4_USB_PODF_MASK_V2 (0x3F << 22)
#define MXC_CCM_PDR4_PER0_PODF_MASK_V2 (0x3F << 16)
#define MXC_CCM_PDR4_UART_PODF_MASK_V2 (0x3F << 10)
/* Bit definitions for RCSR */
#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
#define MXC_CCM_RCSR_NF16B (1 << 14)
#define MXC_CCM_RCSR_NFC_4K (1 << 9)
#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
#define MXC_CCM_PCTL_BRM 0x80000000
#define MXC_CCM_PCTL_PD_OFFSET 26
#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
#define MXC_CCM_PCTL_MFD_OFFSET 16
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
#define MXC_CCM_PCTL_MFI_OFFSET 10
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
#define MXC_CCM_PCTL_MFN_OFFSET 0
#define MXC_CCM_PCTL_MFN_MASK 0x3FF
/* Bit definitions for Audio clock mux register*/
#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
/* Extra definitions for Version 2 */
#define MXC_CCM_ACMR_CKILH_PODF0_OFFSET 16
#define MXC_CCM_ACMR_CKILH_PODF1_OFFSET 19
#define MXC_CCM_ACMR_CKILH_PODF2_OFFSET 22
#define MXC_CCM_ACMR_CKILH_PODF3_OFFSET 25
#define MXC_CCM_ACMR_CKILH_PODF_MASK 0x7
/* Bit definitions for Clock gating Register*/
#define MXC_CCM_CGR0_ASRC_OFFSET 0
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
#define MXC_CCM_CGR0_ATA_OFFSET 2
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
#define MXC_CCM_CGR0_CAN1_OFFSET 6
#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
#define MXC_CCM_CGR0_CAN2_OFFSET 8
#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
#define MXC_CCM_CGR0_CSPI1_OFFSET 10
#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
#define MXC_CCM_CGR0_CSPI2_OFFSET 12
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
#define MXC_CCM_CGR0_ECT_OFFSET 14
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
#define MXC_CCM_CGR0_EMI_OFFSET 18
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
#define MXC_CCM_CGR0_EPIT1_OFFSET 20
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
#define MXC_CCM_CGR0_EPIT2_OFFSET 22
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
#define MXC_CCM_CGR0_ESAI_OFFSET 24
#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
#define MXC_CCM_CGR1_FEC_OFFSET 0
#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
#define MXC_CCM_CGR1_GPIO1_OFFSET 2
#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
#define MXC_CCM_CGR1_GPIO2_OFFSET 4
#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
#define MXC_CCM_CGR1_GPIO3_OFFSET 6
#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
#define MXC_CCM_CGR1_GPT_OFFSET 8
#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
#define MXC_CCM_CGR1_I2C1_OFFSET 10
#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
#define MXC_CCM_CGR1_I2C2_OFFSET 12
#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
#define MXC_CCM_CGR1_I2C3_OFFSET 14
#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
#define MXC_CCM_CGR1_IPU_OFFSET 18
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
#define MXC_CCM_CGR1_KPP_OFFSET 20
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
#define MXC_CCM_CGR1_MLB_OFFSET 22
#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
#define MXC_CCM_CGR1_MSHC_OFFSET 24
#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
#define MXC_CCM_CGR1_OWIRE_OFFSET 26
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
#define MXC_CCM_CGR1_PWM_OFFSET 28
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
#define MXC_CCM_CGR1_RNGC_OFFSET 30
#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
#define MXC_CCM_CGR2_RTC_OFFSET 0
#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
#define MXC_CCM_CGR2_RTIC_OFFSET 2
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
#define MXC_CCM_CGR2_SCC_OFFSET 4
#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
#define MXC_CCM_CGR2_SDMA_OFFSET 6
#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
#define MXC_CCM_CGR2_SPBA_OFFSET 8
#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
#define MXC_CCM_CGR2_SPDIF_OFFSET 10
#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
#define MXC_CCM_CGR2_SSI1_OFFSET 12
#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
#define MXC_CCM_CGR2_SSI2_OFFSET 14
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
#define MXC_CCM_CGR2_UART1_OFFSET 16
#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
#define MXC_CCM_CGR2_UART2_OFFSET 18
#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
#define MXC_CCM_CGR2_UART3_OFFSET 20
#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
#define MXC_CCM_CGR2_USBOTG_OFFSET 22
#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
#define MXC_CCM_CGR2_WDOG_OFFSET 24
#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
#define MXC_CCM_CGR2_MAX_OFFSET 26
#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
#define MXC_CCM_CGR3_CSI_OFFSET 0
#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
#define MXC_CCM_CGR3_IIM_OFFSET 2
#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
#define MXC_CCM_CGR3_GPU2D_OFFSET 4
#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
/*
* LTR0 register offsets
*/
#define MXC_CCM_LTR0_DNTHR_OFFSET 16
#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
#define MXC_CCM_LTR0_UPTHR_OFFSET 22
#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
#define MXC_CCM_LTR0_DIV3CK_OFFSET 1
#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
/*
* LTR1 register offsets
*/
#define MXC_CCM_LTR1_PNCTHR_OFFSET 0
#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
#define MXC_CCM_LTR1_UPCNT_OFFSET 6
#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
#define MXC_CCM_LTR1_DNCNT_OFFSET 14
#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
#define MXC_CCM_LTR1_LTBRSR_OFFSET 22
#define MXC_CCM_LTR1_LTBRSR 0x400000
#define MXC_CCM_LTR1_LTBRSH 0x800000
/*
* LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
*/
#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << MXC_CCM_LTR2_WSW_OFFSET((x)))
#define MXC_CCM_LTR2_EMAC_OFFSET 0
#define MXC_CCM_LTR2_EMAC_MASK 0x1FF
/*
* LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
*/
#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << MXC_CCM_LTR3_WSW_OFFSET((x)))
#define DVSUP_TURBO 0
#define DVSUP_HIGH 1
#define DVSUP_MEDIUM 2
#define DVSUP_LOW 3
#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28)
#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28)
#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28)
#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28)
#define MXC_CCM_PMCR0_DVSUP_OFFSET 28
#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28)
#define MXC_CCM_PMCR0_DVFS_UPDATE_FINISH 0x01000000
#define MXC_CCM_PMCR0_DVFEV 0x00800000
#define MXC_CCM_PMCR0_DVFIS 0x00400000
#define MXC_CCM_PMCR0_LBMI 0x00200000
#define MXC_CCM_PMCR0_LBFL 0x00100000
#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18)
#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18)
#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18)
#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18)
#define MXC_CCM_PMCR0_LBCF_OFFSET 18
#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18)
#define MXC_CCM_PMCR0_PTVIS 0x00020000
#define MXC_CCM_PMCR0_DVFS_START 0x00010000
#define MXC_CCM_PMCR0_DVFS_START_MASK 0x1 << 16)
#define MXC_CCM_PMCR0_FSVAIM 0x00008000
#define MXC_CCM_PMCR0_FSVAI_OFFSET 13
#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13)
#define MXC_CCM_PMCR0_DPVCR 0x00001000
#define MXC_CCM_PMCR0_DPVV 0x00000800
#define MXC_CCM_PMCR0_WFIM 0x00000400
#define MXC_CCM_PMCR0_DRCE3 0x00000200
#define MXC_CCM_PMCR0_DRCE2 0x00000100
#define MXC_CCM_PMCR0_DRCE1 0x00000080
#define MXC_CCM_PMCR0_DRCE0 0x00000040
#define MXC_CCM_PMCR0_DCR 0x00000020
#define MXC_CCM_PMCR0_DVFEN 0x00000010
#define MXC_CCM_PMCR0_PTVAIM 0x00000008
#define MXC_CCM_PMCR0_PTVAI_OFFSET 1
#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1)
#define MXC_CCM_PMCR0_DPTEN 0x00000001
#define MXC_CCM_PMCR1_DVGP_OFFSET 0
#define MXC_CCM_PMCR1_DVGP_MASK (0xF)
#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7)
#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8)
#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22)
#define MXC_CCM_DCVR_ULV_OFFSET 22
#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12)
#define MXC_CCM_DCVR_LLV_OFFSET 12
#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2)
#define MXC_CCM_DCVR_ELV_OFFSET 2
#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7)
#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7
#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F
#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0
#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
#define MXC_CCM_COSR_CLKOEN (1 << 5)
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 13)
#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 13
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 10)
#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 10
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
/* extra definitions for Version 2 */
#define MXC_CCM_COSR_CKIL_CKIH_MASK (1 << 7)
#define MXC_CCM_COSR_CKIL_CKIH_OFFSET 7
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK_V2 (0x3F << 10)
/*
* PMCR0 register offsets
*/
#define MXC_CCM_PMCR0_LBFL_OFFSET 20
#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
/*
* PMCR2 register definitions
*/
#define MXC_CCM_PMCR2_OSC24M_DOWN (1 << 16)
#define MXC_CCM_PMCR2_OSC_AUDIO_DOWN (1 << 17)
#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */

804
arch/arm/mach-mx35/devices.c Normal file
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@@ -0,0 +1,804 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spba.h>
#include <mach/sdma.h>
#include "iomux.h"
#include "sdma_script_code.h"
#include "sdma_script_code_v2.h"
#include "board-mx35_3stack.h"
void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr)
{
if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) {
sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR;
sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR;
sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR;
sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR;
sdma_script_addr->mxc_sdma_uartsh_2_per_addr =
uartsh_2_per_ADDR;
sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr =
uartsh_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR;
sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR;
sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR;
sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR;
sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;
sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = spdif_2_mcu_ADDR;
sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR;
sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR;
sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr =
ext_mem__ipu_ram_ADDR;
sdma_script_addr->mxc_sdma_descrambler_addr = -1;
sdma_script_addr->mxc_sdma_start_addr =
(unsigned short *)sdma_code;
sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
sdma_script_addr->mxc_sdma_ram_code_start_addr =
RAM_CODE_START_ADDR;
} else {
sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_V2;
sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;
sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR_V2;
sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_V2;
sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_V2;
sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR_V2;
sdma_script_addr->mxc_sdma_uartsh_2_per_addr =
uartsh_2_per_ADDR_V2;
sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr =
uartsh_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_V2;
sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_V2;
sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_V2;
sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_V2;
sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_V2;
sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;
sdma_script_addr->mxc_sdma_spdif_2_mcu_addr =
spdif_2_mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_mcu_2_spdif_addr =
mcu_2_spdif_ADDR_V2;
sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR_V2;
sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr =
ext_mem__ipu_ram_ADDR_V2;
sdma_script_addr->mxc_sdma_descrambler_addr = -1;
sdma_script_addr->mxc_sdma_start_addr =
(unsigned short *)sdma_code_v2;
sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
sdma_script_addr->mxc_sdma_ram_code_start_addr =
RAM_CODE_START_ADDR_V2;
}
}
static void mxc_nop_release(struct device *dev)
{
/* Nothing */
}
#if defined(CONFIG_RTC_MXC) || defined(CONFIG_RTC_MXC_MODULE)
static struct resource rtc_resources[] = {
{
.start = RTC_BASE_ADDR,
.end = RTC_BASE_ADDR + 0x30,
.flags = IORESOURCE_MEM,
},
{
.start = MXC_INT_RTC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mxc_rtc_device = {
.name = "mxc_rtc",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static void mxc_init_rtc(void)
{
(void)platform_device_register(&mxc_rtc_device);
}
#else
static inline void mxc_init_rtc(void)
{
}
#endif
#if defined(CONFIG_MXC_MC9SDZ60_RTC) || defined(CONFIG_MXC_MC9SDZ60_RTC_MODULE)
static struct resource pmic_rtc_resources[] = {
{
.start = MXC_PSEUDO_IRQ_RTC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pmic_rtc_device = {
.name = "pmic_rtc",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(pmic_rtc_resources),
.resource = pmic_rtc_resources,
};
static void pmic_init_rtc(void)
{
platform_device_register(&pmic_rtc_device);
}
#else
static void pmic_init_rtc(void)
{
}
#endif
#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = WDOG1_BASE_ADDR,
.end = WDOG1_BASE_ADDR + 0x30,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mxc_wdt_device = {
.name = "mxc_wdt",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
static void mxc_init_wdt(void)
{
(void)platform_device_register(&mxc_wdt_device);
}
#else
static inline void mxc_init_wdt(void)
{
}
#endif
#if defined(CONFIG_MXC_IPU) || defined(CONFIG_MXC_IPU_MODULE)
static struct mxc_ipu_config mxc_ipu_data = {
.rev = 2,
};
static struct resource ipu_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR,
.end = IPU_CTRL_BASE_ADDR + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
.start = MXC_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
},
{
.start = MXC_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mxc_ipu_device = {
.name = "mxc_ipu",
.id = -1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxc_ipu_data,
},
.num_resources = ARRAY_SIZE(ipu_resources),
.resource = ipu_resources,
};
static void mxc_init_ipu(void)
{
platform_device_register(&mxc_ipu_device);
}
#else
static inline void mxc_init_ipu(void)
{
}
#endif
/* SPI controller and device data */
#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)
#ifdef CONFIG_SPI_MXC_SELECT1
/*!
* Resource definition for the CSPI1
*/
static struct resource mxcspi1_resources[] = {
[0] = {
.start = CSPI1_BASE_ADDR,
.end = CSPI1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_CSPI1,
.end = MXC_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC CSPI1 */
static struct mxc_spi_master mxcspi1_data = {
.maxchipselect = 4,
.spi_version = 7,
};
/*! Device Definition for MXC CSPI1 */
static struct platform_device mxcspi1_device = {
.name = "mxc_spi",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxcspi1_data,
},
.num_resources = ARRAY_SIZE(mxcspi1_resources),
.resource = mxcspi1_resources,
};
#endif /* CONFIG_SPI_MXC_SELECT1 */
#ifdef CONFIG_SPI_MXC_SELECT2
/*!
* Resource definition for the CSPI2
*/
static struct resource mxcspi2_resources[] = {
[0] = {
.start = CSPI2_BASE_ADDR,
.end = CSPI2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_CSPI2,
.end = MXC_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC CSPI2 */
static struct mxc_spi_master mxcspi2_data = {
.maxchipselect = 4,
.spi_version = 7,
};
/*! Device Definition for MXC CSPI2 */
static struct platform_device mxcspi2_device = {
.name = "mxc_spi",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxcspi2_data,
},
.num_resources = ARRAY_SIZE(mxcspi2_resources),
.resource = mxcspi2_resources,
};
#endif /* CONFIG_SPI_MXC_SELECT2 */
static inline void mxc_init_spi(void)
{
/* SPBA configuration for CSPI2 - MCU is set */
spba_take_ownership(SPBA_CSPI2, SPBA_MASTER_A);
#ifdef CONFIG_SPI_MXC_SELECT1
if (platform_device_register(&mxcspi1_device) < 0)
printk(KERN_ERR "Error: Registering the SPI Controller_1\n");
#endif /* CONFIG_SPI_MXC_SELECT1 */
#ifdef CONFIG_SPI_MXC_SELECT2
if (platform_device_register(&mxcspi2_device) < 0)
printk(KERN_ERR "Error: Registering the SPI Controller_2\n");
#endif /* CONFIG_SPI_MXC_SELECT2 */
}
#else
static inline void mxc_init_spi(void)
{
}
#endif
/* I2C controller and device data */
#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
#ifdef CONFIG_I2C_MXC_SELECT1
/*!
* Resource definition for the I2C1
*/
static struct resource mxci2c1_resources[] = {
[0] = {
.start = I2C_BASE_ADDR,
.end = I2C_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C,
.end = MXC_INT_I2C,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c1_data = {
.i2c_clk = 100000,
};
#endif
/*!
* Resource definition for the I2C2
*/
static struct resource mxci2c2_resources[] = {
[0] = {
.start = I2C2_BASE_ADDR,
.end = I2C2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C2,
.end = MXC_INT_I2C2,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c2_data = {
.i2c_clk = 100000,
};
#ifdef CONFIG_I2C_MXC_SELECT3
/*!
* Resource definition for the I2C3
*/
static struct resource mxci2c3_resources[] = {
[0] = {
.start = I2C3_BASE_ADDR,
.end = I2C3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_I2C3,
.end = MXC_INT_I2C3,
.flags = IORESOURCE_IRQ,
},
};
/*! Platform Data for MXC I2C */
static struct mxc_i2c_platform_data mxci2c3_data = {
.i2c_clk = 100000,
};
#endif
/*! Device Definition for MXC I2C1 */
static struct platform_device mxci2c_devices[] = {
#ifdef CONFIG_I2C_MXC_SELECT1
{
.name = "mxc_i2c",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c1_data,
},
.num_resources = ARRAY_SIZE(mxci2c1_resources),
.resource = mxci2c1_resources,},
#endif
{
.name = "mxc_i2c_slave",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c2_data,
},
.num_resources = ARRAY_SIZE(mxci2c2_resources),
.resource = mxci2c2_resources,},
#ifdef CONFIG_I2C_MXC_SELECT3
{
.name = "mxc_i2c",
.id = 2,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxci2c3_data,
},
.num_resources = ARRAY_SIZE(mxci2c3_resources),
.resource = mxci2c3_resources,},
#endif
};
static inline void mxc_init_i2c(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) {
if (platform_device_register(&mxci2c_devices[i]) < 0)
dev_err(&mxci2c_devices[i].dev,
"Unable to register I2C device\n");
}
}
#else
static inline void mxc_init_i2c(void)
{
}
#endif
struct mxc_gpio_port mxc_gpio_ports[] = {
[0] = {
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START
},
[1] = {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32
},
[2] = {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.irq_high = 0,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
}
};
int __init mxc_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
}
static struct platform_device mxc_dma_device = {
.name = "mxc_dma",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
};
static inline void mxc_init_dma(void)
{
(void)platform_device_register(&mxc_dma_device);
}
static struct resource spdif_resources[] = {
{
.start = SPDIF_BASE_ADDR,
.end = SPDIF_BASE_ADDR + 0x50,
.flags = IORESOURCE_MEM,
},
};
static struct mxc_spdif_platform_data mxc_spdif_data = {
.spdif_tx = 1,
.spdif_rx = 1,
.spdif_clk_44100 = 3, /* spdif_ext_clk source for 44.1KHz */
.spdif_clk_48000 = 0, /* audio osc source */
.spdif_clkid = 0,
.spdif_clk = NULL, /* spdif bus clk */
};
static struct platform_device mxc_alsa_spdif_device = {
.name = "mxc_alsa_spdif",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxc_spdif_data,
},
.num_resources = ARRAY_SIZE(spdif_resources),
.resource = spdif_resources,
};
static inline void mxc_init_spdif(void)
{
mxc_spdif_data.spdif_clk = clk_get(NULL, "spdif_ipg_clk");
clk_put(mxc_spdif_data.spdif_clk);
mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_clk");
clk_put(mxc_spdif_data.spdif_core_clk);
mxc_spdif_data.spdif_audio_clk = clk_get(NULL, "spdif_audio_clk");
clk_put(mxc_spdif_data.spdif_audio_clk);
platform_device_register(&mxc_alsa_spdif_device);
}
static struct platform_device mxc_alsa_surround_device = {
.name = "imx-3stack-wm8580",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
};
static void mxc_init_surround_audio(void)
{
platform_device_register(&mxc_alsa_surround_device);
}
static struct mxc_audio_platform_data mxc_bt_audio_data;
static struct platform_device mxc_bt_alsa_device = {
.name = "imx-3stack-bt",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxc_bt_audio_data,
},
};
static void mxc_init_bt_audio(void)
{
mxc_bt_audio_data.src_port = 2;
mxc_bt_audio_data.ext_port = 5;
mxc_bt_audio_data.ext_ram = 1;
platform_device_register(&mxc_bt_alsa_device);
}
static struct resource asrc_resources[] = {
{
.start = ASRC_BASE_ADDR,
.end = ASRC_BASE_ADDR + 0x9C,
.flags = IORESOURCE_MEM,
},
};
static struct mxc_asrc_platform_data mxc_asrc_data;
static struct platform_device mxc_asrc_device = {
.name = "mxc_asrc",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &mxc_asrc_data,
},
.num_resources = ARRAY_SIZE(asrc_resources),
.resource = asrc_resources,
};
static inline void mxc_init_asrc(void)
{
if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1)
mxc_asrc_data.channel_bits = 3;
else
mxc_asrc_data.channel_bits = 4;
mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
clk_put(mxc_asrc_data.asrc_core_clk);
mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_audio_clk");
clk_set_rate(mxc_asrc_data.asrc_audio_clk, 768000);
clk_put(mxc_asrc_data.asrc_audio_clk);
platform_device_register(&mxc_asrc_device);
}
#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
static struct resource flexcan1_resources[] = {
{
.start = CAN1_BASE_ADDR,
.end = CAN1_BASE_ADDR + 0x97F,
.flags = IORESOURCE_MEM,},
{
.start = MXC_INT_CAN1,
.end = MXC_INT_CAN1,
.flags = IORESOURCE_IRQ,}
};
static struct resource flexcan2_resources[] = {
{
.start = CAN2_BASE_ADDR,
.end = CAN2_BASE_ADDR + 0x97F,
.flags = IORESOURCE_MEM,},
{
.start = MXC_INT_CAN2,
.end = MXC_INT_CAN2,
.flags = IORESOURCE_IRQ,}
};
static struct platform_device flexcan_devices[] = {
{
.name = "FlexCAN",
.id = 0,
.dev = {
.release = mxc_nop_release,
.platform_data = &flexcan_data[0],
},
.num_resources = ARRAY_SIZE(flexcan1_resources),
.resource = flexcan1_resources,},
{
.name = "FlexCAN",
.id = 1,
.dev = {
.release = mxc_nop_release,
.platform_data = &flexcan_data[1],
},
.num_resources = ARRAY_SIZE(flexcan2_resources),
.resource = flexcan2_resources,},
};
static inline void mxc_init_flexcan(void)
{
platform_device_register(&flexcan_devices[0]);
platform_device_register(&flexcan_devices[1]);
}
#else
static inline void mxc_init_flexcan(void)
{
}
#endif
#if defined(CONFIG_HW_RANDOM_FSL_RNGC) || \
defined(CONFIG_HW_RANDOM_FSL_RNGC_MODULE)
static struct resource rngc_resources[] = {
{
.start = RNGC_BASE_ADDR,
.end = RNGC_BASE_ADDR + 0x34,
.flags = IORESOURCE_MEM,
},
{
.start = MXC_INT_RNG,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device fsl_rngc_device = {
.name = "fsl_rngc",
.id = -1,
.num_resources = ARRAY_SIZE(rngc_resources),
.resource = rngc_resources,
};
static inline void mxc_init_rngc(void)
{
platform_device_register(&fsl_rngc_device);
}
#else
static inline void mxc_init_rngc(void)
{
}
#endif
#if defined(CONFIG_MXC_IIM) || defined(CONFIG_MXC_IIM_MODULE)
static struct resource mxc_iim_resources[] = {
{
.start = IIM_BASE_ADDR,
.end = IIM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mxc_iim_device = {
.name = "mxc_iim",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(mxc_iim_resources),
.resource = mxc_iim_resources
};
static inline void mxc_init_iim(void)
{
if (platform_device_register(&mxc_iim_device) < 0)
dev_err(&mxc_iim_device.dev,
"Unable to register mxc iim device\n");
}
#else
static inline void mxc_init_iim(void)
{
}
#endif
static struct resource mxc_gpu_resources[] = {
{
.start = MXC_INT_GPU2D,
.end = MXC_INT_GPU2D,
.name = "gpu_2d_irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device gpu_device = {
.name = "mxc_gpu",
.id = 0,
.dev = {
.release = mxc_nop_release,
},
.num_resources = ARRAY_SIZE(mxc_gpu_resources),
.resource = mxc_gpu_resources,
};
static void __init mxc_init_gpu(void)
{
platform_device_register(&gpu_device);
}
int __init mxc_init_devices(void)
{
mxc_init_wdt();
mxc_init_ipu();
mxc_init_spi();
mxc_init_i2c();
pmic_init_rtc();
mxc_init_rtc();
mxc_init_dma();
mxc_init_bt_audio();
mxc_init_spdif();
mxc_init_surround_audio();
mxc_init_asrc();
mxc_init_flexcan();
mxc_init_rngc();
mxc_init_iim();
mxc_init_gpu();
/* SPBA configuration for SSI2 - SDMA and MCU are set */
spba_take_ownership(SPBA_SSI2, SPBA_MASTER_C | SPBA_MASTER_A);
return 0;
}

1046
arch/arm/mach-mx35/dma.c Normal file
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606
arch/arm/mach-mx35/dvfs.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* @file dvfs.c
*
* @brief A simplied driver for the Freescale Semiconductor MXC DVFS module.
*
* Upon initialization, the DVFS driver initializes the DVFS hardware
* sets up driver nodes attaches to the DVFS interrupt and initializes internal
* data structures. When the DVFS interrupt occurs the driver checks the cause
* of the interrupt (lower frequency, increase frequency or emergency) and
* changes the CPU voltage according to translation table that is loaded into
* the driver.
*
* @ingroup PM
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include "crm_regs.h"
/*
* The frequency of div_3_clk will affect the dvfs sample rate..
*/
#define DVFS_DIV3CK (3 << MXC_CCM_LTR0_DIV3CK_OFFSET)
/*
* Panic threshold. Panic frequency change request
* will be sent if DVFS counter value will be more than this value.
*/
#define DVFS_PNCTHR (63 << MXC_CCM_LTR1_PNCTHR_OFFSET)
/*
* Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add
*/
#define DVFS_LTBRSR (1 << MXC_CCM_LTR1_LTBRSR_OFFSET)
/* EMAC defines how many samples are included in EMA calculation */
#define DVFS_EMAC (0x20 << MXC_CCM_LTR2_EMAC_OFFSET)
/*
* Frequency increase threshold. Increase frequency change request
* will be sent if DVFS counter value will be more than this value.
*/
#define DVFS_UPTHR(val) (val << MXC_CCM_LTR0_UPTHR_OFFSET)
/*
* Frequency decrease threshold. Decrease frequency change request
* will be sent if DVFS counter value will be less than this value.
*/
#define DVFS_DNTHR(val) (val << MXC_CCM_LTR0_DNTHR_OFFSET)
/*
* DNCNT defines the amount of times the down threshold should be exceeded
* before DVFS will trigger frequency decrease request.
*/
#define DVFS_DNCNT(val) (val << MXC_CCM_LTR1_DNCNT_OFFSET)
/*
* UPCNT defines the amount of times the up threshold should be exceeded
* before DVFS will trigger frequency increase request.
*/
#define DVFS_UPCNT(val) (val << MXC_CCM_LTR1_UPCNT_OFFSET)
#define DVFS_DVSUP(val) (val << MXC_CCM_PMCR0_DVSUP_OFFSET)
#define MXC_DVFS_MAX_WP_NUM 2
enum {
FSVAI_FREQ_NOCHANGE = 0x0,
FSVAI_FREQ_INCREASE,
FSVAI_FREQ_DECREASE,
FSVAI_FREQ_EMERG,
};
struct dvfs_wp {
unsigned long cpu_rate;
u32 core_voltage;
u32 dvsup;
u32 dnthr;
u32 upthr;
u32 dncnt;
u32 upcnt;
};
/* the default working points for MX35 TO2 DVFS. */
static struct dvfs_wp dvfs_wp_tbl[MXC_DVFS_MAX_WP_NUM] = {
{399000000, 1200000, DVFS_DVSUP(DVSUP_LOW), DVFS_DNTHR(18),
DVFS_UPTHR(31), DVFS_DNCNT(0x33),
DVFS_UPCNT(0x33)},
/* TBD: Need to set default voltage according to published data sheet */
{532000000, 1350000, DVFS_DVSUP(DVSUP_TURBO), DVFS_DNTHR(18),
DVFS_UPTHR(30), DVFS_DNCNT(0x33),
DVFS_UPCNT(0x33)}
};
static u8 dvfs_wp_num = MXC_DVFS_MAX_WP_NUM;
/* Used for tracking the number of interrupts */
static u32 dvfs_nr_up[MXC_DVFS_MAX_WP_NUM];
static u32 dvfs_nr_dn[MXC_DVFS_MAX_WP_NUM];
static unsigned long stored_cpu_rate; /* cpu rate before DVFS starts */
static u32 stored_pmcr0;
static int dvfs_is_active; /* indicate DVFS is active or not */
static struct delayed_work dvfs_work;
/*
* Clock structures
*/
static struct clk *cpu_clk;
static struct regulator *core_reg;
const static u8 ltr_gp_weight[] = {
0, /* 0 */
0,
0,
0,
0,
0, /* 5 */
0,
0,
0,
0,
0, /* 10 */
0,
0,
0,
0,
0, /* 15 */
};
DEFINE_SPINLOCK(mxc_dvfs_lock);
/*!
* This function sets the weight of general purpose signals
* @param gp_id number of general purpose bit
* @param weight the weight of the general purpose bit
*/
static void set_gp_weight(int gp_id, u8 weight)
{
u32 reg;
if (gp_id < 9) {
reg = __raw_readl(MXC_CCM_LTR3);
reg = (reg & ~(MXC_CCM_LTR3_WSW_MASK(gp_id))) |
(weight << MXC_CCM_LTR3_WSW_OFFSET(gp_id));
__raw_writel(reg, MXC_CCM_LTR3);
} else if (gp_id < 16) {
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_WSW_MASK(gp_id))) |
(weight << MXC_CCM_LTR2_WSW_OFFSET(gp_id));
__raw_writel(reg, MXC_CCM_LTR2);
}
}
/*!
* This function sets upper threshold, lower threshold,
* up-counter, down-counter for load tracking.
* @param upthr upper threshold
* @param dnthr lower threshold
* @param upcnt up counter
* @param dncnt down counter
*/
static void set_ltr_thres_counter(u32 upthr, u32 dnthr, u32 upcnt, u32 dncnt)
{
u32 reg;
reg = __raw_readl(MXC_CCM_LTR0);
reg =
(reg &
~(MXC_CCM_LTR0_UPTHR_MASK |
MXC_CCM_LTR0_DNTHR_MASK)) | upthr | dnthr;
__raw_writel(reg, MXC_CCM_LTR0);
reg = __raw_readl(MXC_CCM_LTR1);
reg =
(reg &
~(MXC_CCM_LTR1_UPCNT_MASK |
MXC_CCM_LTR1_DNCNT_MASK)) | upcnt | dncnt;
__raw_writel(reg, MXC_CCM_LTR1);
}
/*!
* This function is called for module initialization.
* It sets up the DVFS hardware.
* It sets default values for DVFS thresholds and counters. The default
* values was chosen from a set of different reasonable values. They was tested
* and the default values in the driver gave the best results.
* More work should be done to find optimal values.
*
* @return 0 if successful; non-zero otherwise.
*
*/
static int init_dvfs_controller(void)
{
u32 i, reg;
/* setup LTR0 */
reg = __raw_readl(MXC_CCM_LTR0);
reg = (reg & ~(MXC_CCM_LTR0_DIV3CK_MASK)) | DVFS_DIV3CK;
__raw_writel(reg, MXC_CCM_LTR0);
/* set up LTR1 */
reg = __raw_readl(MXC_CCM_LTR1);
reg = (reg & ~(MXC_CCM_LTR1_PNCTHR_MASK | MXC_CCM_LTR1_LTBRSR_MASK));
reg = reg | DVFS_PNCTHR | DVFS_LTBRSR;
__raw_writel(reg, MXC_CCM_LTR1);
/* setup LTR2 */
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC;
__raw_writel(reg, MXC_CCM_LTR2);
/* Set general purpose weights to 0 */
for (i = 0; i < 16; i++)
set_gp_weight(i, ltr_gp_weight[i]);
/* ARM interrupt, mask load buf full interrupt */
reg = __raw_readl(MXC_CCM_PMCR0);
reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI;
__raw_writel(reg, MXC_CCM_PMCR0);
return 0;
}
static void dvfs_workqueue_handler(struct work_struct *work)
{
u32 pmcr0 = stored_pmcr0;
u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >>
MXC_CCM_PMCR0_FSVAI_OFFSET;
u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >>
MXC_CCM_PMCR0_DVSUP_OFFSET;
u32 curr_cpu;
u8 curr_dvfs;
if (!dvfs_is_active)
return;
if (fsvai == FSVAI_FREQ_NOCHANGE) {
/* Do nothing. Freq change is not required */
printk(KERN_WARNING "fsvai should not be 0\n");
goto exit;
}
if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) ||
((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) ||
(fsvai == FSVAI_FREQ_EMERG)))) {
/* Interrupt should be disabled in these cases according to
* the spec since DVFS is already at lowest (highest) state */
printk(KERN_WARNING "Something is wrong?\n");
goto exit;
}
/*Disable DPTC voltage update */
pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_DPVCR;
__raw_writel(pmcr0, MXC_CCM_PMCR0);
curr_cpu = clk_get_rate(cpu_clk);
for (curr_dvfs = 0; curr_dvfs < dvfs_wp_num; curr_dvfs++) {
if (dvfs_wp_tbl[curr_dvfs].cpu_rate == curr_cpu) {
if (fsvai == FSVAI_FREQ_DECREASE) {
curr_dvfs--;
dvfs_nr_dn[dvsup]++;
/*reduce frequency and then voltage */
clk_set_rate(cpu_clk,
dvfs_wp_tbl[curr_dvfs].cpu_rate);
regulator_set_voltage(core_reg,
dvfs_wp_tbl[curr_dvfs].
core_voltage,
dvfs_wp_tbl[curr_dvfs].
core_voltage);
pr_info("Decrease frequency to: %ld \n",
dvfs_wp_tbl[curr_dvfs].cpu_rate);
} else {
/*increase freq to the highest one */
curr_dvfs = dvfs_wp_num - 1;
dvfs_nr_up[dvsup]++;
/*Increase voltage and then frequency */
regulator_set_voltage(core_reg,
dvfs_wp_tbl[curr_dvfs].
core_voltage,
dvfs_wp_tbl[curr_dvfs].
core_voltage);
clk_set_rate(cpu_clk,
dvfs_wp_tbl[curr_dvfs].cpu_rate);
pr_info("Increase frequency to: %ld \n",
dvfs_wp_tbl[curr_dvfs].cpu_rate);
}
pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVSUP_MASK)
| (dvfs_wp_tbl[curr_dvfs].dvsup);
__raw_writel(pmcr0, MXC_CCM_PMCR0);
set_ltr_thres_counter(dvfs_wp_tbl[curr_dvfs].upthr,
dvfs_wp_tbl[curr_dvfs].dnthr,
dvfs_wp_tbl[curr_dvfs].upcnt,
dvfs_wp_tbl[curr_dvfs].dncnt);
break;
}
}
exit:
/* unmask interrupt */
pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_FSVAIM;
__raw_writel(pmcr0, MXC_CCM_PMCR0);
/*DVFS update finish */
pmcr0 = (pmcr0 | MXC_CCM_PMCR0_DVFS_UPDATE_FINISH);
__raw_writel(pmcr0, MXC_CCM_PMCR0);
}
static irqreturn_t dvfs_irq(int irq, void *dev_id)
{
u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
/* Config dvfs_start bit */
pmcr0 = pmcr0 | MXC_CCM_PMCR0_DVFS_START;
/*Mask interrupt */
pmcr0 = pmcr0 | MXC_CCM_PMCR0_FSVAIM;
__raw_writel(pmcr0, MXC_CCM_PMCR0);
stored_pmcr0 = pmcr0;
schedule_delayed_work(&dvfs_work, 0);
return IRQ_RETVAL(1);
}
/*!
* This function enables the DVFS module.
*/
static int start_dvfs(void)
{
u32 reg = 0;
unsigned long flags;
u8 i;
if (dvfs_is_active) {
pr_info("DVFS is already started\n");
return 0;
}
spin_lock_irqsave(&mxc_dvfs_lock, flags);
stored_cpu_rate = clk_get_rate(cpu_clk);
for (i = 0; i < dvfs_wp_num; i++) {
if (dvfs_wp_tbl[i].cpu_rate == stored_cpu_rate) {
/*Set LTR0 and LTR1 */
set_ltr_thres_counter(dvfs_wp_tbl[i].upthr,
dvfs_wp_tbl[i].dnthr,
dvfs_wp_tbl[i].upcnt,
dvfs_wp_tbl[i].dncnt);
reg = __raw_readl(MXC_CCM_PMCR0);
reg =
(reg & ~MXC_CCM_PMCR0_DVSUP_MASK) | (dvfs_wp_tbl[i].
dvsup);
/* enable dvfs and interrupt */
reg =
(reg & ~MXC_CCM_PMCR0_FSVAIM) | MXC_CCM_PMCR0_DVFEN;
__raw_writel(reg, MXC_CCM_PMCR0);
dvfs_is_active = 1;
pr_info("DVFS Starts\n");
break;
}
}
spin_unlock_irqrestore(&mxc_dvfs_lock, flags);
if (dvfs_is_active)
return 0;
else
return 1;
}
/*!
* This function disables the DVFS module.
*/
static void stop_dvfs(void)
{
u32 pmcr0;
unsigned long curr_cpu = clk_get_rate(cpu_clk);
u8 index;
if (dvfs_is_active) {
pmcr0 = __raw_readl(MXC_CCM_PMCR0);
/* disable dvfs and its interrupt */
pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVFEN) | MXC_CCM_PMCR0_FSVAIM;
__raw_writel(pmcr0, MXC_CCM_PMCR0);
if (stored_cpu_rate < curr_cpu) {
for (index = 0; index < dvfs_wp_num; index++) {
if (dvfs_wp_tbl[index].cpu_rate ==
stored_cpu_rate)
break;
}
clk_set_rate(cpu_clk, stored_cpu_rate);
regulator_set_voltage(core_reg,
dvfs_wp_tbl[index].core_voltage,
dvfs_wp_tbl[index].core_voltage);
} else if (stored_cpu_rate > curr_cpu) {
for (index = 0; index < dvfs_wp_num; index++) {
if (dvfs_wp_tbl[index].cpu_rate ==
stored_cpu_rate)
break;
}
regulator_set_voltage(core_reg,
dvfs_wp_tbl[index].core_voltage,
dvfs_wp_tbl[index].core_voltage);
clk_set_rate(cpu_clk, stored_cpu_rate);
}
dvfs_is_active = 0;
}
pr_info("DVFS is stopped\n");
}
static ssize_t dvfs_enable_store(struct sys_device *dev, struct sysdev_attribute *attr,
const char *buf, size_t size)
{
if (strstr(buf, "1") != NULL) {
if (start_dvfs() != 0)
printk(KERN_ERR "Failed to start DVFS\n");
} else if (strstr(buf, "0") != NULL) {
stop_dvfs();
}
return size;
}
static ssize_t dvfs_status_show(struct sys_device *dev, struct sysdev_attribute *attr,
char *buf)
{
int size = 0, i;
if (dvfs_is_active)
size = sprintf(buf, "DVFS is enabled\n");
else
size = sprintf(buf, "DVFS is disabled\n");
size += sprintf((buf + size), "UP:\t");
for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++)
size += sprintf((buf + size), "%d\t", dvfs_nr_up[i]);
size += sprintf((buf + size), "\n");
size += sprintf((buf + size), "DOWN:\t");
for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++)
size += sprintf((buf + size), "%d\t", dvfs_nr_dn[i]);
size += sprintf((buf + size), "\n");
return size;
}
static ssize_t dvfs_status_store(struct sys_device *dev, struct sysdev_attribute *attr,
const char *buf, size_t size)
{
if (strstr(buf, "reset") != NULL) {
int i;
for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++) {
dvfs_nr_up[i] = 0;
dvfs_nr_dn[i] = 0;
}
}
return size;
}
static SYSDEV_ATTR(enable, 0200, NULL, dvfs_enable_store);
static SYSDEV_ATTR(status, 0644, dvfs_status_show, dvfs_status_store);
static struct sysdev_class dvfs_sysclass = {
.name = "dvfs",
};
static struct sys_device dvfs_device = {
.id = 0,
.cls = &dvfs_sysclass,
};
static int dvfs_sysdev_ctrl_init(void)
{
int err;
err = sysdev_class_register(&dvfs_sysclass);
if (!err)
err = sysdev_register(&dvfs_device);
if (!err) {
err = sysdev_create_file(&dvfs_device, &attr_enable);
err = sysdev_create_file(&dvfs_device, &attr_status);
}
return err;
}
static void dvfs_sysdev_ctrl_exit(void)
{
sysdev_remove_file(&dvfs_device, &attr_enable);
sysdev_remove_file(&dvfs_device, &attr_status);
sysdev_unregister(&dvfs_device);
sysdev_class_unregister(&dvfs_sysclass);
}
static int __init dvfs_init(void)
{
int err = 0;
u8 index;
unsigned long curr_cpu;
if (cpu_is_mx35_rev(CHIP_REV_1_0) == 1) {
/*
* Don't support DVFS for auto path in TO1 because
* the voltages under 399M are all 1.2v
*/
if (!(__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON)) {
pr_info("MX35 TO1 auto path, no need to use DVFS \n");
return -1;
}
}
cpu_clk = clk_get(NULL, "cpu_clk");
curr_cpu = clk_get_rate(cpu_clk);
if (board_is_rev(BOARD_REV_2))
core_reg = regulator_get(NULL, "SW2");
else
core_reg = regulator_get(NULL, "SW3");
dvfs_is_active = 0;
/*Set voltage */
for (index = 0; index < dvfs_wp_num; index++) {
if (dvfs_wp_tbl[index].cpu_rate == curr_cpu
&& !IS_ERR(core_reg)) {
regulator_set_voltage(core_reg,
dvfs_wp_tbl[index].core_voltage,
dvfs_wp_tbl[index].core_voltage);
break;
}
}
err = init_dvfs_controller();
if (err) {
printk(KERN_ERR "DVFS: Unable to initialize DVFS");
return err;
}
INIT_DELAYED_WORK(&dvfs_work, dvfs_workqueue_handler);
/* request the DVFS interrupt */
err = request_irq(MXC_INT_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL);
if (err) {
printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt");
return err;
}
err = dvfs_sysdev_ctrl_init();
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for dvfs");
return err;
}
return err;
}
static void __exit dvfs_cleanup(void)
{
stop_dvfs();
/* release the DVFS interrupt */
free_irq(MXC_INT_DVFS, NULL);
dvfs_sysdev_ctrl_exit();
clk_put(cpu_clk);
regulator_put(core_reg);
}
module_init(dvfs_init);
module_exit(dvfs_cleanup);
MODULE_AUTHOR("Freescale Seminconductor, Inc.");
MODULE_DESCRIPTION("DVFS driver");
MODULE_LICENSE("GPL");

206
arch/arm/mach-mx35/iomux.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @defgroup GPIO_MX35 Board GPIO and Muxing Setup
* @ingroup MSL_MX35
*/
/*!
* @file mach-mx35/iomux.c
*
* @brief I/O Muxing control functions
*
* @ingroup GPIO_MX35
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
#include "iomux.h"
/*!
* IOMUX register (base) addresses
*/
#define IOMUXGPR (IO_ADDRESS(IOMUXC_BASE_ADDR))
#define IOMUXSW_MUX_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 4)
#define IOMUXSW_MUX_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x324)
#define IOMUXSW_PAD_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x328)
#define IOMUXSW_PAD_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x790)
#define IOMUXSW_INPUT_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x7A8)
#define IOMUXSW_INPUT_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x9F4)
#define MUX_PIN_NUM_MAX \
(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
#define MUX_INPUT_NUM_MUX \
(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
static DEFINE_SPINLOCK(gpio_mux_lock);
static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX];
/*!
* This function is used to configure a pin through the IOMUX module.
* FIXED ME: for backward compatible. Will be static function!
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param cfg an output function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 ret = 0;
u32 pin_index = PIN_TO_IOMUX_INDEX(pin);
void *mux_reg = IOMUXGPR + PIN_TO_IOMUX_MUX(pin);
u8 *rp;
BUG_ON(pin_index > MUX_PIN_NUM_MAX);
BUG_ON((mux_reg > IOMUXSW_MUX_END) || (mux_reg < IOMUXSW_MUX_CTL));
spin_lock(&gpio_mux_lock);
__raw_writel(cfg, mux_reg);
/*
* Log a warning if a pin changes ownership
*/
rp = iomux_pin_res_table + pin_index;
if ((cfg & *rp) && (*rp != cfg)) {
/*Console: how to do */
printk(KERN_ERR "iomux_config_mux: Warning: iomux pin"
" config changed, index=%d register=%p, "
" prev=0x%x new=0x%x\n", pin_index, mux_reg,
*rp, cfg);
ret = -EINVAL;
}
*rp = cfg;
spin_unlock(&gpio_mux_lock);
return ret;
}
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 gpio = IOMUX_TO_GPIO(pin);
int ret = iomux_config_mux(pin, cfg);
if (gpio < MXC_GPIO_IRQS) {
if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) ||
(((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) &&
((pin == MX35_PIN_GPIO1_0) || (pin == MX35_PIN_GPIO1_1) ||
(pin == MX35_PIN_GPIO2_0) || (pin == MX35_PIN_GPIO3_0))))
ret |= gpio_request(gpio, NULL);
}
return ret;
}
EXPORT_SYMBOL(mxc_request_iomux);
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 pin_index = PIN_TO_IOMUX_INDEX(pin);
u8 *rp = iomux_pin_res_table + pin_index;
u32 gpio = IOMUX_TO_GPIO(pin);
BUG_ON((pin_index > MUX_PIN_NUM_MAX));
*rp = 0;
if (gpio < MXC_GPIO_IRQS) {
if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) ||
(((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) &&
((pin == MX35_PIN_GPIO1_0) || (pin == MX35_PIN_GPIO1_1) ||
(pin == MX35_PIN_GPIO2_0) || (pin == MX35_PIN_GPIO3_0))))
gpio_free(gpio);
}
}
EXPORT_SYMBOL(mxc_free_iomux);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b #iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
{
void *pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
BUG_ON((pad_reg > IOMUXSW_PAD_END) || (pad_reg < IOMUXSW_PAD_CTL));
spin_lock(&gpio_mux_lock);
__raw_writel(config, pad_reg);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en)
{
u32 l;
spin_lock(&gpio_mux_lock);
l = __raw_readl(IOMUXGPR);
if (en)
l |= gp;
else
l &= ~gp;
__raw_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
/*!
* This function configures input path.
*
* @param input index of input select register as defined in \b
* #iomux_input_select_t
* @param config the binary value of elements defined in \b
* #iomux_input_config_t
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
{
void *reg = IOMUXSW_INPUT_CTL + (input << 2);
BUG_ON(input >= MUX_INPUT_NUM_MUX);
__raw_writel(config, reg);
}
EXPORT_SYMBOL(mxc_iomux_set_input);

295
arch/arm/mach-mx35/iomux.h Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_MX35_IOMUX_H__
#define __MACH_MX35_IOMUX_H__
#include <linux/types.h>
#include <mach/gpio.h>
#include "mx35_pins.h"
/*!
* @file mach-mx35/iomux.h
*
* @brief I/O Muxing control definitions and functions
*
* @ingroup GPIO_MX35
*/
typedef unsigned int iomux_pin_name_t;
/*!
* various IOMUX functions
*/
typedef enum iomux_pin_config {
MUX_CONFIG_FUNC = 0, /*!< used as function */
MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
} iomux_pin_cfg_t;
/*!
* various IOMUX pad functions
*/
typedef enum iomux_pad_config {
PAD_CTL_DRV_3_3V = 0x0 << 13,
PAD_CTL_DRV_1_8V = 0x1 << 13,
PAD_CTL_HYS_CMOS = 0x0 << 8,
PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
PAD_CTL_PKE_NONE = 0x0 << 7,
PAD_CTL_PKE_ENABLE = 0x1 << 7,
PAD_CTL_PUE_KEEPER = 0x0 << 6,
PAD_CTL_PUE_PUD = 0x1 << 6,
PAD_CTL_100K_PD = 0x0 << 4,
PAD_CTL_47K_PU = 0x1 << 4,
PAD_CTL_100K_PU = 0x2 << 4,
PAD_CTL_22K_PU = 0x3 << 4,
PAD_CTL_ODE_CMOS = 0x0 << 3,
PAD_CTL_ODE_OpenDrain = 0x1 << 3,
PAD_CTL_DRV_NORMAL = 0x0 << 1,
PAD_CTL_DRV_HIGH = 0x1 << 1,
PAD_CTL_DRV_MAX = 0x2 << 1,
PAD_CTL_SRE_SLOW = 0x0 << 0,
PAD_CTL_SRE_FAST = 0x1 << 0
} iomux_pad_config_t;
/*!
* various IOMUX general purpose functions
*/
typedef enum iomux_gp_func {
MUX_SDCTL_CSD0_SEL = 0x1 << 0,
MUX_SDCTL_CSD1_SEL = 0x1 << 1,
MUX_TAMPER_DETECT_EN = 0x1 << 2,
} iomux_gp_func_t;
/*!
* various IOMUX input select register index
*/
typedef enum iomux_input_select {
MUX_IN_AMX_P5_RXCLK = 0,
MUX_IN_AMX_P5_RXFS,
MUX_IN_AMX_P6_DA,
MUX_IN_AMX_P6_DB,
MUX_IN_AMX_P6_RXCLK,
MUX_IN_AMX_P6_RXFS,
MUX_IN_AMX_P6_TXCLK,
MUX_IN_AMX_P6_TXFS,
MUX_IN_CAN1_CANRX,
MUX_IN_CAN2_CANRX,
MUX_IN_CCM_32K_MUXED,
MUX_IN_CCM_PMIC_RDY,
MUX_IN_CSPI1_SS2_B,
MUX_IN_CSPI1_SS3_B,
MUX_IN_CSPI2_CLK_IN,
MUX_IN_CSPI2_DATAREADY_B,
MUX_IN_CSPI2_MISO,
MUX_IN_CSPI2_MOSI,
MUX_IN_CSPI2_SS0_B,
MUX_IN_CSPI2_SS1_B,
MUX_IN_CSPI2_SS2_B,
MUX_IN_CSPI2_SS3_B,
MUX_IN_EMI_WEIM_DTACK_B,
MUX_IN_ESDHC1_DAT4_IN,
MUX_IN_ESDHC1_DAT5_IN,
MUX_IN_ESDHC1_DAT6_IN,
MUX_IN_ESDHC1_DAT7_IN,
MUX_IN_ESDHC3_CARD_CLK_IN,
MUX_IN_ESDHC3_CMD_IN,
MUX_IN_ESDHC3_DAT0,
MUX_IN_ESDHC3_DAT1,
MUX_IN_ESDHC3_DAT2,
MUX_IN_ESDHC3_DAT3,
MUX_IN_GPIO1_IN_0,
MUX_IN_GPIO1_IN_10,
MUX_IN_GPIO1_IN_11,
MUX_IN_GPIO1_IN_1,
MUX_IN_GPIO1_IN_20,
MUX_IN_GPIO1_IN_21,
MUX_IN_GPIO1_IN_22,
MUX_IN_GPIO1_IN_2,
MUX_IN_GPIO1_IN_3,
MUX_IN_GPIO1_IN_4,
MUX_IN_GPIO1_IN_5,
MUX_IN_GPIO1_IN_6,
MUX_IN_GPIO1_IN_7,
MUX_IN_GPIO1_IN_8,
MUX_IN_GPIO1_IN_9,
MUX_IN_GPIO2_IN_0,
MUX_IN_GPIO2_IN_10,
MUX_IN_GPIO2_IN_11,
MUX_IN_GPIO2_IN_12,
MUX_IN_GPIO2_IN_13,
MUX_IN_GPIO2_IN_14,
MUX_IN_GPIO2_IN_15,
MUX_IN_GPIO2_IN_16,
MUX_IN_GPIO2_IN_17,
MUX_IN_GPIO2_IN_18,
MUX_IN_GPIO2_IN_19,
MUX_IN_GPIO2_IN_1,
MUX_IN_GPIO2_IN_20,
MUX_IN_GPIO2_IN_21,
MUX_IN_GPIO2_IN_22,
MUX_IN_GPIO2_IN_23,
MUX_IN_GPIO2_IN_24,
MUX_IN_GPIO2_IN_25,
MUX_IN_GPIO2_IN_26,
MUX_IN_GPIO2_IN_27,
MUX_IN_GPIO2_IN_28,
MUX_IN_GPIO2_IN_29,
MUX_IN_GPIO2_IN_2,
MUX_IN_GPIO2_IN_30,
MUX_IN_GPIO2_IN_31,
MUX_IN_GPIO2_IN_3,
MUX_IN_GPIO2_IN_4,
MUX_IN_GPIO2_IN_5,
MUX_IN_GPIO2_IN_6,
MUX_IN_GPIO2_IN_7,
MUX_IN_GPIO2_IN_8,
MUX_IN_GPIO2_IN_9,
MUX_IN_GPIO3_IN_0,
MUX_IN_GPIO3_IN_10,
MUX_IN_GPIO3_IN_11,
MUX_IN_GPIO3_IN_12,
MUX_IN_GPIO3_IN_13,
MUX_IN_GPIO3_IN_14,
MUX_IN_GPIO3_IN_15,
MUX_IN_GPIO3_IN_4,
MUX_IN_GPIO3_IN_5,
MUX_IN_GPIO3_IN_6,
MUX_IN_GPIO3_IN_7,
MUX_IN_GPIO3_IN_8,
MUX_IN_GPIO3_IN_9,
MUX_IN_I2C3_SCL_IN,
MUX_IN_I2C3_SDA_IN,
MUX_IN_IPU_DISPB_D0_VSYNC,
MUX_IN_IPU_DISPB_D12_VSYNC,
MUX_IN_IPU_DISPB_SD_D,
MUX_IN_IPU_SENSB_DATA_0,
MUX_IN_IPU_SENSB_DATA_1,
MUX_IN_IPU_SENSB_DATA_2,
MUX_IN_IPU_SENSB_DATA_3,
MUX_IN_IPU_SENSB_DATA_4,
MUX_IN_IPU_SENSB_DATA_5,
MUX_IN_IPU_SENSB_DATA_6,
MUX_IN_IPU_SENSB_DATA_7,
MUX_IN_KPP_COL_0,
MUX_IN_KPP_COL_1,
MUX_IN_KPP_COL_2,
MUX_IN_KPP_COL_3,
MUX_IN_KPP_COL_4,
MUX_IN_KPP_COL_5,
MUX_IN_KPP_COL_6,
MUX_IN_KPP_COL_7,
MUX_IN_KPP_ROW_0,
MUX_IN_KPP_ROW_1,
MUX_IN_KPP_ROW_2,
MUX_IN_KPP_ROW_3,
MUX_IN_KPP_ROW_4,
MUX_IN_KPP_ROW_5,
MUX_IN_KPP_ROW_6,
MUX_IN_KPP_ROW_7,
MUX_IN_OWIRE_BATTERY_LINE,
MUX_IN_SPDIF_HCKT_CLK2,
MUX_IN_SPDIF_SPDIF_IN1,
MUX_IN_UART3_UART_RTS_B,
MUX_IN_UART3_UART_RXD_MUX,
MUX_IN_USB_OTG_DATA_0,
MUX_IN_USB_OTG_DATA_1,
MUX_IN_USB_OTG_DATA_2,
MUX_IN_USB_OTG_DATA_3,
MUX_IN_USB_OTG_DATA_4,
MUX_IN_USB_OTG_DATA_5,
MUX_IN_USB_OTG_DATA_6,
MUX_IN_USB_OTG_DATA_7,
MUX_IN_USB_OTG_DIR,
MUX_IN_USB_OTG_NXT,
MUX_IN_USB_UH2_DATA_0,
MUX_IN_USB_UH2_DATA_1,
MUX_IN_USB_UH2_DATA_2,
MUX_IN_USB_UH2_DATA_3,
MUX_IN_USB_UH2_DATA_4,
MUX_IN_USB_UH2_DATA_5,
MUX_IN_USB_UH2_DATA_6,
MUX_IN_USB_UH2_DATA_7,
MUX_IN_USB_UH2_DIR,
MUX_IN_USB_UH2_NXT,
MUX_IN_USB_UH2_USB_OC,
} iomux_input_select_t;
/*!
* various IOMUX input functions
*/
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
INPUT_CTL_PATH1,
INPUT_CTL_PATH2,
INPUT_CTL_PATH3,
INPUT_CTL_PATH4,
INPUT_CTL_PATH5,
INPUT_CTL_PATH6,
INPUT_CTL_PATH7,
} iomux_input_cfg_t;
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
/*!
* Release ownership for an IO pin
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
/*!
* This function enables/disables the general purpose function for a particular
* signal.
*
* @param gp one signal as defined in \b #iomux_gp_func_t
* @param en \b #true to enable; \b #false to disable
*/
void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en);
/*!
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in \b #iomux_pin_name_t
* @param config the ORed value of elements defined in \b
* #iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
/*!
* This function configures input path.
*
* @param input index of input select register as defined in \b
* #iomux_input_select_t
* @param config the binary value of elements defined in \b
* #iomux_input_cfg_t
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
#endif

77
arch/arm/mach-mx35/mm.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
/*!
* @file mach-mx35/mm.c
*
* @brief This file creates static mapping between physical to virtual memory.
*
* @ingroup Memory_MX35
*/
/*!
* This structure defines the MX35 memory map.
*/
static struct map_desc mx35_io_desc[] __initdata = {
{
.virtual = IRAM_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX35_IRAM_BASE_ADDR),
.length = MX35_IRAM_SIZE,
.type = MT_DEVICE_NONSHARED},
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE,
.type = MT_DEVICE},
{
.virtual = NFC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(NFC_BASE_ADDR),
.length = NFC_SIZE,
.type = MT_DEVICE_NONSHARED},
{
.virtual = AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
.length = AVIC_SIZE,
.type = MT_DEVICE_NONSHARED},
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED},
{
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE_NONSHARED},
{
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED},
};
/*!
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory map for
* the IO modules.
*/
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}

1260
arch/arm/mach-mx35/mx35_3stack.c Normal file
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File diff suppressed because it is too large Load Diff

161
arch/arm/mach-mx35/mx35_3stack_cpld.c Normal file
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@@ -0,0 +1,161 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include "board-mx35_3stack.h"
#include "crm_regs.h"
#include "iomux.h"
/*!
* @file mach-mx35/mx35_3stack_cpld.c
*
* @brief This file contains the board specific initialization routines.
*
* @ingroup MSL_MX35
*/
static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 expio_irq;
u32 index, mask;
desc->chip->mask(irq); /* irq = gpio irq number */
index = __raw_readw(mx35_3stack_board_io + INTR_STATUS_REG);
mask = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG);
if (unlikely(!(index & (~mask)))) {
printk(KERN_ERR "\nEXPIO: Spurious interrupt:0x%0x\n\n", index);
pr_info("CPLD IMR(0x38)=0x%x, PENDING(0x28)=0x%x\n", mask,
index);
goto out;
}
index = index & (~mask);
expio_irq = MXC_BOARD_IRQ_START;
for (; index != 0; index >>= 1, expio_irq++) {
struct irq_desc *d;
if ((index & 1) == 0)
continue;
d = irq_desc + expio_irq;
if (unlikely(!(d->handle_irq))) {
printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n",
expio_irq);
BUG(); /* oops */
}
d->handle_irq(expio_irq, d);
}
out:
desc->chip->ack(irq);
desc->chip->unmask(irq);
}
/*
* Disable an expio pin's interrupt by setting the bit in the imr.
* @param irq an expio virtual irq number
*/
static void expio_mask_irq(u32 irq)
{
u16 reg, expio = MXC_IRQ_TO_EXPIO(irq);
reg = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG);
/* mask the interrupt */
__raw_writew(reg | (1 << expio), mx35_3stack_board_io + INTR_MASK_REG);
}
/*
* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
* @param irq an expanded io virtual irq number
*/
static void expio_ack_irq(u32 irq)
{
u32 expio = MXC_IRQ_TO_EXPIO(irq);
/* clear the interrupt status */
__raw_writew(1 << expio, mx35_3stack_board_io + INTR_RESET_REG);
__raw_writew(0, mx35_3stack_board_io + INTR_RESET_REG);
/* mask the interrupt */
expio_mask_irq(irq);
}
/*
* Enable a expio pin's interrupt by clearing the bit in the imr.
* @param irq a expio virtual irq number
*/
static void expio_unmask_irq(u32 irq)
{
u16 reg, expio = MXC_IRQ_TO_EXPIO(irq);
reg = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG);
/* unmask the interrupt */
__raw_writew(reg & (~(1 << expio)),
mx35_3stack_board_io + INTR_MASK_REG);
}
static struct irq_chip expio_irq_chip = {
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
};
static int __init mxc_expio_init(void)
{
int i;
mx35_3stack_board_io = (u32) ioremap(BOARD_IO_ADDR, SZ_4K);
if (mx35_3stack_board_io == 0)
return -ENOMEM;
if ((__raw_readw(mx35_3stack_board_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
(__raw_readw(mx35_3stack_board_io + MAGIC_NUMBER2_REG) != 0x5555))
return -ENODEV;
pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
readw(mx35_3stack_board_io + CPLD_CODE_VER_REG));
/*
* Configure INT line as GPIO input
*/
mxc_request_iomux(EXPIO_PARENT_INT, MUX_CONFIG_FUNC);
gpio_request(IOMUX_TO_GPIO(EXPIO_PARENT_INT), NULL);
gpio_direction_input(IOMUX_TO_GPIO(EXPIO_PARENT_INT));
/* disable the interrupt and clear the status */
__raw_writew(0, mx35_3stack_board_io + INTR_MASK_REG);
__raw_writew(0xFFFF, mx35_3stack_board_io + INTR_RESET_REG);
__raw_writew(0, mx35_3stack_board_io + INTR_RESET_REG);
__raw_writew(0x1F, mx35_3stack_board_io + INTR_MASK_REG);
for (i = MXC_BOARD_IRQ_START; i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS);
i++) {
set_irq_chip(i, &expio_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
set_irq_type(IOMUX_TO_IRQ(EXPIO_PARENT_INT), IRQF_TRIGGER_LOW);
set_irq_chained_handler(IOMUX_TO_IRQ(EXPIO_PARENT_INT),
mxc_expio_irq_handler);
return 0;
}
arch_initcall(mxc_expio_init);

1378
arch/arm/mach-mx35/mx35_3stack_gpio.c Normal file
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372
arch/arm/mach-mx35/mx35_3stack_irq.c Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mfd/mc9s08dz60/pmic.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/bitops.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <mach/gpio.h>
#include "board-mx35_3stack.h"
#include "iomux.h"
/*!
* @file mach-mx35/mx35_3stack_irq.c
*
* @brief This file contains the board specific initialization routines.
*
* @ingroup MSL_MX35
*/
#ifdef CONFIG_MXC_PSEUDO_IRQS
/*
* The interrupt status and mask variables.
*/
static unsigned long pseudo_irq_pending;
static unsigned long pseudo_irq_enable;
static unsigned long pseudo_irq_wakeup;
static unsigned long pseudo_suspend;
static atomic_t pseudo_irq_state = ATOMIC_INIT(0);
/*
* The declaration of handler of two work queue.
* The one is the work queue to indentify the events from MCU.
* The another is the work queue to change the events mask.
*/
static void mcu_event_handler(struct work_struct *work);
static void mcu_state_handler(struct work_struct *work);
static void mcu_event_delay(unsigned long data);
/*!
* The work structure for mcu events.
*/
static DECLARE_WORK(mcu_event_ws, mcu_event_handler);
static DECLARE_WORK(mcu_state_ws, mcu_state_handler);
static DEFINE_TIMER(mcu_delay_timer, mcu_event_delay, HZ, 0);
static inline void mxc_pseudo_irq_ack(void)
{
disable_irq(MXC_PSEUDO_PARENT);
atomic_set(&pseudo_irq_state, 0);
}
static inline void mxc_pseudo_irq_trigger(void)
{
if (!atomic_xchg(&pseudo_irq_state, 1))
enable_irq(MXC_PSEUDO_PARENT);
}
/*
* mask a pseudo interrupt by setting the bit in the mask variable.
* @param irq a pseudo virtual irq number
*/
static void pseudo_mask_irq(u32 irq)
{
int index = irq - MXC_PSEUDO_IO_BASE;
clear_bit(index, &pseudo_irq_enable);
}
/*
* disable a pseudo interrupt by triggerring a work queue
* @param irq a pseudo virtual irq number
*/
static void pseudo_disable_irq(u32 irq)
{
struct irq_desc *desc = irq_desc + irq;
desc->chip->mask(irq);
desc->status |= IRQ_MASKED;
schedule_work(&mcu_state_ws);
}
/*
* Acknowledge a pseudo interrupt by clearing the bit in the isr variable.
* @param irq a pseudo virtual irq number
*/
static void pseudo_ack_irq(u32 irq)
{
int index = irq - MXC_PSEUDO_IO_BASE;
/* clear the interrupt status */
clear_bit(index, &pseudo_irq_pending);
}
/*
* unmask a pseudo interrupt by clearing the bit in the imr.
* @param irq a pseudo virtual irq number
*/
static void pseudo_unmask_irq(u32 irq)
{
int index = irq - MXC_PSEUDO_IO_BASE;
set_bit(index, &pseudo_irq_enable);
if (test_bit(index, &pseudo_irq_pending))
mxc_pseudo_irq_trigger();
}
/*
* Enable a pseudo interrupt by triggerring a work queue
* @param irq a pseudo virtual irq number
*/
static void pseudo_enable_irq(u32 irq)
{
struct irq_desc *desc = irq_desc + irq;
desc->chip->unmask(irq);
desc->status &= ~IRQ_MASKED;
schedule_work(&mcu_state_ws);
}
/*
* set pseudo irq as a wake-up source.
* @param irq a pseudo virtual irq number
* @param enable enable as wake-up if equal to non-ero
* @return This function return 0 on success
*/
static int pseudo_set_wake_irq(u32 irq, u32 enable)
{
int index = irq - MXC_PSEUDO_IO_BASE;
if (index >= MXC_MAX_PSEUDO_IO_LINES)
return -ENODEV;
if (enable) {
if (!pseudo_irq_wakeup)
enable_irq_wake(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0));
pseudo_irq_wakeup |= (1 << index);
} else {
pseudo_irq_wakeup &= ~(1 << index);
if (!pseudo_irq_wakeup)
disable_irq_wake(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0));
}
return 0;
}
static struct irq_chip pseudo_irq_chip = {
.ack = pseudo_ack_irq,
.mask = pseudo_mask_irq,
.disable = pseudo_disable_irq,
.unmask = pseudo_unmask_irq,
.enable = pseudo_enable_irq,
.set_wake = pseudo_set_wake_irq,
};
static void mxc_pseudo_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 pseudo_irq;
u32 index, mask;
desc->chip->mask(irq);
mxc_pseudo_irq_ack();
mask = pseudo_irq_enable;
index = pseudo_irq_pending;
if (unlikely(!(index & mask))) {
printk(KERN_ERR "\nPseudo IRQ: Spurious interrupt:0x%0x\n\n",
index);
pr_info("IEN=0x%x, PENDING=0x%x\n", mask, index);
return;
}
index = index & mask;
pseudo_irq = MXC_PSEUDO_IO_BASE;
for (; index != 0; index >>= 1, pseudo_irq++) {
struct irq_desc *d;
if ((index & 1) == 0)
continue;
d = irq_desc + pseudo_irq;
if (unlikely(!(d->handle_irq))) {
printk(KERN_ERR "\nPseudo irq: %d unhandeled\n",
pseudo_irq);
BUG(); /* oops */
}
d->handle_irq(pseudo_irq, d);
d->chip->ack(pseudo_irq);
}
}
static void mcu_event_delay(unsigned long data)
{
schedule_work(&mcu_event_ws);
}
/*!
* This function is called when mcu interrupt occurs on the processor.
* It is the interrupt handler for the mcu.
*
* @param irq the irq number
* @param dev_id the pointer on the device
*
* @return The function returns IRQ_HANDLED when handled.
*/
static irqreturn_t mcu_irq_handler(int irq, void *dev_id)
{
disable_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0));
if (pseudo_suspend)
mod_timer(&mcu_delay_timer, jiffies + HZ);
else
schedule_work(&mcu_event_ws);
return IRQ_HANDLED;
}
/*!
* This function is the work handler of mcu interrupt.
* It reads the events status and trigger the pseudo irq.
*/
static void mcu_event_handler(struct work_struct *work)
{
int i, err;
unsigned int flag1, flag2;
/* read int flags and ack int */
for (i = 0; i < 3; i++) {
err = mcu_pmic_read_reg(REG_MCU_INT_FLAG_1, &flag1, 0xFFFFFFFF);
err |= mcu_pmic_read_reg(REG_MCU_INT_FLAG_2,
&flag2, 0xFFFFFFFF);
err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_1, 0, 0xFFFFFFFF);
err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_2, 0, 0xFFFFFFFF);
if (err == 0)
break;
}
if (i >= 3) {
printk(KERN_ERR "Reads MCU event fail\n");
goto no_new_events;
}
for (i = 0; flag1 && (i < MCU_INT_RTC); i++, flag1 >>= 1)
if (flag1 & 1)
set_bit(i, &pseudo_irq_pending);
for (i = MCU_INT_RTC; flag2 && (i <= MCU_INT_KEYPAD); i++, flag2 >>= 1)
if (flag2 & 1)
set_bit(i, &pseudo_irq_pending);
no_new_events:
if (pseudo_irq_pending & pseudo_irq_enable)
mxc_pseudo_irq_trigger();
enable_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0));
}
static void mcu_state_handler(struct work_struct *work)
{
int err, i;
unsigned int event1, event2;
event1 = pseudo_irq_enable & ((1 << MCU_INT_RTC) - 1);
event2 = pseudo_irq_enable >> MCU_INT_RTC;
for (i = 0; i < 3; i++) {
err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF);
err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF);
if (err == 0)
break;
}
if (i >= 3)
printk(KERN_ERR "Change MCU event mask fail\n");
}
static int __init mxc_pseudo_init(void)
{
int i;
/* disable the interrupt and clear the status */
pseudo_irq_pending = 0;
pseudo_irq_enable = 0;
pr_info("3-Stack Pseudo interrupt rev=0.1v\n");
for (i = MXC_PSEUDO_IO_BASE;
i < (MXC_PSEUDO_IO_BASE + MXC_MAX_PSEUDO_IO_LINES); i++) {
set_irq_chip(i, &pseudo_irq_chip);
set_irq_handler(i, handle_simple_irq);
set_irq_flags(i, IRQF_VALID);
}
set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN);
set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler);
/* Set and install PMIC IRQ handler */
mxc_request_iomux(MX35_PIN_GPIO1_0, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_GPIO1_0, PAD_CTL_PKE_NONE);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_GPIO1_0), NULL);
gpio_direction_input(IOMUX_TO_GPIO(MX35_PIN_GPIO1_0));
set_irq_type(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0), IRQF_TRIGGER_RISING);
if (request_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0), mcu_irq_handler,
0, "MCU_IRQ", 0)) {
printk(KERN_ERR "mcu request irq failed\n");
return -1;
}
return 0;
}
fs_initcall_sync(mxc_pseudo_init);
static int mxc_pseudo_irq_suspend(struct platform_device *dev,
pm_message_t mesg)
{
int err, i;
unsigned int event1, event2;
if (!pseudo_irq_wakeup)
return 0;
event1 = pseudo_irq_wakeup & ((1 << MCU_INT_RTC) - 1);
event2 = pseudo_irq_wakeup >> MCU_INT_RTC;
for (i = 0; i < 3; i++) {
err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF);
err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF);
if (err == 0)
break;
}
pseudo_suspend = 1;
return err;
}
static int mxc_pseudo_irq_resume(struct platform_device *dev)
{
if (!pseudo_irq_wakeup)
return 0;
schedule_work(&mcu_state_ws);
pseudo_suspend = 0;
return 0;
}
static struct platform_driver mxc_pseudo_irq_driver = {
.driver = {
.name = "mxc_pseudo_irq",
},
.suspend = mxc_pseudo_irq_suspend,
.resume = mxc_pseudo_irq_resume,
};
static int __init mxc_pseudo_sysinit(void)
{
return platform_driver_register(&mxc_pseudo_irq_driver);
}
late_initcall(mxc_pseudo_sysinit);
#endif /* CONFIG_MXC_PSEUDO_IRQS */

347
arch/arm/mach-mx35/mx35_3stack_pmic_mc13892.c Normal file
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@@ -0,0 +1,347 @@
/*
* mx35-3stack-pmic-mc13892.c -- i.MX35 3STACK Driver for Atlas MC13892 PMIC
*/
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/pmic_external.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc13892/core.h>
#include <mach/irqs.h>
#include "iomux.h"
/*
* Convenience conversion.
* Here atm, maybe there is somewhere better for this.
*/
#define mV_to_uV(mV) (mV * 1000)
#define uV_to_mV(uV) (uV / 1000)
#define V_to_uV(V) (mV_to_uV(V * 1000))
#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
#define STANDBYSECINV_LSH 11
#define STANDBYSECINV_WID 1
/* CPU */
static struct regulator_consumer_supply sw1_consumers[] = {
{
.supply = "cpu_vcc",
}
};
struct mc13892;
static struct regulator_init_data sw1_init = {
.constraints = {
.name = "SW1",
.min_uV = mV_to_uV(600),
.max_uV = mV_to_uV(1375),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.valid_modes_mask = 0,
.always_on = 1,
.boot_on = 1,
.initial_state = PM_SUSPEND_MEM,
.state_mem = {
.uV = 700000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
.consumer_supplies = sw1_consumers,
};
static struct regulator_init_data sw2_init = {
.constraints = {
.name = "SW2",
.min_uV = mV_to_uV(900),
.max_uV = mV_to_uV(1850),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
.initial_state = PM_SUSPEND_MEM,
.state_mem = {
.uV = 1200000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
.state_standby = {
.uV = 1000000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
}
};
static struct regulator_init_data sw3_init = {
.constraints = {
.name = "SW3",
.min_uV = mV_to_uV(1100),
.max_uV = mV_to_uV(1850),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
}
};
static struct regulator_init_data sw4_init = {
.constraints = {
.name = "SW4",
.min_uV = mV_to_uV(1100),
.max_uV = mV_to_uV(1850),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
}
};
static struct regulator_init_data viohi_init = {
.constraints = {
.name = "VIOHI",
.boot_on = 1,
}
};
static struct regulator_init_data vusb_init = {
.constraints = {
.name = "VUSB",
.boot_on = 1,
}
};
static struct regulator_init_data swbst_init = {
.constraints = {
.name = "SWBST",
}
};
static struct regulator_init_data vdig_init = {
.constraints = {
.name = "VDIG",
.min_uV = mV_to_uV(1050),
.max_uV = mV_to_uV(1800),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vpll_init = {
.constraints = {
.name = "VPLL",
.min_uV = mV_to_uV(1050),
.max_uV = mV_to_uV(1800),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vusb2_init = {
.constraints = {
.name = "VUSB2",
.min_uV = mV_to_uV(2400),
.max_uV = mV_to_uV(2775),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vvideo_init = {
.constraints = {
.name = "VVIDEO",
.min_uV = mV_to_uV(2500),
.max_uV = mV_to_uV(2775),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vaudio_init = {
.constraints = {
.name = "VAUDIO",
.min_uV = mV_to_uV(2300),
.max_uV = mV_to_uV(3000),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vsd_init = {
.constraints = {
.name = "VSD",
.min_uV = mV_to_uV(1800),
.max_uV = mV_to_uV(3150),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vcam_init = {
.constraints = {
.name = "VCAM",
.min_uV = mV_to_uV(2500),
.max_uV = mV_to_uV(3000),
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
}
};
static struct regulator_init_data vgen1_init = {
.constraints = {
.name = "VGEN1",
.min_uV = mV_to_uV(1200),
.max_uV = mV_to_uV(3150),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data vgen2_init = {
.constraints = {
.name = "VGEN2",
.min_uV = mV_to_uV(1200),
.max_uV = mV_to_uV(3150),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
}
};
static struct regulator_init_data vgen3_init = {
.constraints = {
.name = "VGEN3",
.min_uV = mV_to_uV(1800),
.max_uV = mV_to_uV(2900),
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
}
};
static struct regulator_init_data gpo1_init = {
.constraints = {
.name = "GPO1",
}
};
static struct regulator_init_data gpo2_init = {
.constraints = {
.name = "GPO2",
}
};
static struct regulator_init_data gpo3_init = {
.constraints = {
.name = "GPO3",
}
};
static struct regulator_init_data gpo4_init = {
.constraints = {
.name = "GPO4",
}
};
static struct regulator_init_data pwg1_init = {
.constraints = {
.name = "PWG1",
}
};
static struct regulator_init_data pwg2_init = {
.constraints = {
.name = "PWG2",
}
};
/*!
* the event handler for power on event
*/
static void power_on_evt_handler(void)
{
pr_info("pwr on event1 is received \n");
}
/*!
* pmic board initialization code
*/
static int init_mc13892(void)
{
unsigned int value;
pmic_event_callback_t power_key_event;
if (!board_is_rev(BOARD_REV_2))
return -1;
/* subscribe PWRON1 event. */
power_key_event.param = NULL;
power_key_event.func = (void *)power_on_evt_handler;
pmic_event_subscribe(EVENT_PWRONI, power_key_event);
pmic_read_reg(REG_POWER_CTL2, &value, 0xffffff);
/* Bit 11 (STANDBYSECINV): Active Low */
value |= 0x00800;
/* Bit 12 (WDIRESET): enable */
value |= 0x01000;
pmic_write_reg(REG_POWER_CTL2, value, 0xffffff);
/* Battery charger default settings */
/* current limit = 1200mA, PLIM = 1000mw, disable auto charge */
value = 0x210068;
pmic_write_reg(REG_CHARGE, value, 0x018078);
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
mc13892_register_regulator(mc13892, MC13892_PWGT1, &pwg1_init);
mc13892_register_regulator(mc13892, MC13892_PWGT2, &pwg2_init);
init_mc13892();
return 0;
}
static struct mc13892_platform_data mc13892_plat = {
.init = mc13892_regulator_init,
};
static struct i2c_board_info __initdata mc13892_i2c_device = {
I2C_BOARD_INFO("mc13892", 0x08),
.irq = IOMUX_TO_IRQ(MX35_PIN_GPIO2_0),
.platform_data = &mc13892_plat,
};
int __init mx35_3stack_init_mc13892(void)
{
return i2c_register_board_info(0, &mc13892_i2c_device, 1);
}

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arch/arm/mach-mx35/mx35_3stack_pmic_mc9s08dz60.c Normal file
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/*
* mx35-3stack-pmic-mc9s08dz60.c -- i.MX35 3STACK Driver for MCU PMIC
*/
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/pmic_external.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc9s08dz60/core.h>
#include "iomux.h"
#include "board-mx35_3stack.h"
static struct regulator_init_data lcd_init = {
.constraints = {
.name = "LCD",
}
};
static struct regulator_init_data wifi_init = {
.constraints = {
.name = "WIFI",
}
};
static struct regulator_init_data hdd_init = {
.constraints = {
.name = "HDD",
}
};
static struct regulator_init_data gps_init = {
.constraints = {
.name = "GPS",
}
};
static struct regulator_init_data spkr_init = {
.constraints = {
.name = "SPKR",
}
};
static int mc9s08dz60_regulator_init(struct mc9s08dz60 *mc9s08dz60)
{
if (!board_is_rev(BOARD_REV_2))
return 0;
mc9s08dz60_register_regulator(
mc9s08dz60, MC9S08DZ60_LCD, &lcd_init);
mc9s08dz60_register_regulator(mc9s08dz60,
MC9S08DZ60_WIFI, &wifi_init);
mc9s08dz60_register_regulator(
mc9s08dz60, MC9S08DZ60_HDD, &hdd_init);
mc9s08dz60_register_regulator(
mc9s08dz60, MC9S08DZ60_GPS, &gps_init);
mc9s08dz60_register_regulator(mc9s08dz60,
MC9S08DZ60_SPKR, &spkr_init);
return 0;
}
static struct mc9s08dz60_platform_data mc9s08dz60_plat = {
.init = mc9s08dz60_regulator_init,
};
static struct i2c_board_info __initdata mc9s08dz60_i2c_device = {
I2C_BOARD_INFO("mc9s08dz60", 0x69),
.platform_data = &mc9s08dz60_plat,
};
static struct resource mc9s08dz60_keypad_resource = {
.start = MXC_PSEUDO_IRQ_KEYPAD,
.end = MXC_PSEUDO_IRQ_KEYPAD,
.flags = IORESOURCE_IRQ,
};
static struct platform_device mc9s08dz60_keypad_dev = {
.name = "mc9s08dz60keypad",
.num_resources = 1,
.resource = &mc9s08dz60_keypad_resource,
};
int __init mx35_3stack_init_mc9s08dz60(void)
{
int retval = 0;
retval = i2c_register_board_info(0, &mc9s08dz60_i2c_device, 1);
if (retval == 0)
platform_device_register(&mc9s08dz60_keypad_dev);
return retval;
}

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
#define __ASM_ARCH_MXC_MX35_PINS_H__
/*!
* @file arch-mxc/mx35_pins.h
*
* @brief MX35 I/O Pin List
*
* @ingroup GPIO_MX35
*/
#ifndef __ASSEMBLY__
/*!
* @name IOMUX/PAD Bit field definitions
*/
/*! @{ */
/*!
* In order to identify pins more effectively, each mux-controlled pin's
* enumerated value is constructed in the following way:
*
* -------------------------------------------------------------------
* 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
* -------------------------------------------------------------------
* IO_P | IO_I | RSVD | PAD_I | MUX_I
* -------------------------------------------------------------------
*
* Bit 0 to 7 contains MUX_I used to identify the register
* offset (base is IOMUX_module_base ) defined in the Section
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
* definitions are used for the pad control register.the MX35_PIN_A0 is
* defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
* So the absolute address is: IOMUX_module_base + 0x28.
* The pad control register offset is: 0x368.
*/
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* MUX control register offset
*/
#define MUX_I 0
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* PAD control register offset
*/
#define PAD_I 10
/*!
* Starting bit position within each entry of \b iomux_pins to represent the
* reserved filed
*/
#define RSVD_I 21
#define NON_GPIO_I 0x7
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
#define NON_MUX_I PIN_TO_MUX_MASK
#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
((mi) << MUX_I) | ((pi) << PAD_I))
#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
_MXC_BUILD_PIN(gp, gi, mi, pi)
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
/*! @} End IOMUX/PAD Bit field definitions */
/*!
* This enumeration is constructed based on the Section
* "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
* value is constructed based on the rules described above.
*/
enum iomux_pins {
MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x1C, 0x340),
MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(1, 18, 0xC8, 0x4CC),
MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(1, 19, 0xCC, 0x4D0),
MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(1, 20, 0xD0, 0x4D4),
MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(1, 21, 0xD4, 0x4D8),
MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(1, 22, 0xD8, 0x4DC),
MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(1, 23, 0xDC, 0x4E0),
MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(2, 11, 0x19C, 0x5E0),
MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(2, 12, 0x1A0, 0x5E4),
MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(2, 13, 0x1A4, 0x5E8),
MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
};
#endif
#endif

80
arch/arm/mach-mx35/pm.c Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <mach/hardware.h>
/*!
* @defgroup MSL_MX35 i.MX35 Machine Specific Layer (MSL)
*/
/*!
* @file mach-mx35/pm.c
* @brief This file contains suspend operations
*
* @ingroup MSL_MX35
*/
static int mx35_suspend_enter(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_MEM:
mxc_cpu_lp_set(STOP_POWER_OFF);
break;
case PM_SUSPEND_STANDBY:
mxc_cpu_lp_set(STOP_POWER_ON);
break;
default:
return -EINVAL;
}
/* Executing CP15 (Wait-for-Interrupt) Instruction */
cpu_do_idle();
return 0;
}
/*
* Called after processes are frozen, but before we shut down devices.
*/
static int mx35_suspend_prepare(void)
{
return 0;
}
/*
* Called after devices are re-setup, but before processes are thawed.
*/
static void mx35_suspend_finish(void)
{
}
static int mx35_pm_valid(suspend_state_t state)
{
return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
}
struct platform_suspend_ops mx35_suspend_ops = {
.valid = mx35_pm_valid,
.prepare = mx35_suspend_prepare,
.enter = mx35_suspend_enter,
.finish = mx35_suspend_finish,
};
static int __init mx35_pm_init(void)
{
pr_info("Static Power Management for Freescale i.MX35\n");
suspend_set_ops(&mx35_suspend_ops);
return 0;
}
late_initcall(mx35_pm_init);

254
arch/arm/mach-mx35/sdma_script_code.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
/*!
* @file sdma_script_code.h
* @brief This file contains functions of SDMA scripts code initialization
*
* The file was generated automatically. Based on sdma scripts library.
*
* @ingroup SDMA
*/
/*******************************************************************************
SDMA RELEASE LABEL: "SS15_RINGO"
*******************************************************************************/
#ifndef __SDMA_SCRIPT_CODE_H__
#define __SDMA_SCRIPT_CODE_H__
/*!
* SDMA ROM scripts start addresses and sizes
*/
#define start_ADDR 0
#define start_SIZE 22
#define core_ADDR 80
#define core_SIZE 232
#define common_ADDR 312
#define common_SIZE 330
#define ap_2_ap_ADDR 642
#define ap_2_ap_SIZE 41
#define app_2_mcu_ADDR 683
#define app_2_mcu_SIZE 64
#define mcu_2_app_ADDR 747
#define mcu_2_app_SIZE 70
#define uart_2_mcu_ADDR 817
#define uart_2_mcu_SIZE 75
#define shp_2_mcu_ADDR 892
#define shp_2_mcu_SIZE 69
#define mcu_2_shp_ADDR 961
#define mcu_2_shp_SIZE 72
#define per_2_shp_ADDR 1033
#define per_2_shp_SIZE 78
#define shp_2_per_ADDR 1111
#define shp_2_per_SIZE 72
#define uartsh_2_mcu_ADDR 1183
#define uartsh_2_mcu_SIZE 69
#define mcu_2_ata_ADDR 1252
#define mcu_2_ata_SIZE 81
#define ata_2_mcu_ADDR 1333
#define ata_2_mcu_SIZE 96
#define loop_DMAs_routines_ADDR 1429
#define loop_DMAs_routines_SIZE 227
#define test_ADDR 1656
#define test_SIZE 63
#define signature_ADDR 1023
#define signature_SIZE 1
/*!
* SDMA RAM scripts start addresses and sizes
*/
#define app_2_per_ADDR 6144
#define app_2_per_SIZE 66
#define asrc__mcu_ADDR 6210
#define asrc__mcu_SIZE 114
#define ext_mem__ipu_ram_ADDR 6324
#define ext_mem__ipu_ram_SIZE 123
#define mcu_2_spdif_ADDR 6447
#define mcu_2_spdif_SIZE 103
#define p_2_p_ADDR 6550
#define p_2_p_SIZE 254
#define per_2_app_ADDR 6804
#define per_2_app_SIZE 74
#define spdif_2_mcu_ADDR 6878
#define spdif_2_mcu_SIZE 47
#define uart_2_per_ADDR 6925
#define uart_2_per_SIZE 73
#define uartsh_2_per_ADDR 6998
#define uartsh_2_per_SIZE 67
/*!
* SDMA RAM image start address and size
*/
#define RAM_CODE_START_ADDR 6144
#define RAM_CODE_SIZE 921
/*!
* Buffer that holds the SDMA RAM image
*/
__attribute__ ((__aligned__(4)))
#ifndef CONFIG_XIP_KERNEL
const
#endif
static const short sdma_code[] = {
0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6ad7, 0x008f, 0x00d5,
0x7d01, 0x008d, 0x05a0, 0x0478, 0x7d03, 0x0479, 0x7d1c, 0x7c21,
0x0479, 0x7c14, 0x6ddd, 0x56ee, 0x62c8, 0x7e28, 0x0660, 0x7d02,
0x0210, 0x0212, 0x6ac8, 0x7f22, 0x0212, 0x6ac8, 0x7f1f, 0x0212,
0x6ac8, 0x7f1c, 0x2003, 0x4800, 0x7cef, 0x9836, 0x6ddd, 0x7802,
0x62c8, 0x6ac8, 0x9835, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8,
0x9835, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c08, 0x6ddf, 0x7f06,
0x0000, 0x4d00, 0x7d05, 0xc1fa, 0x57db, 0x9806, 0xc273, 0x0454,
0xc20a, 0x9801, 0xc1d9, 0xc1e3, 0x56f3, 0x57db, 0x047a, 0x7d07,
0x072f, 0x076e, 0x7d02, 0x6ec7, 0x9855, 0x6ed7, 0x9855, 0x074f,
0x076e, 0x7d02, 0x6e01, 0x9855, 0x6e05, 0x5ce3, 0x048f, 0x0410,
0x3c0f, 0x5c93, 0x0eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6,
0x5deb, 0x55fb, 0x008e, 0x0768, 0x7d02, 0x0769, 0x7c04, 0x06d4,
0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05,
0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9887, 0x7802, 0x5205, 0x6ac8,
0x7c26, 0x9887, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21,
0x9887, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x0768,
0x7d02, 0x0769, 0x7c0a, 0x4c00, 0x7c08, 0x0768, 0x7d03, 0x5a05,
0x7f11, 0x9894, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000,
0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc1fa, 0x57db, 0x9856, 0x68cc,
0x98a2, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd8a8, 0xc20a, 0x9844,
0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0,
0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc13c,
0x7d2a, 0x5ade, 0x008e, 0xc14e, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8,
0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b,
0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd903, 0x98df, 0x6b05, 0xc5f5,
0x7e27, 0x7f29, 0x98df, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc61f,
0x7e18, 0x7f1a, 0x98df, 0x6b05, 0xc595, 0x7e07, 0x7f06, 0x52de,
0x53e6, 0xc159, 0x7dd7, 0x0200, 0x98b7, 0x0007, 0x6004, 0x680c,
0x53f6, 0x028e, 0x00a3, 0xc256, 0x048b, 0x0498, 0x0454, 0x068a,
0x98df, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98e8,
0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98e8, 0x0007,
0x68ff, 0x60d0, 0x98e8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00,
0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8,
0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f,
0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8,
0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a,
0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc1d9,
0xc1e3, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6,
0x993c, 0x6ac7, 0x993c, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d,
0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015,
0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9950, 0x620a, 0x7e38,
0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03,
0x62c8, 0x7e2c, 0x995d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217,
0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x997c, 0x0015, 0x0015,
0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01,
0x62c8, 0x5a26, 0x7c13, 0x997c, 0x7806, 0x0b00, 0x620b, 0x5a06,
0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000,
0x55eb, 0x4d00, 0x7d11, 0xc1fa, 0x57db, 0x993c, 0x68cc, 0x9989,
0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9990, 0x0017, 0x00a3,
0x0b70, 0x0311, 0x5313, 0xc213, 0xc20a, 0x9931, 0x0b70, 0x0311,
0x5313, 0x076c, 0x7c01, 0xc1d9, 0x5efb, 0x068a, 0x076b, 0x7c01,
0xc1d9, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b,
0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x0689,
0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18,
0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x99c1,
0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228,
0x99ca, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x99b8,
0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x99a8, 0x08ff,
0x00bf, 0x077f, 0x7d15, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0,
0x5deb, 0x028f, 0x0212, 0x0212, 0x3aff, 0x05da, 0x7c02, 0x073e,
0x99f3, 0x02a4, 0x02dd, 0x7d02, 0x073e, 0x99f3, 0x075e, 0x99f3,
0x55eb, 0x0598, 0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c,
0x7d01, 0x9a30, 0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02,
0x0e01, 0x9a0a, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0,
0x5d93, 0x06a0, 0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08,
0x0769, 0x7d03, 0x5502, 0x7e17, 0x9a17, 0x5d04, 0x7f14, 0x0689,
0x5093, 0x4800, 0x7d01, 0x9a02, 0x9a7b, 0x0015, 0x7806, 0x5502,
0x5d04, 0x074f, 0x5502, 0x5d24, 0x072f, 0x7c01, 0x9a7b, 0x0017,
0x076f, 0x7c01, 0x2001, 0x5593, 0x009d, 0x0007, 0xda82, 0x99d0,
0x6cd3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a3f, 0x5893,
0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802,
0x5502, 0x6dc8, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502,
0x7e09, 0x9a4c, 0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01,
0x9a37, 0x9a7b, 0x9a75, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02,
0x0e01, 0x9a62, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0,
0x5d93, 0x06a0, 0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08,
0x0769, 0x7d03, 0x65c8, 0x7e09, 0x9a6f, 0x5d04, 0x7f06, 0x0689,
0x5093, 0x4800, 0x7d01, 0x9a5a, 0x9a7b, 0x5593, 0x009d, 0x0007,
0x6cff, 0xda82, 0x99d0, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01,
0x99d0, 0x99b8, 0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f,
0x7c02, 0x05a0, 0x9a8f, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210,
0x04ba, 0x04ad, 0x0454, 0x0006, 0xc1e3, 0x57db, 0x52f3, 0x6ac5,
0x52fb, 0x6ad3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb,
0x0478, 0x7d03, 0x0479, 0x7d20, 0x7c25, 0x0479, 0x7c19, 0x59e3,
0x56ee, 0x61c8, 0x7e2e, 0x62c8, 0x7e2c, 0x65c8, 0x7e2a, 0x0660,
0x7d03, 0x0112, 0x0112, 0x9ab6, 0x0512, 0x0512, 0x0211, 0x02a9,
0x02ad, 0x6ac8, 0x7f1e, 0x2003, 0x4800, 0x7ceb, 0x51e3, 0x9ad0,
0x7802, 0x62c8, 0x6ac8, 0x9acf, 0x6dce, 0x0015, 0x7802, 0x62c8,
0x6ac8, 0x9acf, 0x6dcf, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c09,
0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57db,
0x9a9a, 0x0007, 0x68ff, 0xc213, 0xc20a, 0x9a95, 0xc1d9, 0xc1e3,
0x57db, 0x52f3, 0x047a, 0x7d02, 0x6ad7, 0x9ae7, 0x6a05, 0x008f,
0x00d5, 0x7d01, 0x008d, 0x05a0, 0x56fb, 0x0015, 0x0015, 0x0015,
0x047a, 0x7d07, 0x7804, 0x5206, 0x6ac8, 0x5226, 0x6ac8, 0x7c0f,
0x9b01, 0x7804, 0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x7c0a, 0x6a28,
0x7f08, 0x0000, 0x4d00, 0x7d07, 0xc1fa, 0x57db, 0x9ae7, 0xc273,
0x9b0a, 0xc277, 0x0454, 0xc20a, 0x9ae0, 0xc1e3, 0x57db, 0x52f3,
0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e,
0x1e94, 0x6ee3, 0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8,
0x2694, 0x52eb, 0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8,
0x7f23, 0x2501, 0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8,
0x6ec3, 0x0260, 0x7df1, 0x62d0, 0xc27a, 0x9b52, 0x6ee3, 0x008f,
0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e,
0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00,
0x7d09, 0xc1fa, 0x57db, 0x9b11, 0x0007, 0x6aff, 0x62d0, 0xc27a,
0x0458, 0x0454, 0x6add, 0x7ff8, 0xc20a, 0x9b0e, 0xc1d9, 0xc1e3,
0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269,
0x7d17, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e,
0x7d26, 0x6ac8, 0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98,
0x5202, 0x0260, 0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc27a, 0x9b95,
0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e,
0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000,
0x4d00, 0x7d0b, 0xc1fa, 0x57db, 0x9b5b, 0x0007, 0x6aff, 0x6add,
0x7ffc, 0x62d0, 0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc20a,
0x9b58
};
#endif

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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
/*!
* @file sdma_script_code.h
* @brief This file contains functions of SDMA scripts code initialization
*
* The file was generated automatically. Based on sdma scripts library.
*
* @ingroup SDMA
*/
/*******************************************************************************
SDMA RELEASE LABEL: "SDMA_RINGO.03.00.00"
*******************************************************************************/
#ifndef SDMA_SCRIPT_CODE_V2_H
#define SDMA_SCRIPT_CODE_V2_H
/*!
* SDMA ROM scripts start addresses and sizes
*/
#define start_ADDR_V2 0
#define start_SIZE_V2 24
#define core_ADDR_V2 80
#define core_SIZE_V2 233
#define common_ADDR_V2 313
#define common_SIZE_V2 416
#define ap_2_ap_ADDR_V2 729
#define ap_2_ap_SIZE_V2 41
#define app_2_mcu_ADDR_V2 770
#define app_2_mcu_SIZE_V2 64
#define mcu_2_app_ADDR_V2 834
#define mcu_2_app_SIZE_V2 70
#define uart_2_mcu_ADDR_V2 904
#define uart_2_mcu_SIZE_V2 75
#define shp_2_mcu_ADDR_V2 979
#define shp_2_mcu_SIZE_V2 69
#define mcu_2_shp_ADDR_V2 1048
#define mcu_2_shp_SIZE_V2 72
#define per_2_shp_ADDR_V2 1120
#define per_2_shp_SIZE_V2 78
#define shp_2_per_ADDR_V2 1198
#define shp_2_per_SIZE_V2 72
#define uartsh_2_mcu_ADDR_V2 1270
#define uartsh_2_mcu_SIZE_V2 69
#define mcu_2_ata_ADDR_V2 1339
#define mcu_2_ata_SIZE_V2 90
#define ata_2_mcu_ADDR_V2 1429
#define ata_2_mcu_SIZE_V2 102
#define app_2_per_ADDR_V2 1531
#define app_2_per_SIZE_V2 66
#define per_2_app_ADDR_V2 1597
#define per_2_app_SIZE_V2 74
#define loop_DMAs_routines_ADDR_V2 1671
#define loop_DMAs_routines_SIZE_V2 240
#define test_ADDR_V2 1911
#define test_SIZE_V2 63
#define signature_ADDR_V2 1022
#define signature_SIZE_V2 1
/*!
* SDMA RAM scripts start addresses and sizes
*/
#define asrc__mcu_ADDR_V2 6144
#define asrc__mcu_SIZE_V2 116
#define ext_mem__ipu_ram_ADDR_V2 6260
#define ext_mem__ipu_ram_SIZE_V2 123
#define mcu_2_spdif_ADDR_V2 6383
#define mcu_2_spdif_SIZE_V2 103
#define p_2_p_ADDR_V2 6486
#define p_2_p_SIZE_V2 260
#define spdif_2_mcu_ADDR_V2 6746
#define spdif_2_mcu_SIZE_V2 47
#define uart_2_per_ADDR_V2 6793
#define uart_2_per_SIZE_V2 73
#define uartsh_2_per_ADDR_V2 6866
#define uartsh_2_per_SIZE_V2 67
/*!
* SDMA RAM image start address and size
*/
#define RAM_CODE_START_ADDR_V2 6144
#define RAM_CODE_SIZE_V2 789
/*!
* Buffer that holds the SDMA RAM image
*/
static const short sdma_code_v2[] = {
0xc230, 0xc23a, 0x56f3, 0x57db, 0x047a, 0x7d07, 0x072f, 0x076e,
0x7d02, 0x6ec7, 0x9813, 0x6ed7, 0x9813, 0x074f, 0x076e, 0x7d02,
0x6e01, 0x9813, 0x6e05, 0x5ce3, 0x048f, 0x0410, 0x3c0f, 0x5c93,
0x0e03, 0x0611, 0x1eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6,
0x5deb, 0x55fb, 0x008e, 0x076a, 0x7d02, 0x076b, 0x7c04, 0x06d4,
0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05,
0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9847, 0x7802, 0x5205, 0x6ac8,
0x7c26, 0x9847, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21,
0x9847, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x076a,
0x7d02, 0x076b, 0x7c0a, 0x4c00, 0x7c08, 0x076a, 0x7d03, 0x5a05,
0x7f11, 0x9854, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000,
0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc251, 0x57db, 0x9814, 0x68cc,
0x9862, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd868, 0xc261, 0x9802,
0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0,
0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc18a,
0x7d2a, 0x5ade, 0x008e, 0xc19c, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8,
0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b,
0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd8c3, 0x989f, 0x6b05, 0xc6e7,
0x7e27, 0x7f29, 0x989f, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc711,
0x7e18, 0x7f1a, 0x989f, 0x6b05, 0xc687, 0x7e07, 0x7f06, 0x52de,
0x53e6, 0xc1a8, 0x7dd7, 0x0200, 0x9877, 0x0007, 0x6004, 0x680c,
0x53f6, 0x028e, 0x00a3, 0xc2ad, 0x048b, 0x0498, 0x0454, 0x068a,
0x989f, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98a8,
0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98a8, 0x0007,
0x68ff, 0x60d0, 0x98a8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00,
0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8,
0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f,
0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8,
0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a,
0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc230,
0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6,
0x98fc, 0x6ac7, 0x98fc, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d,
0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015,
0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9910, 0x620a, 0x7e38,
0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03,
0x62c8, 0x7e2c, 0x991d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217,
0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x993c, 0x0015, 0x0015,
0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01,
0x62c8, 0x5a26, 0x7c13, 0x993c, 0x7806, 0x0b00, 0x620b, 0x5a06,
0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000,
0x55eb, 0x4d00, 0x7d11, 0xc251, 0x57db, 0x98fc, 0x68cc, 0x9949,
0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9950, 0x0017, 0x00a3,
0x0b70, 0x0311, 0x5313, 0xc26a, 0xc261, 0x98f1, 0x0b70, 0x0311,
0x5313, 0x076c, 0x7c01, 0xc230, 0x5efb, 0x068a, 0x076b, 0x7c01,
0xc230, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b,
0xc18a, 0x7d2b, 0x5ac0, 0x5bc8, 0xc19c, 0x7c27, 0x0388, 0x0689,
0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18,
0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x9981,
0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228,
0x998a, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x9978,
0x008b, 0x52c0, 0x53c8, 0xc1a8, 0x7dd6, 0x0200, 0x9968, 0x08ff,
0x00bf, 0x077f, 0x7d1b, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0,
0x5deb, 0x028f, 0x32ff, 0x0210, 0x32ff, 0x0210, 0x0212, 0x0217,
0x0217, 0x32ff, 0x0212, 0x05da, 0x7c02, 0x073e, 0x99b9, 0x02a4,
0x02dd, 0x7d02, 0x073e, 0x99b9, 0x075e, 0x99b9, 0x55eb, 0x0598,
0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, 0x7d01, 0x99f6,
0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x99d0,
0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0,
0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, 0x0769, 0x7d03,
0x5502, 0x7e17, 0x99dd, 0x5d04, 0x7f14, 0x0689, 0x5093, 0x4800,
0x7d01, 0x99c8, 0x9a41, 0x0015, 0x7806, 0x5502, 0x5d04, 0x074d,
0x5502, 0x5d24, 0x072d, 0x7c01, 0x9a41, 0x0017, 0x076d, 0x7c01,
0x2001, 0x5593, 0x009d, 0x0007, 0xda48, 0x9990, 0x6cd3, 0x0769,
0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a05, 0x5893, 0x00d6, 0x7d01,
0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x6dc8,
0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e09, 0x9a12,
0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x99fd, 0x9a41,
0x9a3b, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a28,
0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0,
0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03,
0x65c8, 0x7e09, 0x9a35, 0x5d04, 0x7f06, 0x0689, 0x5093, 0x4800,
0x7d01, 0x9a20, 0x9a41, 0x5593, 0x009d, 0x0007, 0x6cff, 0xda48,
0x9990, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, 0x9990, 0x9978,
0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, 0x7c02, 0x05a0,
0x9a55, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, 0x04ba, 0x04ad,
0x0454, 0x0006, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d02,
0x6ad7, 0x9a63, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0,
0x56fb, 0x0015, 0x0015, 0x0015, 0x047a, 0x7d07, 0x7804, 0x5206,
0x6ac8, 0x5226, 0x6ac8, 0x7c0f, 0x9a7d, 0x7804, 0x5206, 0x6a0b,
0x5226, 0x6a0b, 0x7c0a, 0x6a28, 0x7f08, 0x0000, 0x4d00, 0x7d07,
0xc251, 0x57db, 0x9a63, 0xc2ca, 0x9a86, 0xc2ce, 0x0454, 0xc261,
0x9a5c, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94,
0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3, 0x62d0, 0x5aeb,
0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb, 0x6ad5, 0x6ee3,
0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501, 0x4d00, 0x7d26,
0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x62d0,
0xc2d1, 0x9ace, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d,
0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9,
0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc251, 0x57db, 0x9a8d,
0x0007, 0x6aff, 0x62d0, 0xc2d1, 0x0458, 0x0454, 0x6add, 0x7ff8,
0xc261, 0x9a8a, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb,
0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94, 0x5206, 0x0248,
0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8, 0x7f22, 0x2501,
0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6add,
0x7f18, 0x62d0, 0xc2d1, 0x9b11, 0x008f, 0x2001, 0x00d5, 0x7d01,
0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001,
0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b, 0xc251, 0x57db,
0x9ad7, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0, 0xc2d1, 0x0458,
0x0454, 0x6add, 0x7ff6, 0xc261, 0x9ad4
};
#endif

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx35/serial.c
*
* @brief This file contains the UART initiliazation.
*
* @ingroup MSL_MX35
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <mach/hardware.h>
#include <mach/mxc_uart.h>
#include <mach/spba.h>
#include "serial.h"
#include "board-mx35_3stack.h"
#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
/*!
* This is an array where each element holds information about a UART port,
* like base address of the UART, interrupt numbers etc. This structure is
* passed to the serial_core.c file. Based on which UART is used, the core file
* passes back the appropriate port structure as an argument to the control
* functions.
*/
static uart_mxc_port mxc_ports[] = {
[0] = {
.port = {
.membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
.mapbase = UART1_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART1_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.ints_muxed = UART1_MUX_INTS,
.irqs = {UART1_INT2, UART1_INT3},
.mode = UART1_MODE,
.ir_mode = UART1_IR,
.enabled = UART1_ENABLED,
.hardware_flow = UART1_HW_FLOW,
.cts_threshold = UART1_UCR4_CTSTL,
.dma_enabled = UART1_DMA_ENABLE,
.dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
.rx_threshold = UART1_UFCR_RXTL,
.tx_threshold = UART1_UFCR_TXTL,
.shared = UART1_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART1_TX,
.dma_rx_id = MXC_DMA_UART1_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
[1] = {
.port = {
.membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
.mapbase = UART2_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART2_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 1,
},
.ints_muxed = UART2_MUX_INTS,
.irqs = {UART2_INT2, UART2_INT3},
.mode = UART2_MODE,
.ir_mode = UART2_IR,
.enabled = UART2_ENABLED,
.hardware_flow = UART2_HW_FLOW,
.cts_threshold = UART2_UCR4_CTSTL,
.dma_enabled = UART2_DMA_ENABLE,
.dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
.rx_threshold = UART2_UFCR_RXTL,
.tx_threshold = UART2_UFCR_TXTL,
.shared = UART2_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART2_TX,
.dma_rx_id = MXC_DMA_UART2_RX,
.rxd_mux = MXC_UART_IR_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#if UART3_ENABLED == 1
[2] = {
.port = {
.membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
.mapbase = UART3_BASE_ADDR,
.iotype = SERIAL_IO_MEM,
.irq = UART3_INT1,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 2,
},
.ints_muxed = UART3_MUX_INTS,
.irqs = {UART3_INT2, UART3_INT3},
.mode = UART3_MODE,
.ir_mode = UART3_IR,
.enabled = UART3_ENABLED,
.hardware_flow = UART3_HW_FLOW,
.cts_threshold = UART3_UCR4_CTSTL,
.dma_enabled = UART3_DMA_ENABLE,
.dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
.rx_threshold = UART3_UFCR_RXTL,
.tx_threshold = UART3_UFCR_TXTL,
.shared = UART3_SHARED_PERI,
.dma_tx_id = MXC_DMA_UART3_TX,
.dma_rx_id = MXC_DMA_UART3_RX,
.rxd_mux = MXC_UART_RXDMUX,
.ir_tx_inv = MXC_IRDA_TX_INV,
.ir_rx_inv = MXC_IRDA_RX_INV,
},
#endif
};
static struct platform_device mxc_uart_device1 = {
.name = "mxcintuart",
.id = 0,
.dev = {
.platform_data = &mxc_ports[0],
},
};
static struct platform_device mxc_uart_device2 = {
.name = "mxcintuart",
.id = 1,
.dev = {
.platform_data = &mxc_ports[1],
},
};
#if UART3_ENABLED == 1
static struct platform_device mxc_uart_device3 = {
.name = "mxcintuart",
.id = 2,
.dev = {
.platform_data = &mxc_ports[2],
},
};
#endif
static int __init mxc_init_uart(void)
{
/* Register all the MXC UART platform device structures */
platform_device_register(&mxc_uart_device1);
platform_device_register(&mxc_uart_device2);
/* Grab ownership of shared UARTs 3 and 4, only when enabled */
#if UART3_ENABLED == 1
#if UART3_DMA_ENABLE == 1
spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C));
#else
spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A);
#endif /* UART3_DMA_ENABLE */
platform_device_register(&mxc_uart_device3);
#endif /* UART3_ENABLED */
return 0;
}
#else
static int __init mxc_init_uart(void)
{
return 0;
}
#endif
arch_initcall(mxc_init_uart);

132
arch/arm/mach-mx35/serial.h Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX35_SERIAL_H__
#define __ARCH_ARM_MACH_MX35_SERIAL_H__
/*!
* @file mach-mx35/serial.h
*
* @ingroup MSL_MX35
*/
#include <mach/mxc_uart.h>
/* UART 1 configuration */
/*!
* This option allows to choose either an interrupt-driven software controlled
* hardware flow control (set this option to 0) or hardware-driven hardware
* flow control (set this option to 1).
*/
#define UART1_HW_FLOW 1
/*!
* This specifies the threshold at which the CTS pin is deasserted by the
* RXFIFO. Set this value in Decimal to anything from 0 to 32 for
* hardware-driven hardware flow control. Read the HW spec while specifying
* this value. When using interrupt-driven software controlled hardware
* flow control set this option to -1.
*/
#define UART1_UCR4_CTSTL 16
/*!
* This is option to enable (set this option to 1) or disable DMA data transfer
*/
#define UART1_DMA_ENABLE 0
/*!
* Specify the size of the DMA receive buffer. The minimum buffer size is 512
* bytes. The buffer size should be a multiple of 256.
*/
#define UART1_DMA_RXBUFSIZE 1024
/*!
* Specify the MXC UART's Receive Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the RxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_RXTL 16
/*!
* Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
* which a maskable interrupt is generated by the TxFIFO. Set this value in
* Decimal to anything from 0 to 32. Read the HW spec while specifying this
* value.
*/
#define UART1_UFCR_TXTL 16
/* UART 2 configuration */
#define UART2_HW_FLOW 1
#define UART2_UCR4_CTSTL 16
#define UART2_DMA_ENABLE 0
#define UART2_DMA_RXBUFSIZE 1024
#define UART2_UFCR_RXTL 16
#define UART2_UFCR_TXTL 16
/* UART 3 configuration */
#define UART3_HW_FLOW 1
#define UART3_UCR4_CTSTL 16
#define UART3_DMA_ENABLE 1
#define UART3_DMA_RXBUFSIZE 1024
#define UART3_UFCR_RXTL 16
#define UART3_UFCR_TXTL 16
/*
* UART Chip level Configuration that a user may not have to edit. These
* configuration vary depending on how the UART module is integrated with
* the ARM core
*/
/*
* Is the MUXED interrupt output sent to the ARM core
*/
#define INTS_NOTMUXED 0
#define INTS_MUXED 1
/* UART 1 configuration */
/*!
* This define specifies whether the muxed ANDed interrupt line or the
* individual interrupts from the UART port is integrated with the ARM core.
* There exists a define like this for each UART port. Valid values that can
* be used are \b INTS_NOTMUXED or \b INTS_MUXED.
*/
#define UART1_MUX_INTS INTS_MUXED
/*!
* This define specifies the transmitter interrupt number or the interrupt
* number of the ANDed interrupt in case the interrupts are muxed. There exists
* a define like this for each UART port.
*/
#define UART1_INT1 MXC_INT_UART1
/*!
* This define specifies the receiver interrupt number. If the interrupts of
* the UART are muxed, then we specify here a dummy value -1. There exists a
* define like this for each UART port.
*/
#define UART1_INT2 -1
/*!
* This specifies the master interrupt number. If the interrupts of the UART
* are muxed, then we specify here a dummy value of -1. There exists a define
* like this for each UART port.
*/
#define UART1_INT3 -1
/*!
* This specifies if the UART is a shared peripheral. It holds the shared
* peripheral number if it is shared or -1 if it is not shared. There exists
* a define like this for each UART port.
*/
#define UART1_SHARED_PERI -1
/* UART 2 configuration */
#define UART2_MUX_INTS INTS_MUXED
#define UART2_INT1 MXC_INT_UART2
#define UART2_INT2 -1
#define UART2_INT3 -1
#define UART2_SHARED_PERI -1
/* UART 3 configuration */
#define UART3_MUX_INTS INTS_MUXED
#define UART3_INT1 MXC_INT_UART3
#define UART3_INT2 -1
#define UART3_INT3 -1
#define UART3_SHARED_PERI SPBA_UART3
#endif /* __ARCH_ARM_MACH_MX35_SERIAL_H__ */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/proc-fns.h>
#include <asm/system.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include "crm_regs.h"
/*!
* @defgroup MSL_MX35 i.MX35 Machine Specific Layer (MSL)
*/
/*!
* @file mach-mx35/system.c
* @brief This file contains idle and reset functions.
*
* @ingroup MSL_MX35
*/
/*!
* MX35 low-power mode
*/
enum mx35_low_pwr_mode {
MX35_RUN_MODE,
MX35_WAIT_MODE,
MX35_DOZE_MODE,
MX35_STOP_MODE
};
extern int mxc_jtag_enabled;
/*!
* This function is used to set cpu low power mode before WFI instruction
*
* @param mode indicates different kinds of power modes
*/
void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
unsigned int lpm;
unsigned long reg;
/*read CCMR value */
reg = __raw_readl(MXC_CCM_CCMR);
switch (mode) {
case WAIT_UNCLOCKED_POWER_OFF:
lpm = MX35_DOZE_MODE;
break;
case STOP_POWER_ON:
case STOP_POWER_OFF:
lpm = MX35_STOP_MODE;
/* Enabled Well Bias */
reg |= MXC_CCM_CCMR_WBEN;
if (!board_is_rev(BOARD_REV_1))
reg |= MXC_CCM_CCMR_VSTBY;
break;
case WAIT_CLOCKED:
case WAIT_UNCLOCKED:
default:
/* Wait is the default mode used when idle. */
lpm = MX35_WAIT_MODE;
break;
}
/* program LPM bit */
reg = (reg & (~MXC_CCM_CCMR_LPM_MASK)) | lpm << MXC_CCM_CCMR_LPM_OFFSET;
/* program Interrupt holdoff bit */
reg = reg | MXC_CCM_CCMR_WFI;
/* TBD: PMIC has put the voltage back to Normal if the voltage ready */
/* counter finished */
reg = reg | MXC_CCM_CCMR_STBY_EXIT_SRC;
__raw_writel(reg, MXC_CCM_CCMR);
}
EXPORT_SYMBOL(mxc_cpu_lp_set);
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks.
*/
if (!mxc_jtag_enabled) {
#ifdef CONFIG_MX35_DOZE_DURING_IDLE
/*set as Doze mode */
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
#else
/* set as Wait mode */
mxc_cpu_lp_set(WAIT_UNCLOCKED);
#endif
cpu_do_idle();
}
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
void arch_reset(char mode)
{
/* Assert SRS signal */
mxc_wd_reset();
}

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arch/arm/mach-mx35/usb.h Normal file
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/*
* Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
extern int usbotg_init(struct platform_device *pdev);
extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
extern struct platform_device *host_pdev_register(struct resource *res,
int n_res, struct fsl_usb2_platform_data *config);
extern int fsl_usb_host_init(struct platform_device *pdev);
extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
extern int gpio_usbh2_active(void);
extern void gpio_usbh2_inactive(void);
extern int gpio_usbotg_utmi_active(void);
extern void gpio_usbotg_utmi_inactive(void);
/*
* Determine which platform_data struct to use for the DR controller,
* based on which transceiver is configured.
* PDATA is a pointer to it.
*/
static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config;
#define PDATA (&dr_utmi_config)
/*
* Used to set pdata->operating_mode before registering the platform_device.
* If OTG is configured, the controller operates in OTG mode,
* otherwise it's either host or device.
*/
#ifdef CONFIG_USB_OTG
#define DR_UDC_MODE FSL_USB2_DR_OTG
#define DR_HOST_MODE FSL_USB2_DR_OTG
#else
#define DR_UDC_MODE FSL_USB2_DR_DEVICE
#define DR_HOST_MODE FSL_USB2_DR_HOST
#endif
#ifdef CONFIG_USB_EHCI_ARC_OTG
static inline void dr_register_host(struct resource *r, int rs)
{
PDATA->operating_mode = DR_HOST_MODE;
host_pdev_register(r, rs, PDATA);
}
#else
static inline void dr_register_host(struct resource *r, int rs)
{
}
#endif
#ifdef CONFIG_USB_GADGET_ARC
static struct platform_device dr_udc_device;
static inline void dr_register_udc(void)
{
PDATA->operating_mode = DR_UDC_MODE;
dr_udc_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_udc_device))
printk(KERN_ERR "usb: can't register DR gadget\n");
else
printk(KERN_INFO "usb: DR gadget (%s) registered\n",
PDATA->transceiver);
}
#else
static inline void dr_register_udc(void)
{
}
#endif
#ifdef CONFIG_USB_OTG
static struct platform_device dr_otg_device;
/*
* set the proper operating_mode and
* platform_data pointer, then register the
* device.
*/
static inline void dr_register_otg(void)
{
PDATA->operating_mode = FSL_USB2_DR_OTG;
dr_otg_device.dev.platform_data = PDATA;
if (platform_device_register(&dr_otg_device))
printk(KERN_ERR "usb: can't register otg device\n");
else
printk(KERN_INFO "usb: DR OTG registered\n");
}
#else
static inline void dr_register_otg(void)
{
}
#endif

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arch/arm/mach-mx35/usb_dr.c Normal file
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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
/*
* platform data structs
* - Which one to use is determined by CONFIG options in usb.h
* - operating_mode plugged at run time
*/
static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
.name = "DR",
.platform_init = usbotg_init,
.platform_uninit = usbotg_uninit,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
.power_budget = 500, /* 500 mA max power */
.gpio_usb_active = gpio_usbotg_utmi_active,
.gpio_usb_inactive = gpio_usbotg_utmi_inactive,
.transceiver = "utmi",
};
/*
* resources
*/
static struct resource otg_resources[] = {
[0] = {
.start = (u32)(USB_OTGREGS_BASE),
.end = (u32)(USB_OTGREGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USBOTG,
.flags = IORESOURCE_IRQ,
},
};
static u64 dr_udc_dmamask = ~(u32) 0;
static void dr_udc_release(struct device *dev)
{
}
static u64 dr_otg_dmamask = ~(u32) 0;
static void dr_otg_release(struct device *dev)
{
}
/*
* platform device structs
* dev.platform_data field plugged at run time
*/
static struct platform_device __maybe_unused dr_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.release = dr_udc_release,
.dma_mask = &dr_udc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static struct platform_device __maybe_unused dr_otg_device = {
.name = "fsl-usb2-otg",
.id = -1,
.dev = {
.release = dr_otg_release,
.dma_mask = &dr_otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
static int __init usb_dr_init(void)
{
pr_debug("%s: \n", __func__);
/* i.MX35 1.0 should work in INCR mode */
if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) {
PDATA->change_ahb_burst = 1;
PDATA->ahb_burst_mode = 0;
}
dr_register_otg();
dr_register_host(otg_resources, ARRAY_SIZE(otg_resources));
dr_register_udc();
return 0;
}
module_init(usb_dr_init);

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arch/arm/mach-mx35/usb_h2.c Normal file
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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/usb/fsl_xcvr.h>
#include <mach/hardware.h>
#include <mach/arc_otg.h>
#include "usb.h"
static struct fsl_usb2_platform_data usbh2_config = {
.name = "Host 2",
.platform_init = fsl_usb_host_init,
.platform_uninit = fsl_usb_host_uninit,
.operating_mode = FSL_USB2_MPH_HOST,
.phy_mode = FSL_USB2_PHY_SERIAL,
.power_budget = 500, /* 500 mA max power */
.gpio_usb_active = gpio_usbh2_active,
.gpio_usb_inactive = gpio_usbh2_inactive,
.transceiver = "serial",
};
static struct resource usbh2_resources[] = {
[0] = {
.start = (u32) (USB_H2REGS_BASE),
.end = (u32) (USB_H2REGS_BASE + 0x1ff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MXC_INT_USBHS,
.flags = IORESOURCE_IRQ,
},
};
static int __init usbh2_init(void)
{
pr_debug("%s: \n", __func__);
/* i.MX35 1.0 should work in INCR mode */
if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) {
usbh2_config.change_ahb_burst = 1;
usbh2_config.ahb_burst_mode = 0;
}
host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
&usbh2_config);
return 0;
}
module_init(usbh2_init);

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