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ENGR00117720-2 MX28: Add Debug Uart Driver Support
Add D-UART driver support for MX28 Signed-off-by: Fred Fan <r01011@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
This commit is contained in:
Robby Cai
Matt Sealey
@@ -359,6 +359,30 @@ config SERIAL_STMP_APP
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help
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Driver for Sigmatel 36XX/37XX internal application serial port
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config SERIAL_MXS_DUART
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tristate "i.MXS debug serial port support"
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depends on ARCH_MXS
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select SERIAL_CORE
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help
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Driver for Freescale i.MXS internal debug serial port
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config SERIAL_MXS_DUART_CONSOLE
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bool "Support for console on i.MXS debug serial port"
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depends on SERIAL_MXS_DUART=y
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select SERIAL_CORE_CONSOLE
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---help---
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Say Y here if you wish to use the i.MXS debug serial port as the
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system console (the system console is the device which receives all
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kernel messages and warnings and which allows logins in single user
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mode).
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Even if you say Y here, the currently visible framebuffer console
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(/dev/tty0) will still be used as the system console by default, but
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you can alter that using a kernel command line option such as
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"console=ttyAM0". (Try "man bootparam" or see the documentation of
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your boot loader (lilo or loadlin) about how to pass options to the
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kernel at boot time.)
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config SERIAL_AMBA_PL011
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tristate "ARM AMBA PL011 serial port support"
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depends on ARM_AMBA
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@@ -77,6 +77,7 @@ obj-$(CONFIG_SERIAL_MXC) += mxc_uart.o
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obj-$(CONFIG_SERIAL_MXC_CONSOLE) += mxc_uart_early.o
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obj-$(CONFIG_SERIAL_STMP_DBG) += stmp-dbg.o
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obj-$(CONFIG_SERIAL_STMP_APP) += stmp-app.o
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obj-$(CONFIG_SERIAL_MXS_DUART) += mxs-duart.o
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obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
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obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
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obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
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772
drivers/serial/mxs-duart.c
Normal file
772
drivers/serial/mxs-duart.c
Normal file
@@ -0,0 +1,772 @@
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/*
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#if defined(CONFIG_SERIAL_MXS_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <mach/device.h>
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#include "regs-duart.h"
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/* treated as variable unless submitted to open-source */
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#define PORT_DUART 100
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#define SERIAL_DUART_MAJOR 204
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#define SERIAL_DUART_MINOR 16
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#define SERIAL_RX_LIMIT 256
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#define ISR_PASS_LIMIT 256
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#define DUART_DEVID "DebugUART"
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static int force_cd = 1;
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static struct uart_driver duart_drv;
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct duart_port {
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struct uart_port port;
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struct clk *clk;
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unsigned int im; /* interrupt mask */
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unsigned int old_status;
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int suspended;
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};
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static void duart_stop_tx(struct uart_port *port)
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{
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struct duart_port *dp = container_of(port, struct duart_port, port);
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dp->im &= ~BM_UARTDBGIMSC_TXIM;
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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}
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static void duart_start_tx(struct uart_port *port)
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{
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struct duart_port *dp = container_of(port, struct duart_port, port);
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dp->im |= BM_UARTDBGIMSC_TXIM;
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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}
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static void duart_stop_rx(struct uart_port *port)
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{
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struct duart_port *dp = container_of(port, struct duart_port, port);
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dp->im &= ~(BM_UARTDBGIMSC_OEIM | BM_UARTDBGIMSC_BEIM |
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BM_UARTDBGIMSC_PEIM | BM_UARTDBGIMSC_FEIM |
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BM_UARTDBGIMSC_RTIM | BM_UARTDBGIMSC_RXIM);
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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}
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static void duart_enable_ms(struct uart_port *port)
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{
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struct duart_port *dp = container_of(port, struct duart_port, port);
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dp->im |= BM_UARTDBGIMSC_RIMIM | BM_UARTDBGIMSC_CTSMIM |
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BM_UARTDBGIMSC_DCDMIM | BM_UARTDBGIMSC_DSRMIM;
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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}
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static void duart_rx_chars(struct duart_port *dp)
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{
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struct tty_struct *tty = dp->port.info->port.tty;
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unsigned int status, ch, flag, rsr, max_count = SERIAL_RX_LIMIT;
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status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
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while ((status & BM_UARTDBGFR_RXFE) == 0 && max_count--) {
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ch = __raw_readl(dp->port.membase + HW_UARTDBGDR);
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flag = TTY_NORMAL;
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dp->port.icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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rsr = __raw_readl(dp->port.membase + HW_UARTDBGRSR_ECR);
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if (unlikely(rsr & (BM_UARTDBGRSR_ECR_OE |
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BM_UARTDBGRSR_ECR_BE |
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BM_UARTDBGRSR_ECR_PE |
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BM_UARTDBGRSR_ECR_FE))) {
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if (rsr & BM_UARTDBGRSR_ECR_BE) {
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rsr &= ~(BM_UARTDBGRSR_ECR_FE |
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BM_UARTDBGRSR_ECR_PE);
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dp->port.icount.brk++;
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if (uart_handle_break(&dp->port))
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goto ignore_char;
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} else if (rsr & BM_UARTDBGRSR_ECR_PE)
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dp->port.icount.parity++;
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else if (rsr & BM_UARTDBGRSR_ECR_FE)
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dp->port.icount.frame++;
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if (rsr & BM_UARTDBGRSR_ECR_OE)
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dp->port.icount.overrun++;
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rsr &= dp->port.read_status_mask;
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if (rsr & BM_UARTDBGRSR_ECR_BE)
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flag = TTY_BREAK;
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else if (rsr & BM_UARTDBGRSR_ECR_PE)
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flag = TTY_PARITY;
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else if (rsr & BM_UARTDBGRSR_ECR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(&dp->port, ch))
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goto ignore_char;
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uart_insert_char(&dp->port, rsr, BM_UARTDBGRSR_ECR_OE, ch,
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flag);
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ignore_char:
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status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
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}
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tty_flip_buffer_push(tty);
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return;
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}
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static void duart_tx_chars(struct duart_port *dp)
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{
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int count;
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struct circ_buf *xmit = &dp->port.info->xmit;
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if (dp->port.x_char) {
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__raw_writel(dp->port.x_char, dp->port.membase + HW_UARTDBGDR);
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dp->port.icount.tx++;
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dp->port.x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(&dp->port)) {
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duart_stop_tx(&dp->port);
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return;
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}
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count = dp->port.fifosize >> 1;
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do {
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__raw_writel(xmit->buf[xmit->tail],
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dp->port.membase + HW_UARTDBGDR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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dp->port.icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (--count > 0);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&dp->port);
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if (uart_circ_empty(xmit))
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duart_stop_tx(&dp->port);
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}
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static void duart_modem_status(struct duart_port *dp)
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{
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unsigned int status, delta;
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status = __raw_readl(dp->port.membase + HW_UARTDBGFR) &
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(BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS);
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delta = status ^ dp->old_status;
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dp->old_status = status;
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if (!delta)
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return;
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if (delta & BM_UARTDBGFR_DCD)
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uart_handle_dcd_change(&dp->port, status & BM_UARTDBGFR_DCD);
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if (delta & BM_UARTDBGFR_DSR)
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dp->port.icount.dsr++;
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if (delta & BM_UARTDBGFR_CTS)
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uart_handle_cts_change(&dp->port, status & BM_UARTDBGFR_CTS);
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wake_up_interruptible(&dp->port.info->delta_msr_wait);
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}
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static irqreturn_t duart_int(int irq, void *dev_id)
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{
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int handled = 0;
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struct duart_port *dp = dev_id;
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unsigned int status, pass_counter = ISR_PASS_LIMIT;
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spin_lock(&dp->port.lock);
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status = __raw_readl(dp->port.membase + HW_UARTDBGMIS);
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while (status) {
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handled = 1;
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__raw_writel(status & ~(BM_UARTDBGMIS_TXMIS |
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BM_UARTDBGMIS_RTMIS |
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BM_UARTDBGMIS_RXMIS),
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dp->port.membase + HW_UARTDBGICR);
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if (status & (BM_UARTDBGMIS_RTMIS | BM_UARTDBGMIS_RXMIS))
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duart_rx_chars(dp);
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if (status & (BM_UARTDBGMIS_DSRMMIS |
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BM_UARTDBGMIS_DCDMMIS |
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BM_UARTDBGMIS_CTSMMIS | BM_UARTDBGMIS_RIMMIS))
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duart_modem_status(dp);
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if (status & BM_UARTDBGMIS_TXMIS)
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duart_tx_chars(dp);
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if (pass_counter-- == 0)
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break;
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status = __raw_readl(dp->port.membase + HW_UARTDBGMIS);
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};
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spin_unlock(&dp->port.lock);
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return IRQ_RETVAL(handled);
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}
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static unsigned int duart_tx_empty(struct uart_port *port)
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{
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struct duart_port *dp = (struct duart_port *)port;
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unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
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return status & (BM_UARTDBGFR_BUSY | BM_UARTDBGFR_TXFF) ?
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0 : TIOCSER_TEMT;
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}
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static unsigned int duart_get_mctrl(struct uart_port *port)
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{
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unsigned int result = 0;
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struct duart_port *dp = (struct duart_port *)port;
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unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
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#define TEST_AND_SET_BIT(uartbit, tiocmbit) do { \
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if (status & uartbit) \
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result |= tiocmbit; \
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} while (0)
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TEST_AND_SET_BIT(BM_UARTDBGFR_DCD, TIOCM_CAR);
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TEST_AND_SET_BIT(BM_UARTDBGFR_DSR, TIOCM_DSR);
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TEST_AND_SET_BIT(BM_UARTDBGFR_CTS, TIOCM_CTS);
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TEST_AND_SET_BIT(BM_UARTDBGFR_RI, TIOCM_RNG);
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#undef TEST_AND_SET_BIT
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if (force_cd)
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result |= TIOCM_CAR;
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return result;
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}
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static void duart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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unsigned int cr;
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struct duart_port *dp = (struct duart_port *)port;
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cr = __raw_readl(dp->port.membase + HW_UARTDBGCR);
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#define TEST_AND_SET_BIT(tiocmbit, uartbit) do { \
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if (mctrl & tiocmbit) \
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cr |= uartbit; \
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else \
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cr &= ~uartbit; \
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} while (0)
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TEST_AND_SET_BIT(TIOCM_RTS, BM_UARTDBGCR_RTS);
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TEST_AND_SET_BIT(TIOCM_DTR, BM_UARTDBGCR_DTR);
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TEST_AND_SET_BIT(TIOCM_OUT1, BM_UARTDBGCR_OUT1);
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TEST_AND_SET_BIT(TIOCM_OUT2, BM_UARTDBGCR_OUT2);
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TEST_AND_SET_BIT(TIOCM_LOOP, BM_UARTDBGCR_LBE);
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#undef TEST_AND_SET_BIT
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__raw_writel(cr, dp->port.membase + HW_UARTDBGCR);
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}
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static void duart_break_ctl(struct uart_port *port, int break_state)
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{
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unsigned long flags;
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unsigned int lcr_h;
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struct duart_port *dp = (struct duart_port *)port;
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spin_lock_irqsave(&dp->port.lock, flags);
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lcr_h = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
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if (break_state == -1)
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lcr_h |= BM_UARTDBGLCR_H_BRK;
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else
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lcr_h &= ~BM_UARTDBGLCR_H_BRK;
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__raw_writel(lcr_h, dp->port.membase + HW_UARTDBGLCR_H);
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spin_unlock_irqrestore(&dp->port.lock, flags);
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}
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static int duart_startup(struct uart_port *port)
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{
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u32 cr, lcr;
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int retval;
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struct duart_port *dp = (struct duart_port *)port;
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/*
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* Allocate the IRQ
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*/
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retval = request_irq(dp->port.irq, duart_int, 0, DUART_DEVID, dp);
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if (retval)
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return retval;
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/* wake up the UART */
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__raw_writel(0, dp->port.membase + HW_UARTDBGDR);
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__raw_writel(BF_UARTDBGIFLS_TXIFLSEL(BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF)
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|
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BF_UARTDBGIFLS_RXIFLSEL(BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF),
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dp->port.membase + HW_UARTDBGIFLS);
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/*
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* Provoke TX FIFO interrupt into asserting.
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*/
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cr = BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_RXE | BM_UARTDBGCR_TXE;
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__raw_writel(cr, dp->port.membase + HW_UARTDBGCR);
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lcr = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
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lcr |= BM_UARTDBGLCR_H_FEN;
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__raw_writel(lcr, dp->port.membase + HW_UARTDBGLCR_H);
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/*
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* initialise the old status of the modem signals
|
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*/
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dp->old_status = __raw_readl(dp->port.membase + HW_UARTDBGFR) &
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(BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS);
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/*
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* Finally, enable interrupts
|
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*/
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dp->im = BM_UARTDBGIMSC_RXIM | BM_UARTDBGIMSC_RTIM;
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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return 0;
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}
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static void duart_shutdown(struct uart_port *port)
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{
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unsigned long flags;
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unsigned int val;
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struct duart_port *dp = (struct duart_port *)port;
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/*
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* disable all interrupts
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*/
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spin_lock_irqsave(&dp->port.lock, flags);
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dp->im = 0;
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__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
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__raw_writel(0xffff, dp->port.membase + HW_UARTDBGICR);
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spin_unlock_irqrestore(&dp->port.lock, flags);
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free_irq(dp->port.irq, dp);
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|
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/*
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* disable the port
|
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*/
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__raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE,
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dp->port.membase + HW_UARTDBGCR);
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/*
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* disable break condition and fifos
|
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*/
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val = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
|
||||
val &= ~(BM_UARTDBGLCR_H_BRK | BM_UARTDBGLCR_H_FEN);
|
||||
__raw_writel(val, dp->port.membase + HW_UARTDBGLCR_H);
|
||||
}
|
||||
|
||||
static void
|
||||
duart_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
struct ktermios *old)
|
||||
{
|
||||
unsigned int lcr_h, old_cr;
|
||||
unsigned long flags;
|
||||
unsigned int baud, quot;
|
||||
|
||||
/*
|
||||
* Ask the core to calculate the divisor for us.
|
||||
*/
|
||||
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
|
||||
quot = (port->uartclk << 2) / baud;
|
||||
|
||||
switch (termios->c_cflag & CSIZE) {
|
||||
case CS5:
|
||||
lcr_h = BF_UARTDBGLCR_H_WLEN(0);
|
||||
break;
|
||||
case CS6:
|
||||
lcr_h = BF_UARTDBGLCR_H_WLEN(1);
|
||||
break;
|
||||
case CS7:
|
||||
lcr_h = BF_UARTDBGLCR_H_WLEN(2);
|
||||
break;
|
||||
default: /* CS8 */
|
||||
lcr_h = BF_UARTDBGLCR_H_WLEN(3);
|
||||
break;
|
||||
}
|
||||
if (termios->c_cflag & CSTOPB)
|
||||
lcr_h |= BM_UARTDBGLCR_H_STP2;
|
||||
if (termios->c_cflag & PARENB) {
|
||||
lcr_h |= BM_UARTDBGLCR_H_PEN;
|
||||
if (!(termios->c_cflag & PARODD))
|
||||
lcr_h |= BM_UARTDBGLCR_H_EPS;
|
||||
}
|
||||
lcr_h |= BM_UARTDBGLCR_H_FEN;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/*
|
||||
* Update the per-port timeout.
|
||||
*/
|
||||
uart_update_timeout(port, termios->c_cflag, baud);
|
||||
|
||||
port->read_status_mask = BM_UARTDBGRSR_ECR_OE;
|
||||
if (termios->c_iflag & INPCK)
|
||||
port->read_status_mask |= BM_UARTDBGRSR_ECR_FE |
|
||||
BM_UARTDBGRSR_ECR_PE;
|
||||
if (termios->c_iflag & (BRKINT | PARMRK))
|
||||
port->read_status_mask |= BM_UARTDBGRSR_ECR_BE;
|
||||
|
||||
/*
|
||||
* Characters to ignore
|
||||
*/
|
||||
port->ignore_status_mask = 0;
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
port->ignore_status_mask |= BM_UARTDBGRSR_ECR_FE |
|
||||
BM_UARTDBGRSR_ECR_PE;
|
||||
if (termios->c_iflag & IGNBRK) {
|
||||
port->ignore_status_mask |= BM_UARTDBGRSR_ECR_BE;
|
||||
/*
|
||||
* If we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
*/
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
port->ignore_status_mask |= BM_UARTDBGRSR_ECR_OE;
|
||||
}
|
||||
|
||||
if (UART_ENABLE_MS(port, termios->c_cflag))
|
||||
duart_enable_ms(port);
|
||||
|
||||
/* first, disable everything */
|
||||
old_cr = __raw_readl(port->membase + HW_UARTDBGCR);
|
||||
__raw_writel(0, port->membase + HW_UARTDBGCR);
|
||||
|
||||
/* Set baud rate */
|
||||
__raw_writel(quot & 0x3f, port->membase + HW_UARTDBGFBRD);
|
||||
__raw_writel(quot >> 6, port->membase + HW_UARTDBGIBRD);
|
||||
/*
|
||||
* ----------v----------v----------v----------v-----
|
||||
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
|
||||
* ----------^----------^----------^----------^-----
|
||||
*/
|
||||
__raw_writel(lcr_h, port->membase + HW_UARTDBGLCR_H);
|
||||
__raw_writel(old_cr, port->membase + HW_UARTDBGCR);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static const char *duart_type(struct uart_port *port)
|
||||
{
|
||||
return port->type == PORT_DUART ? DUART_DEVID : NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Release the memory region(s) being used by 'port'
|
||||
*/
|
||||
static void duart_release_port(struct uart_port *port)
|
||||
{
|
||||
release_mem_region(port->mapbase, PAGE_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Request the memory region(s) being used by 'port'
|
||||
*/
|
||||
static int duart_request_port(struct uart_port *port)
|
||||
{
|
||||
return request_mem_region(port->mapbase, PAGE_SIZE, DUART_DEVID)
|
||||
!= NULL ? 0 : -EBUSY;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure/autoconfigure the port.
|
||||
*/
|
||||
static void duart_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE) {
|
||||
port->type = PORT_DUART;
|
||||
duart_request_port(port);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* verify the new serial_struct (for TIOCSSERIAL).
|
||||
*/
|
||||
static int duart_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||
{
|
||||
int ret = 0;
|
||||
if (ser->type != PORT_UNKNOWN && ser->type != PORT_DUART)
|
||||
ret = -EINVAL;
|
||||
if (ser->irq < 0 || ser->irq >= NR_IRQS)
|
||||
ret = -EINVAL;
|
||||
if (ser->baud_base < 9600)
|
||||
ret = -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct uart_ops duart_pops = {
|
||||
.tx_empty = duart_tx_empty,
|
||||
.set_mctrl = duart_set_mctrl,
|
||||
.get_mctrl = duart_get_mctrl,
|
||||
.stop_tx = duart_stop_tx,
|
||||
.start_tx = duart_start_tx,
|
||||
.stop_rx = duart_stop_rx,
|
||||
.enable_ms = duart_enable_ms,
|
||||
.break_ctl = duart_break_ctl,
|
||||
.startup = duart_startup,
|
||||
.shutdown = duart_shutdown,
|
||||
.set_termios = duart_set_termios,
|
||||
.type = duart_type,
|
||||
.release_port = duart_release_port,
|
||||
.request_port = duart_request_port,
|
||||
.config_port = duart_config_port,
|
||||
.verify_port = duart_verify_port,
|
||||
};
|
||||
|
||||
static struct duart_port duart_port = {
|
||||
.port = {
|
||||
.iotype = SERIAL_IO_MEM,
|
||||
#ifdef CONFIG_MXS_EARLY_CONSOLE
|
||||
.membase = MXS_DEBUG_CONSOLE_VIRT,
|
||||
.mapbase = MXS_DEBUG_CONSOLE_PHYS,
|
||||
#endif
|
||||
.fifosize = 16,
|
||||
.ops = &duart_pops,
|
||||
.flags = ASYNC_BOOT_AUTOCONF,
|
||||
.line = 0,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE
|
||||
|
||||
static void
|
||||
duart_console_write(struct console *co, const char *s, unsigned int count)
|
||||
{
|
||||
struct uart_port *port = &duart_port.port;
|
||||
unsigned int status, old_cr;
|
||||
int i;
|
||||
/*
|
||||
* First save the CR then disable the interrupts
|
||||
*/
|
||||
old_cr = __raw_readl(port->membase + HW_UARTDBGCR);
|
||||
__raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE,
|
||||
port->membase + HW_UARTDBGCR);
|
||||
/*
|
||||
* Now, do each character
|
||||
*/
|
||||
for (i = 0; i < count; i++) {
|
||||
do {
|
||||
status = __raw_readl(port->membase + HW_UARTDBGFR);
|
||||
} while (status & BM_UARTDBGFR_TXFF);
|
||||
|
||||
__raw_writel(s[i], port->membase + HW_UARTDBGDR);
|
||||
if (s[i] == '\n') {
|
||||
do {
|
||||
status = __raw_readl(port->membase +
|
||||
HW_UARTDBGFR);
|
||||
} while (status & BM_UARTDBGFR_TXFF);
|
||||
__raw_writel('\r', port->membase + HW_UARTDBGDR);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Finally, wait for transmitter to become empty
|
||||
* and restore the TCR
|
||||
*/
|
||||
do {
|
||||
status = __raw_readl(port->membase + HW_UARTDBGFR);
|
||||
} while (status & BM_UARTDBGFR_BUSY);
|
||||
__raw_writel(old_cr, port->membase + HW_UARTDBGCR);
|
||||
}
|
||||
|
||||
static void __init
|
||||
duart_console_get_options(struct uart_port *port, int *baud,
|
||||
int *parity, int *bits)
|
||||
{
|
||||
if (__raw_readl(port->membase + HW_UARTDBGCR) & BM_UARTDBGCR_UARTEN) {
|
||||
unsigned int lcr_h, quot;
|
||||
lcr_h = __raw_readl(port->membase + HW_UARTDBGLCR_H);
|
||||
|
||||
*parity = 'n';
|
||||
if (lcr_h & BM_UARTDBGLCR_H_PEN) {
|
||||
if (lcr_h & BM_UARTDBGLCR_H_EPS)
|
||||
*parity = 'e';
|
||||
else
|
||||
*parity = 'o';
|
||||
}
|
||||
|
||||
if ((lcr_h & BM_UARTDBGLCR_H_WLEN) == BF_UARTDBGLCR_H_WLEN(2))
|
||||
*bits = 7;
|
||||
else
|
||||
*bits = 8;
|
||||
|
||||
quot = (__raw_readl(port->membase + HW_UARTDBGFBRD) & 0x3F) |
|
||||
__raw_readl(port->membase + HW_UARTDBGIBRD) << 6;
|
||||
if (quot == 0)
|
||||
quot = 1;
|
||||
*baud = (port->uartclk << 2) / quot;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init duart_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct uart_port *port;
|
||||
int baud = 115200;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
/*
|
||||
* Check whether an invalid uart number has been specified, and
|
||||
* if so, search for the first available port that does have
|
||||
* console support.
|
||||
*/
|
||||
if (co->index)
|
||||
return -EINVAL;
|
||||
|
||||
port = &duart_port.port;
|
||||
|
||||
if (duart_port.clk == NULL || IS_ERR(duart_port.clk)) {
|
||||
duart_port.clk = clk_get(NULL, "uart");
|
||||
if (duart_port.clk == NULL || IS_ERR(duart_port.clk))
|
||||
return -ENODEV;
|
||||
duart_port.port.uartclk = clk_get_rate(duart_port.clk);
|
||||
}
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
else
|
||||
duart_console_get_options(port, &baud, &parity, &bits);
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct console duart_console = {
|
||||
.name = "ttyAM",
|
||||
.write = duart_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = duart_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &duart_drv,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MXS_EARLY_CONSOLE
|
||||
static int __init duart_console_init(void)
|
||||
{
|
||||
register_console(&duart_console);
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(duart_console_init);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
static struct uart_driver duart_drv = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "ttyAM",
|
||||
.dev_name = "ttyAM",
|
||||
.major = SERIAL_DUART_MAJOR,
|
||||
.minor = SERIAL_DUART_MINOR,
|
||||
.nr = 1,
|
||||
#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE
|
||||
.cons = &duart_console,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __devinit duart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENOMEM;
|
||||
/*
|
||||
* Will use mapbase and membase here if !CONFIG_MXS_EARLY_CONSOLE,
|
||||
* or use the overridden values later if CONFIG_MXS_EARLY_CONSOLE
|
||||
*/
|
||||
duart_port.port.mapbase = res->start;
|
||||
duart_port.port.membase =
|
||||
(unsigned char __iomem *)IO_ADDRESS(res->start);
|
||||
|
||||
duart_port.port.irq = platform_get_irq(pdev, 0);
|
||||
if (duart_port.port.irq < 0)
|
||||
return -EINVAL;
|
||||
device_init_wakeup(&pdev->dev, 1);
|
||||
|
||||
duart_port.clk = clk_get(NULL, "uart");
|
||||
if (duart_port.clk == NULL || IS_ERR(duart_port.clk))
|
||||
return -ENODEV;
|
||||
duart_port.suspended = 0;
|
||||
duart_port.port.dev = &pdev->dev;
|
||||
duart_port.port.uartclk = clk_get_rate(duart_port.clk);
|
||||
uart_add_one_port(&duart_drv, &duart_port.port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devexit duart_remove(struct platform_device *pdev)
|
||||
{
|
||||
clk_put(duart_port.clk);
|
||||
uart_remove_one_port(&duart_drv, &duart_port.port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver duart_driver = {
|
||||
.probe = duart_probe,
|
||||
.remove = __devexit_p(duart_remove),
|
||||
.driver = {
|
||||
.name = "mxs-duart",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init duart_init(void)
|
||||
{
|
||||
int ret;
|
||||
ret = uart_register_driver(&duart_drv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&duart_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&duart_drv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit duart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&duart_driver);
|
||||
uart_unregister_driver(&duart_drv);
|
||||
}
|
||||
|
||||
module_init(duart_init);
|
||||
module_exit(duart_exit);
|
||||
module_param(force_cd, int, 0644);
|
||||
MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd/Freescale Inc");
|
||||
MODULE_DESCRIPTION("i.MXS debug uart");
|
||||
MODULE_LICENSE("GPL");
|
||||
301
drivers/serial/regs-duart.h
Normal file
301
drivers/serial/regs-duart.h
Normal file
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* Freescale UARTDBG Register Definitions
|
||||
*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* This file is created by xml file. Don't Edit it.
|
||||
*
|
||||
* Xml Revision: 1.21
|
||||
* Template revision: 26195
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM___UARTDBG_H
|
||||
#define __ARCH_ARM___UARTDBG_H
|
||||
|
||||
|
||||
#define HW_UARTDBGDR (0x00000000)
|
||||
|
||||
#define BP_UARTDBGDR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDR_RESERVED 12
|
||||
#define BM_UARTDBGDR_RESERVED 0x0000F000
|
||||
#define BF_UARTDBGDR_RESERVED(v) \
|
||||
(((v) << 12) & BM_UARTDBGDR_RESERVED)
|
||||
#define BM_UARTDBGDR_OE 0x00000800
|
||||
#define BM_UARTDBGDR_BE 0x00000400
|
||||
#define BM_UARTDBGDR_PE 0x00000200
|
||||
#define BM_UARTDBGDR_FE 0x00000100
|
||||
#define BP_UARTDBGDR_DATA 0
|
||||
#define BM_UARTDBGDR_DATA 0x000000FF
|
||||
#define BF_UARTDBGDR_DATA(v) \
|
||||
(((v) << 0) & BM_UARTDBGDR_DATA)
|
||||
|
||||
#define HW_UARTDBGRSR_ECR (0x00000004)
|
||||
|
||||
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
|
||||
#define BP_UARTDBGRSR_ECR_EC 4
|
||||
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
|
||||
#define BF_UARTDBGRSR_ECR_EC(v) \
|
||||
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
|
||||
#define BM_UARTDBGRSR_ECR_OE 0x00000008
|
||||
#define BM_UARTDBGRSR_ECR_BE 0x00000004
|
||||
#define BM_UARTDBGRSR_ECR_PE 0x00000002
|
||||
#define BM_UARTDBGRSR_ECR_FE 0x00000001
|
||||
|
||||
#define HW_UARTDBGFR (0x00000018)
|
||||
|
||||
#define BP_UARTDBGFR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGFR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
|
||||
#define BP_UARTDBGFR_RESERVED 9
|
||||
#define BM_UARTDBGFR_RESERVED 0x0000FE00
|
||||
#define BF_UARTDBGFR_RESERVED(v) \
|
||||
(((v) << 9) & BM_UARTDBGFR_RESERVED)
|
||||
#define BM_UARTDBGFR_RI 0x00000100
|
||||
#define BM_UARTDBGFR_TXFE 0x00000080
|
||||
#define BM_UARTDBGFR_RXFF 0x00000040
|
||||
#define BM_UARTDBGFR_TXFF 0x00000020
|
||||
#define BM_UARTDBGFR_RXFE 0x00000010
|
||||
#define BM_UARTDBGFR_BUSY 0x00000008
|
||||
#define BM_UARTDBGFR_DCD 0x00000004
|
||||
#define BM_UARTDBGFR_DSR 0x00000002
|
||||
#define BM_UARTDBGFR_CTS 0x00000001
|
||||
|
||||
#define HW_UARTDBGILPR (0x00000020)
|
||||
|
||||
#define BP_UARTDBGILPR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
|
||||
#define BP_UARTDBGILPR_ILPDVSR 0
|
||||
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
|
||||
#define BF_UARTDBGILPR_ILPDVSR(v) \
|
||||
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
|
||||
|
||||
#define HW_UARTDBGIBRD (0x00000024)
|
||||
|
||||
#define BP_UARTDBGIBRD_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
|
||||
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
|
||||
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
|
||||
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
|
||||
|
||||
#define HW_UARTDBGFBRD (0x00000028)
|
||||
|
||||
#define BP_UARTDBGFBRD_UNAVAILABLE 8
|
||||
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGFBRD_RESERVED 6
|
||||
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
|
||||
#define BF_UARTDBGFBRD_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
|
||||
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
|
||||
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
|
||||
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
|
||||
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
|
||||
|
||||
#define HW_UARTDBGLCR_H (0x0000002c)
|
||||
|
||||
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
|
||||
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
|
||||
#define BP_UARTDBGLCR_H_RESERVED 8
|
||||
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
|
||||
#define BF_UARTDBGLCR_H_RESERVED(v) \
|
||||
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
|
||||
#define BM_UARTDBGLCR_H_SPS 0x00000080
|
||||
#define BP_UARTDBGLCR_H_WLEN 5
|
||||
#define BM_UARTDBGLCR_H_WLEN 0x00000060
|
||||
#define BF_UARTDBGLCR_H_WLEN(v) \
|
||||
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
|
||||
#define BM_UARTDBGLCR_H_FEN 0x00000010
|
||||
#define BM_UARTDBGLCR_H_STP2 0x00000008
|
||||
#define BM_UARTDBGLCR_H_EPS 0x00000004
|
||||
#define BM_UARTDBGLCR_H_PEN 0x00000002
|
||||
#define BM_UARTDBGLCR_H_BRK 0x00000001
|
||||
|
||||
#define HW_UARTDBGCR (0x00000030)
|
||||
|
||||
#define BP_UARTDBGCR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGCR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
|
||||
#define BM_UARTDBGCR_CTSEN 0x00008000
|
||||
#define BM_UARTDBGCR_RTSEN 0x00004000
|
||||
#define BM_UARTDBGCR_OUT2 0x00002000
|
||||
#define BM_UARTDBGCR_OUT1 0x00001000
|
||||
#define BM_UARTDBGCR_RTS 0x00000800
|
||||
#define BM_UARTDBGCR_DTR 0x00000400
|
||||
#define BM_UARTDBGCR_RXE 0x00000200
|
||||
#define BM_UARTDBGCR_TXE 0x00000100
|
||||
#define BM_UARTDBGCR_LBE 0x00000080
|
||||
#define BP_UARTDBGCR_RESERVED 3
|
||||
#define BM_UARTDBGCR_RESERVED 0x00000078
|
||||
#define BF_UARTDBGCR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGCR_RESERVED)
|
||||
#define BM_UARTDBGCR_SIRLP 0x00000004
|
||||
#define BM_UARTDBGCR_SIREN 0x00000002
|
||||
#define BM_UARTDBGCR_UARTEN 0x00000001
|
||||
|
||||
#define HW_UARTDBGIFLS (0x00000034)
|
||||
|
||||
#define BP_UARTDBGIFLS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
|
||||
#define BP_UARTDBGIFLS_RESERVED 6
|
||||
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
|
||||
#define BF_UARTDBGIFLS_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
|
||||
#define BP_UARTDBGIFLS_RXIFLSEL 3
|
||||
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
|
||||
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
|
||||
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT 0x0
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
|
||||
#define BP_UARTDBGIFLS_TXIFLSEL 0
|
||||
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
|
||||
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
|
||||
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT 0x0
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
|
||||
|
||||
#define HW_UARTDBGIMSC (0x00000038)
|
||||
|
||||
#define BP_UARTDBGIMSC_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
|
||||
#define BP_UARTDBGIMSC_RESERVED 11
|
||||
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGIMSC_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
|
||||
#define BM_UARTDBGIMSC_OEIM 0x00000400
|
||||
#define BM_UARTDBGIMSC_BEIM 0x00000200
|
||||
#define BM_UARTDBGIMSC_PEIM 0x00000100
|
||||
#define BM_UARTDBGIMSC_FEIM 0x00000080
|
||||
#define BM_UARTDBGIMSC_RTIM 0x00000040
|
||||
#define BM_UARTDBGIMSC_TXIM 0x00000020
|
||||
#define BM_UARTDBGIMSC_RXIM 0x00000010
|
||||
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
|
||||
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
|
||||
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
|
||||
#define BM_UARTDBGIMSC_RIMIM 0x00000001
|
||||
|
||||
#define HW_UARTDBGRIS (0x0000003c)
|
||||
|
||||
#define BP_UARTDBGRIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGRIS_RESERVED 11
|
||||
#define BM_UARTDBGRIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGRIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
|
||||
#define BM_UARTDBGRIS_OERIS 0x00000400
|
||||
#define BM_UARTDBGRIS_BERIS 0x00000200
|
||||
#define BM_UARTDBGRIS_PERIS 0x00000100
|
||||
#define BM_UARTDBGRIS_FERIS 0x00000080
|
||||
#define BM_UARTDBGRIS_RTRIS 0x00000040
|
||||
#define BM_UARTDBGRIS_TXRIS 0x00000020
|
||||
#define BM_UARTDBGRIS_RXRIS 0x00000010
|
||||
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
|
||||
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
|
||||
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
|
||||
#define BM_UARTDBGRIS_RIRMIS 0x00000001
|
||||
|
||||
#define HW_UARTDBGMIS (0x00000040)
|
||||
|
||||
#define BP_UARTDBGMIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGMIS_RESERVED 11
|
||||
#define BM_UARTDBGMIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGMIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
|
||||
#define BM_UARTDBGMIS_OEMIS 0x00000400
|
||||
#define BM_UARTDBGMIS_BEMIS 0x00000200
|
||||
#define BM_UARTDBGMIS_PEMIS 0x00000100
|
||||
#define BM_UARTDBGMIS_FEMIS 0x00000080
|
||||
#define BM_UARTDBGMIS_RTMIS 0x00000040
|
||||
#define BM_UARTDBGMIS_TXMIS 0x00000020
|
||||
#define BM_UARTDBGMIS_RXMIS 0x00000010
|
||||
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
|
||||
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
|
||||
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
|
||||
#define BM_UARTDBGMIS_RIMMIS 0x00000001
|
||||
|
||||
#define HW_UARTDBGICR (0x00000044)
|
||||
|
||||
#define BP_UARTDBGICR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGICR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
|
||||
#define BP_UARTDBGICR_RESERVED 11
|
||||
#define BM_UARTDBGICR_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGICR_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGICR_RESERVED)
|
||||
#define BM_UARTDBGICR_OEIC 0x00000400
|
||||
#define BM_UARTDBGICR_BEIC 0x00000200
|
||||
#define BM_UARTDBGICR_PEIC 0x00000100
|
||||
#define BM_UARTDBGICR_FEIC 0x00000080
|
||||
#define BM_UARTDBGICR_RTIC 0x00000040
|
||||
#define BM_UARTDBGICR_TXIC 0x00000020
|
||||
#define BM_UARTDBGICR_RXIC 0x00000010
|
||||
#define BM_UARTDBGICR_DSRMIC 0x00000008
|
||||
#define BM_UARTDBGICR_DCDMIC 0x00000004
|
||||
#define BM_UARTDBGICR_CTSMIC 0x00000002
|
||||
#define BM_UARTDBGICR_RIMIC 0x00000001
|
||||
|
||||
#define HW_UARTDBGDMACR (0x00000048)
|
||||
|
||||
#define BP_UARTDBGDMACR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDMACR_RESERVED 3
|
||||
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
|
||||
#define BF_UARTDBGDMACR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
|
||||
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
|
||||
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
|
||||
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
|
||||
#endif /* __ARCH_ARM___UARTDBG_H */
|
||||
Reference in New Issue
Block a user