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ENGR00124814-1 fb: Add i.MX EPDC fb driver
Added basic EPDC driver, including support for PXP conversions (rotation, auto-waveform selection, CSC). Self-clock gating also supported. Signed-off-by: Danny Nold <dannynold@freescale.com>
This commit is contained in:
Danny Nold
Matt Sealey
@@ -71,6 +71,17 @@ config FB_MXC_EPSON_PANEL
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endmenu
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config FB_MXC_EINK_PANEL
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depends on FB_MXC
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depends on DMA_ENGINE
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select FB_DEFERRED_IO
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tristate "E-Ink Panel Framebuffer"
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config FB_MXC_EINK_AUTO_UPDATE_MODE
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bool "E-Ink Auto-update Mode Support"
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default n
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depends on FB_MXC_EINK_PANEL
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choice
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prompt "Async Panel Interface Type"
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depends on FB_MXC_ASYNC_PANEL && FB_MXC
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@@ -20,3 +20,4 @@ obj-$(CONFIG_FB_MXC_TVOUT_TVE) += tve.o
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obj-$(CONFIG_FB_MXC_LDB) += ldb.o
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obj-$(CONFIG_FB_MXC_CH7026) += mxcfb_ch7026.o
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#obj-$(CONFIG_FB_MODE_HELPERS) += mxc_edid.o
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obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o
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301
drivers/video/mxc/epdc_regs.h
Normal file
301
drivers/video/mxc/epdc_regs.h
Normal file
@@ -0,0 +1,301 @@
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __EPDC_REGS_INCLUDED__
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#define __EPDC_REGS_INCLUDED__
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extern void __iomem *epdc_base;
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//*************************************
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// Register addresses
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//*************************************
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#define EPDC_CTRL (epdc_base + 0x000)
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#define EPDC_CTRL_SET (epdc_base + 0x004)
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#define EPDC_CTRL_CLEAR (epdc_base + 0x008)
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#define EPDC_CTRL_TOGGLE (epdc_base + 0x00C)
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#define EPDC_WVADDR (epdc_base + 0x020)
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#define EPDC_WB_ADDR (epdc_base + 0x030)
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#define EPDC_RES (epdc_base + 0x040)
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#define EPDC_FORMAT (epdc_base + 0x050)
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#define EPDC_FORMAT_SET (epdc_base + 0x054)
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#define EPDC_FORMAT_CLEAR (epdc_base + 0x058)
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#define EPDC_FORMAT_TOGGLE (epdc_base + 0x05C)
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#define EPDC_FIFOCTRL (epdc_base + 0x0A0)
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#define EPDC_FIFOCTRL_SET (epdc_base + 0x0A4)
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#define EPDC_FIFOCTRL_CLEAR (epdc_base + 0x0A8)
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#define EPDC_FIFOCTRL_TOGGLE (epdc_base + 0x0AC)
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#define EPDC_UPD_ADDR (epdc_base + 0x100)
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#define EPDC_UPD_CORD (epdc_base + 0x120)
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#define EPDC_UPD_SIZE (epdc_base + 0x140)
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#define EPDC_UPD_CTRL (epdc_base + 0x160)
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#define EPDC_UPD_FIXED (epdc_base + 0x180)
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#define EPDC_TEMP (epdc_base + 0x1A0)
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#define EPDC_TCE_CTRL (epdc_base + 0x200)
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#define EPDC_TCE_SDCFG (epdc_base + 0x220)
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#define EPDC_TCE_GDCFG (epdc_base + 0x240)
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#define EPDC_TCE_HSCAN1 (epdc_base + 0x260)
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#define EPDC_TCE_HSCAN2 (epdc_base + 0x280)
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#define EPDC_TCE_VSCAN (epdc_base + 0x2A0)
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#define EPDC_TCE_OE (epdc_base + 0x2C0)
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#define EPDC_TCE_POLARITY (epdc_base + 0x2E0)
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#define EPDC_TCE_TIMING1 (epdc_base + 0x300)
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#define EPDC_TCE_TIMING2 (epdc_base + 0x310)
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#define EPDC_TCE_TIMING3 (epdc_base + 0x320)
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#define EPDC_IRQ_MASK (epdc_base + 0x400)
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#define EPDC_IRQ_MASK_SET (epdc_base + 0x404)
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#define EPDC_IRQ_MASK_CLEAR (epdc_base + 0x408)
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#define EPDC_IRQ_MASK_TOGGLE (epdc_base + 0x40C)
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#define EPDC_IRQ (epdc_base + 0x420)
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#define EPDC_IRQ_SET (epdc_base + 0x424)
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#define EPDC_IRQ_CLEAR (epdc_base + 0x428)
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#define EPDC_IRQ_TOGGLE (epdc_base + 0x42C)
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#define EPDC_STATUS_LUTS (epdc_base + 0x440)
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#define EPDC_STATUS_LUTS_SET (epdc_base + 0x444)
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#define EPDC_STATUS_LUTS_CLEAR (epdc_base + 0x448)
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#define EPDC_STATUS_LUTS_TOGGLE (epdc_base + 0x44C)
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#define EPDC_STATUS_NEXTLUT (epdc_base + 0x460)
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#define EPDC_STATUS_COL (epdc_base + 0x480)
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#define EPDC_STATUS (epdc_base + 0x4A0)
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#define EPDC_STATUS_SET (epdc_base + 0x4A4)
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#define EPDC_STATUS_CLEAR (epdc_base + 0x4A8)
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#define EPDC_STATUS_TOGGLE (epdc_base + 0x4AC)
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#define EPDC_DEBUG (epdc_base + 0x500)
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#define EPDC_DEBUG_LUT0 (epdc_base + 0x540)
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#define EPDC_DEBUG_LUT1 (epdc_base + 0x550)
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#define EPDC_DEBUG_LUT2 (epdc_base + 0x560)
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#define EPDC_DEBUG_LUT3 (epdc_base + 0x570)
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#define EPDC_DEBUG_LUT4 (epdc_base + 0x580)
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#define EPDC_DEBUG_LUT5 (epdc_base + 0x590)
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#define EPDC_DEBUG_LUT6 (epdc_base + 0x5A0)
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#define EPDC_DEBUG_LUT7 (epdc_base + 0x5B0)
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#define EPDC_DEBUG_LUT8 (epdc_base + 0x5C0)
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#define EPDC_DEBUG_LUT9 (epdc_base + 0x5D0)
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#define EPDC_DEBUG_LUT10 (epdc_base + 0x5E0)
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#define EPDC_DEBUG_LUT11 (epdc_base + 0x5F0)
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#define EPDC_DEBUG_LUT12 (epdc_base + 0x600)
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#define EPDC_DEBUG_LUT13 (epdc_base + 0x610)
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#define EPDC_DEBUG_LUT14 (epdc_base + 0x620)
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#define EPDC_DEBUG_LUT15 (epdc_base + 0x630)
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#define EPDC_GPIO (epdc_base + 0x700)
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#define EPDC_VERSION (epdc_base + 0x7F0)
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/*
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* Register field definitions
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*/
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enum {
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/* EPDC_CTRL field values */
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EPDC_CTRL_SFTRST = 0x80000000,
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EPDC_CTRL_CLKGATE = 0x40000000,
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EPDC_CTRL_SRAM_POWERDOWN = 0x100,
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EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
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EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
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EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
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EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
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EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
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EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
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EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
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EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
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EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
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EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
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EPDC_CTRL_BURST_LEN_8_8 = 0x1,
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EPDC_CTRL_BURST_LEN_8_16 = 0,
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/* EPDC_RES field values */
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EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
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EPDC_RES_VERTICAL_OFFSET = 16,
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EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
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EPDC_RES_HORIZONTAL_OFFSET = 0,
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/* EPDC_FORMAT field values */
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EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
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EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
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EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
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EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
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EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
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EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
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EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
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EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
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EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
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EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
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EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
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/* EPDC_FIFOCTRL field values */
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EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
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EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
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EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
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EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
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EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
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EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
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EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
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/* EPDC_UPD_CORD field values */
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EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
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EPDC_UPD_CORD_YCORD_OFFSET = 16,
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EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
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EPDC_UPD_CORD_XCORD_OFFSET = 0,
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/* EPDC_UPD_SIZE field values */
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EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
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EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
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EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
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EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
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/* EPDC_UPD_CTRL field values */
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EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
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EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000,
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EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
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EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
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EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
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EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
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/* EPDC_UPD_FIXED field values */
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EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
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EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
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EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
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EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
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EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
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EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
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/* EPDC_TCE_CTRL field values */
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EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
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EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
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EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
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EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
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EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
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EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
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EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
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EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
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EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
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EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
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EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
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EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
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EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
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EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
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EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
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EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
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/* EPDC_TCE_SDCFG field values */
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EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
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EPDC_TCE_SDCFG_SDSHR = 0x100000,
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EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
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EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
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EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
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EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
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EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
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EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
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EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
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/* EPDC_TCE_GDCFG field values */
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EPDC_TCE_SDCFG_GDRL = 0x10,
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EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
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EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
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EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
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/* EPDC_TCE_HSCAN1 field values */
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EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
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EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
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EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
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EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
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/* EPDC_TCE_HSCAN2 field values */
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EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
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EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
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EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
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EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
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/* EPDC_TCE_VSCAN field values */
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EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
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EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
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EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
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EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
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EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
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EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
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/* EPDC_TCE_OE field values */
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EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
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EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
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EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
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EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
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EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
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EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
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EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
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EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
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/* EPDC_TCE_POLARITY field values */
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EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
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EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
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EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
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EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
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EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
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/* EPDC_TCE_TIMING1 field values */
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EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
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EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
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EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
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EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
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EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
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EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
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EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
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EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
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EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
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/* EPDC_TCE_TIMING2 field values */
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EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
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EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
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EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
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EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
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/* EPDC_TCE_TIMING3 field values */
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EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
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EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
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EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
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EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
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/* EPDC_IRQ_MASK/EPDC_IRQ field values */
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EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
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EPDC_IRQ_LUT_COL_IRQ = 0x20000,
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EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
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EPDC_IRQ_FRAME_END_IRQ = 0x80000,
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EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
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EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
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/* EPDC_STATUS_NEXTLUT field values */
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EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
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EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xF,
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EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
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/* EPDC_STATUS field values */
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EPDC_STATUS_LUTS_UNDERRUN = 0x4,
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EPDC_STATUS_LUTS_BUSY = 0x2,
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EPDC_STATUS_WB_BUSY = 0x1,
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/* EPDC_DEBUG field values */
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EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
|
||||
EPDC_DEBUG_COLLISION_OFF = 0x1,
|
||||
|
||||
/* EPDC_GPIO field values */
|
||||
EPDC_GPIO_PWRCOM = 0x40,
|
||||
EPDC_GPIO_PWRCTRL_MASK = 0x3C,
|
||||
EPDC_GPIO_PWRCTRL_OFFSET = 2,
|
||||
EPDC_GPIO_BDR_MASK = 0x3,
|
||||
EPDC_GPIO_BDR_OFFSET = 0,
|
||||
};
|
||||
|
||||
#endif /* __EPDC_REGS_INCLUDED__ */
|
||||
3067
drivers/video/mxc/mxc_epdc_fb.c
Normal file
3067
drivers/video/mxc/mxc_epdc_fb.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -58,6 +58,56 @@ struct mxcfb_gamma {
|
||||
int slopek[16];
|
||||
};
|
||||
|
||||
struct mxcfb_rect {
|
||||
__u32 top;
|
||||
__u32 left;
|
||||
__u32 width;
|
||||
__u32 height;
|
||||
};
|
||||
|
||||
#define GRAYSCALE_8BIT 0x1
|
||||
#define GRAYSCALE_8BIT_INVERTED 0x2
|
||||
|
||||
#define AUTO_UPDATE_MODE_REGION_MODE 0
|
||||
#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1
|
||||
|
||||
#define UPDATE_MODE_PARTIAL 0x0
|
||||
#define UPDATE_MODE_FULL 0x1
|
||||
|
||||
#define WAVEFORM_MODE_AUTO 257
|
||||
|
||||
#define TEMP_USE_AMBIENT 0x1000
|
||||
|
||||
struct mxcfb_alt_buffer_data {
|
||||
__u32 phys_addr;
|
||||
__u32 width; /* width of entire buffer */
|
||||
__u32 height; /* height of entire buffer */
|
||||
struct mxcfb_rect alt_update_region; /* region within buffer to update */
|
||||
};
|
||||
|
||||
struct mxcfb_update_data {
|
||||
struct mxcfb_rect update_region;
|
||||
__u32 waveform_mode;
|
||||
__u32 update_mode;
|
||||
__u32 update_marker;
|
||||
int temp;
|
||||
int use_alt_buffer;
|
||||
struct mxcfb_alt_buffer_data alt_buffer_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure used to define waveform modes for driver
|
||||
* Needed for driver to perform auto-waveform selection
|
||||
*/
|
||||
struct mxcfb_waveform_modes {
|
||||
int mode_init;
|
||||
int mode_du;
|
||||
int mode_gc4;
|
||||
int mode_gc8;
|
||||
int mode_gc16;
|
||||
int mode_gc32;
|
||||
};
|
||||
|
||||
#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
|
||||
#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
|
||||
#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
|
||||
@@ -69,6 +119,13 @@ struct mxcfb_gamma {
|
||||
#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t)
|
||||
#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t)
|
||||
|
||||
/* IOCTLs for E-ink panel updates */
|
||||
#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes)
|
||||
#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t)
|
||||
#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32)
|
||||
#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data)
|
||||
#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOW('F', 0x2F, __u32)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
extern struct fb_videomode mxcfb_modedb[];
|
||||
@@ -80,13 +137,6 @@ enum {
|
||||
MXCFB_REFRESH_PARTIAL,
|
||||
};
|
||||
|
||||
struct mxcfb_rect {
|
||||
u32 top;
|
||||
u32 left;
|
||||
u32 width;
|
||||
u32 height;
|
||||
};
|
||||
|
||||
int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
|
||||
struct mxcfb_rect *update_region);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user