EPDC driver updated to fail gracefully when the display pmic cannot
be acquired. No longer hanging.
Signed-off-by: Danny Nold <dannynold@freescale.com>
The initial VCOM voltage should be configured once. Previously it was
left unconfigured. Now, the VCOM value is checked the first time
through, and if it is not set correctly, it will be fixed.
Signed-off-by: Danny Nold <dannynold@freescale.com>
A number of Maxim 17135 parts were found to require longer than the
computed max wait time to assert the PWR_GOOD signal, indicating that
display power is up and valid. This fix increases the timeout,
preventing regulator_enable calls from prematurely bailing out
and reporting errors.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Added basic EPDC driver, including support for PXP conversions (rotation,
auto-waveform selection, CSC). Self-clock gating also supported.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Use Common DMA-Engine framework to implement ePXP driver
Use a dma client driver to access ePxP staff.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
support imx53 evk board OTG and Host1 vbus active
and inactive to low the power consume, fix fsl_otg.c
build failt, add vbus power control function pointer
in struct fsl_usb2_platform_data.
Signed-off-by: Hu hui <b29976@freescale.com>
The probe is called only pdev->name is the same with driver_name,
So the statement for name judgement is useless.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
1) Add OV3640 camera QXGA configuration at 7.5fps support.
2) Use double buffer to workaround tearing issue when capturing
still image.
Signed-off-by: Liu Ying <b17645@freescale.com>
1 correct the pata platform device resource check codes
2 Change the end statment of the sdhc1 det pin
iomux definition on mx51 board from ',' to ';'.
3 sdhc driver max blk count on MX31, sinc
customer report that the emmc would be failed when
the blk count is more than 32.
Signed-off-by: Richard Zhu <r65037@freescale.com>
The default partitions are missing in MX53 SPI NOR MTD.
It's because spi nor driver and mx53 msl include different
header files. It causes struct definitions are different.
For i.MX SPI nor driver, need to use asm/mach/flash.h by
aligning with NAND driver.
Signed-off-by: Lily Zhang <r58066@freescale.com>
Call pan display frequently, after a long time, it has chance to show
below error msg:
Error updating SDC buf ....
check buffer busy before update buffer function call to avoid such
issue.
Signed-off-by: Jason Chen <b02280@freescale.com>
1)Medium motion and low motion:
Frame(n)'s even field is used for Previous channel,
Frame(n+1)'s odd field is used for Current channel and
Frame(n+1)'s even field is used for Next channel to generate
de-interlaced Frame(n+1).
2)High motion:
Frame(n)'s odd field is used for Current channel to generate
de-interlaced Frame(n).
Signed-off-by: Liu Ying <b17645@freescale.com>
1) Read buffer 1 ready register before setting buffer 1 ready.
2) Enable ISP in IPU_CONF when using VDI.
3) Fix link issue between MEM_VDI_PRP_VF_MEM and MEM_ROT_VF_MEM.
4) Correct g_channel_init_mask value.
5) Use fixed top field for VDI.
Signed-off-by: Liu Ying <b17645@freescale.com>
The L2 Switch have 4 ports,
and the port0 can be used as ethernet port
when Switch is configured to operate
as a 3-Port Switch (Switch Mode).
Signed-off-by: Niu Xule <b23300@freescale.com>
The support for YUV422 different combinations are added
The YUV422 is supported for DI1 interface for 720P frames with 16bits bus only:
di1_primary video=mxcdi1fb:YUYV16,720P60
To define required YUV422 format use one of:
YUYV16
YVYU16
UYVY16
VYUY16
Signed-off-by: Mark Gutman <r58412@freescale.com>
This can be used for AHCI-compatible interfaces implemented inside
System-On-Chip solutions, or AHCI devices connected via localbus.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This patch should contain no functional changes, just moves code
around.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Factor out some ahci_em_messages handling code from ahci_init_one().
We would like to reuse it for non-PCI devices.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
To make the function bus-independand we have to get rid of
"struct pci_dev *", so let's pass just "struct devce *".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
To make the function generic we have to get rid of "struct pci_dev *",
so let's pass just a "struct devce *".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Make ahci_save_initial_config() a bit more generic by introducing
force_port_map and mask_port_map arguments.
Move PCI stuff into ahci_pci_save_initial_config().
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Currently the driver uses host->iomap to store all the iomapped BARs
of a PCI device (while AHCI devices actually use just a single memory
window).
We're going to teach AHCI to work with non-PCI buses, so there are two
options to make this work:
1. "fake" host->iomap array for non-PCI devices, and place the needed
address at iomap[AHCI_PCI_BAR];
2. Get rid of host->iomap usage, instead introduce a private mmio
field.
This patch implements the second option.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
pp->active_link is not reliable when FBS is enabled.
Both PORT_SCR_ACT and PORT_CMD_ISSUE should be checked
because mixed NCQ and non-NCQ commands may be in flight.
Signed-off-by: Shane Huang <shane.huang@amd.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Make some variables in ahci and a function in pata_pcmcia static, as found
using sparse.
Signed-off-by: Robert Hancock <hancockrwd@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
I obseved there is a sata_async_notification() for every ahci
interrupt. But the async notification does nothing (this is hard
disk drive and no pmp). This cause cpu wastes some time on sntf
register access.
It appears ICH AHCI doesn't support SNotification register, but the
controller reports it does. After quirking it, the async notification
disappears.
PS. it appears all ICH don't support SNotification register from ICH
manual, don't know if we need quirk all ICH. I don't have machines
with all kinds of ICH.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Commit f80ae7e45a0e03da188494c6e947a5c8b0cdfb4a
ahci: filter FPDMA non-zero offset enable for Aspire 3810T
breaks the current git build for configurations that don't define
CONFIG_ATA_ACPI.
This adds an ifdef wrapper to ahci_gtf_filter_workaround.
Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Curiously, Aspire 3810T issues many SATA feature enable commands via
_GTF, of which one is invalid and another is not supported by the
drive. In the process, it also enables FPDMA non-zero offset.
However, the feature also needs to be supported and enabled from the
controller and it's wrong to enable it from _GTF unless the controller
can do it by default.
Currently, this ends up enabling FPDMA non-zero offset only on the
drive side leading to NCQ command failures and eventual disabling of
NCQ. This patch makes libata filter out FPDMA non-zero offset enable
for the machine.
This was reported by Marcus Meissner in bnc#522790.
https://bugzilla.novell.com/show_bug.cgi?id=522790
Reported-by: Marcus Meissner <meissner@novell.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Update the AHCI driver to display all of the HBA capabilities defined in the
AHCI 1.3 specification. Some of these are in a new CAP2 (HBA Capabilities
Extended) register which is only defined on AHCI 1.2 or later. The spec says
that undefined registers should always return 0 on read, but to be safe we
assume a value of 0 unless the controller reports AHCI version 1.2 or later.
The value can also be retrieved through sysfs as with the existing capability
field.
For example, on an Intel Ibex Peak (PCH) controller:
ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pmp pio slum part ems
sxs apst
We don't do anything special with the new flags yet.
Also, change the code that displays the flags to use the same bit enumerations
that are used to control actual operation.
Signed-off-by: Robert Hancock <hancockrwd@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This patch refines ahci_kick_engine() after discussion with Tejun about
FBS(FIS-based switching) support preparation:
a. Kill @force_restart and always kick the engine. The only case where
@force_restart is zero is when it's called from ahci_p5wdh_hardreset()
Actually at that point, BSY is pretty much guaranteed to be set.
b. If PMP is attached, ignore busy and always do CLO. (AHCI-1.3 9.2)
Signed-off-by: Shane Huang <shane.huang@amd.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
