Rework the display command line options to not require new option for
every new display. Add mxcdi0fb/mxcdi1fb option <fmt> and to tell system
what kind of display device is going to use.
Use "di1_primary" to make DI1 the primary display (i.e. fb0).
The display selection is done using video= parameter.
For example on imx51:
di di_fmt video_mode
DVI: 0 RGB24 mxcdi0fb:800x600M-16@60 etc
DVI-HDMI: 0 RGB24 mxcdi0fb:720P60
LVDS: 0 LVDS666 mxcdi0fb:XGA
WVGA lcd: 1 RGB565 mxcdi1fb:800x480M-16@55
TVE: 1 YUV444 mxcdi1fb:TV-NTSC
mxcdi1fb:TV-PAL
mxcdi1fb:720P60
For example on imx53:
di di_fmt video_mode
DVI: 0 RGB24 mxcdi0fb:800x600M-16@60 etc
DVI-HDMI: 0 RGB24 mxcdi0fb:720P60
WVGA lcd: 0 RGB565 mxcdi0fb:800x480M-16@55
TVE: 1 YUV444 mxcdi1fb:TV-NTSC
mxcdi1fb:TV-PAL
mxcdi1fb:720P60
If you want to set NTSC tv as primary display, and make second display
DI0 as DVI 1024x768 resolution, just add
"di1_primary video=mxcdi0fb:RGB24,1024x768M-16@60 video=mxcdi1fb:YUV444,TV-NTSC"
to cmdline.
Signed-off-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Jason Chen <b02280@freescale.com>
Setting the AXI ID on to 1 for sync display channels on MX53 causes
display flickering when system is heavily loaded.
Signed-off-by: Rob Herring <r.herring@freescale.com>
(cherry picked from commit 30df5734fcea4146b60f35238aaf5368f3392b0d)
1. One variable declaration was controlled by ARCH_MXS, but it was
used by other platforms, So remove the ARCH_MXS flags controlling.
2. Added judgement for FEC 1588 interrupt enablement.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
bypass bit set to wrong possition. So ssp alays use xtal.
mmc use ssp module divider instead of ssp clock source
Signed-off-by: Frank Li <Frank.Li@freescale.com>
If you boot up and then go into suspend mode, the clk_busy_wait()
function causes a timeout in the ssp_set_rate function because
the rate is being set while the clock is disable
resulting in the busy bit staying false.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
MX23/MX28: Add power optimization functionality to cpufreq
Add working HCLK autoslow interface and functionality
to cpufreq and clock driver.
Add lowering of x_clk for lowest clock speed state.
MX23: Fix 392MHz voltage value from 1475000 to 1450000.
This lower value is all that is needed when using 130MHz hclk.
MX23: change emiclk from 120000 to 130910 for 360000 cpu entry.
130910 allows more bandwidth and avoids momentary halting
of sdram traffic required between emiclk changes.
MX23/28: fiix problem with previous hclk autoslow
implementation causing a corruption of the CLKCTRL
_HBUS register. The regular hclk divider was getting
set to 21 or 22 or 23 when the LCD was turned off.
This very low speed starves the system.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
Disabling PLL3 was causing failure to boot from MMC slot0.
Move SDHC clocks to be sourced from PLL2 instead of PLL3.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Fixed long-term video playback issue due to incorrect increment of
clock usecount.
Fixed various bugs associated with system entering LP-APM mode.
Fixed incorrect enabling of PLL3 that was not allowing system to enter
LP-APM mode if TVE was built in.
EMI_GARB clock needs to be enabled when certain clock dividers are changed.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
- add set_rate functionality for x_clk.
Added the x_set_rate and x_round_rate functions. A lower
x_clk rate will be used for the lowest power 24Mhz state.
This implementation to be added later into cpufreq but
going ahead and providing the necessary clock driver
functionality now.
- add enable/disable functionality to ref clocks
Assigned the enable and disable function pointers
of each of the *_ref_clk tables to the mx23 enable
and disable functions.
- change lcd clock (default) parent to ref_pix
Self explanatory. Previously this was incorrectly
assigned directly to the PLL which would cause
ref_pix clock to never be gated when not being
used which causes very small but unnecessary
additional power usage to occur when the LCD is disabled.
- add hbus autoslow function to be used by cpufreq
Added this function for eventual used by cpufreq driver.
- fix pll_enable() delay
This delay was changed to match delay requirements given
in the mx23 reference manual from the definition of the
PLLCTRL0 POWER bitfield.
- revise emi_set_rate
emi_set_rate had several small issues.
The amount of iram it was asking for was set to an
arbitrary amount instead of being assigned to the
size of the assembly code. Instead, assigning it
to the size of the assembly code.
When no changes in emiclk speed were being made, we didn't
need to spend the time allocating iram, disabling fiqs/irqs,
and jumping to the assembly routines Added checks to
minimize the time spent in emi_set_rate if then new
clock divisors were the same as the old.
Added functionality for switching the parent between
ref_emi_clk and ref_xtal_clk source based on the clock
speed.
- added "set_sys_dependent_parent" functionality to allow
the reduction some of the peripheral clocks (mainly SSP
and GPMI) during the lowest power 24MHz cpu_clk state
was needed to allow the PLL to turn off and achieve
minimum power usage for that state. The
"set_sys_dependent_parent" functionality implements this
functionality by checking the cpu speed and changing the
parent as needed (but only when the ref count is zero).
- other minor cleanup
In a couple of locations, I saw the following syntax being used:
> -val &= ~(BM_CLKCTRL_FRAC_CPUFRAC << BP_CLKCTRL_FRAC_CPUFRAC);
> -val |= clkctrl_frac;
This was incorrect because the BM_ definition is already
shifted to the correct bitfield location of the register.
Shifting it over further by BP_ is a bug. This bug
didn't cause problems in these cases because the BP_
value happended to be zero, but needed cleaning up anyway.
The mx23_raw_enable was being called without any delays
to ensure the clock was ready for use. Added a call
to check the clock busy bit to ensure the clock is ready
before being used.
- Added clock_busy_wait function which replaced all the
individual busy_wait handling and properly accounts for
clocks with xtal source (which use a separate xtal
sourced busy bit).
- Cleaned up xtal and rtc clocks/sources functionality.
- Added functionality to SSP and GPMI set_rate function
to allow changing the parent clock to the xtal if the
rate is a factor of 24MHz.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
MX28 has two MAC,but External PHY can only be configed by MAC0
which means PHY1 should be configed by MAC0 according to IC spec.
This patch enable dual ENET support. If want to test rootfs from
eth1, can add ip=:::::eth1:dhcp in the command line
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Rob Herring <r.herring@freescale.com>
netdev/fec.c: add phylib supporting to enable carrier detection
BugLink: http://bugs.launchpad.net/bugs/457878
- removed old MII phy control code
- add phylib supporting
- add ethtool interface to make user space NetworkManager works
This patch is ready for upstream, it will be pushed to upstream for merge
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Acked-by: Amit Kucheria <amit.kucheria@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
Deleted the old drivers.
Broke the driver into separate files, for readability and to isolate
hardware dependencies.
Fixed bad block problems in the boot area for the i.MX23.
At this writing, UBI can't handle MTDs larger than 2GiB. If the
general use partition is larger than 2GiB, the driver will create
sub-partitions, none of which are larger than 2GiB.
Updated the default configs for the i.MX23 and i.MX28.
Other, miscellaneous changes.
Signed-off-by: Patrick Turley <patrick.turley@freescale.com>
IDMAC's EBA/UBO/VBO/ILO are 8-byte aligned.
This patch will check the values for EBA/UBO/VBO/ILO 8-byte aligned.
If not, the driver will give out warning information.
Signed-off-by: Liu Ying <b17645@freescale.com>
The max packet length bit mask used for isochronous endpoints should
be 0x7FF instead of 0x8FF. 0x8FF will actually clear higher-order bits
in the max packet length field.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Set correct stride for non-interleave fmt, if not, will cause v4l output
play uncorrectly for ic_bypass mode.
Signed-off-by: Jason Chen <b02280@freescale.com>
