mirror of
https://github.com/genesi/linux-legacy.git
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1dc8f0e201
1 correct the pata platform device resource check codes 2 Change the end statment of the sdhc1 det pin iomux definition on mx51 board from ',' to ';'. 3 sdhc driver max blk count on MX31, sinc customer report that the emmc would be failed when the blk count is more than 32. Signed-off-by: Richard Zhu <r65037@freescale.com>
1332 lines
28 KiB
C
1332 lines
28 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/input.h>
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#include <linux/nodemask.h>
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <linux/ata.h>
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#include <linux/pmic_external.h>
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#include <linux/mfd/mc9s08dz60/pmic.h>
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#include <linux/regulator/consumer.h>
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#include <linux/smsc911x.h>
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#include <linux/i2c/tsc2007.h>
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#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#include <asm/mach/flash.h>
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#endif
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/common.h>
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#include <mach/memory.h>
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#include <mach/gpio.h>
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#include <mach/mmc.h>
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#include "board-mx35_3stack.h"
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#include "crm_regs.h"
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#include "iomux.h"
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/*!
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* @file mach-mx35/mx35_3stack.c
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*
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* @brief This file contains the board specific initialization routines.
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*
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* @ingroup MSL_MX35
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*/
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unsigned int mx35_3stack_board_io;
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static void mxc_nop_release(struct device *dev)
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{
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/* Nothing */
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}
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/* MTD NOR flash */
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#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE)
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static struct mtd_partition mxc_nor_partitions[] = {
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{
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.name = "Bootloader",
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.size = 512 * 1024,
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.offset = 0x00000000,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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{
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.name = "nor.Kernel",
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.size = 4 * 1024 * 1024,
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = 0},
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{
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.name = "nor.userfs",
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.size = 30 * 1024 * 1024,
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = 0},
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{
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.name = "nor.rootfs",
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.size = 28 * 1024 * 1024,
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = MTD_WRITEABLE},
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{
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.name = "FIS directory",
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.size = 12 * 1024,
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.offset = 0x01FE0000,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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{
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.name = "Redboot config",
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.size = MTDPART_SIZ_FULL,
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.offset = 0x01FFF000,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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};
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static struct flash_platform_data mxc_flash_data = {
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.map_name = "cfi_probe",
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.width = 2,
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.parts = mxc_nor_partitions,
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.nr_parts = ARRAY_SIZE(mxc_nor_partitions),
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};
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static struct resource mxc_flash_resource = {
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.start = 0xa0000000,
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.end = 0xa0000000 + 0x04000000 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device mxc_nor_mtd_device = {
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.name = "mxc_nor_flash",
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.id = 0,
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.dev = {
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.release = mxc_nop_release,
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.platform_data = &mxc_flash_data,
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},
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.num_resources = 1,
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.resource = &mxc_flash_resource,
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};
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static void mxc_init_nor_mtd(void)
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{
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(void)platform_device_register(&mxc_nor_mtd_device);
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}
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#else
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static void mxc_init_nor_mtd(void)
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{
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}
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#endif
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/* MTD NAND flash */
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#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) \
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|| defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE)
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static struct mtd_partition mxc_nand_partitions[] = {
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{
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.name = "nand.bootloader",
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.offset = 0,
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.size = 3 * 1024 * 1024},
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{
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.name = "nand.kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = 5 * 1024 * 1024},
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{
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.name = "nand.rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = 256 * 1024 * 1024},
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{
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.name = "nand.configure",
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.offset = MTDPART_OFS_APPEND,
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.size = 8 * 1024 * 1024},
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{
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.name = "nand.userfs",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL},
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};
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static struct resource mxc_nand_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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.name = "NFC_AXI_BASE",
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.start = NFC_BASE_ADDR,
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.end = NFC_BASE_ADDR + SZ_8K - 1,
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},
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{
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.flags = IORESOURCE_IRQ,
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.start = MXC_INT_NANDFC,
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.end = MXC_INT_NANDFC,
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},
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};
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static struct flash_platform_data mxc_nand_data = {
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.parts = mxc_nand_partitions,
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.nr_parts = ARRAY_SIZE(mxc_nand_partitions),
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.width = 1,
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};
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static struct platform_device mxc_nand_mtd_device = {
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.name = "mxc_nandv2_flash",
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.id = 0,
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.dev = {
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.release = mxc_nop_release,
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.platform_data = &mxc_nand_data,
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},
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.resource = mxc_nand_resources,
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.num_resources = ARRAY_SIZE(mxc_nand_resources),
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};
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static void mxc_init_nand_mtd(void)
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{
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if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B)
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mxc_nand_data.width = 2;
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platform_device_register(&mxc_nand_mtd_device);
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}
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#else
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static inline void mxc_init_nand_mtd(void)
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{
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}
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#endif
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static struct mxc_lcd_platform_data lcd_data = {
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.io_reg = "LCD"
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};
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static struct platform_device lcd_dev = {
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.name = "lcd_claa",
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.id = 0,
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.dev = {
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.release = mxc_nop_release,
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.platform_data = (void *)&lcd_data,
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},
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};
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static void mxc_init_lcd(void)
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{
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platform_device_register(&lcd_dev);
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}
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#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
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/* mxc lcd driver */
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static struct platform_device mxc_fb_device = {
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.name = "mxc_sdc_fb",
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.id = 0,
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.dev = {
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.release = mxc_nop_release,
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.coherent_dma_mask = 0xFFFFFFFF,
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},
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};
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static void mxc_init_fb(void)
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{
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(void)platform_device_register(&mxc_fb_device);
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}
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#else
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static inline void mxc_init_fb(void)
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{
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}
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#endif
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#if defined(CONFIG_BACKLIGHT_MXC)
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static struct platform_device mxcbl_devices[] = {
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#if defined(CONFIG_BACKLIGHT_MXC_IPU) || defined(CONFIG_BACKLIGHT_MXC_IPU_MODULE)
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{
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.name = "mxc_ipu_bl",
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.id = 0,
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.dev = {
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.platform_data = (void *)3, /* DISP # for this backlight */
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},
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}
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#endif
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};
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static inline void mxc_init_bl(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) {
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platform_device_register(&mxcbl_devices[i]);
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}
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}
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#else
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static inline void mxc_init_bl(void)
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{
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}
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#endif
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#if defined(CONFIG_MXC_MLB) || defined(CONFIG_MXC_MLB_MODULE)
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static struct resource mlb_resource[] = {
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[0] = {
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.start = MLB_BASE_ADDR,
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.end = MLB_BASE_ADDR + 0x300,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = MXC_INT_MLB,
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.end = MXC_INT_MLB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mxc_mlb_platform_data mlb_data = {
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.reg_nvcc = "VVIDEO",
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.mlb_clk = "mlb_clk",
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};
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static struct platform_device mlb_dev = {
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.name = "mxc_mlb",
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.id = 0,
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.dev = {
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.platform_data = &mlb_data,
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},
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.num_resources = ARRAY_SIZE(mlb_resource),
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.resource = mlb_resource,
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};
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static inline void mxc_init_mlb(void)
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{
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platform_device_register(&mlb_dev);
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}
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#else
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static inline void mxc_init_mlb(void)
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{
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}
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#endif
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static void mxc_unifi_hardreset(int pin_level)
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{
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pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 1, pin_level & 0x01);
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}
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static void mxc_unifi_enable(int en)
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{
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if (en) {
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pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1);
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msleep(10);
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} else
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pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0);
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}
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static struct mxc_unifi_platform_data unifi_data = {
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.hardreset = mxc_unifi_hardreset,
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.enable = mxc_unifi_enable,
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.reg_gpo1 = "GPO2",
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.reg_gpo2 = "GPO3",
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.reg_1v5_ana_bb = "PWGT1",
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.reg_vdd_vpa = "VAUDIO",
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.reg_1v5_dd = "SW1",
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.host_id = 1,
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};
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struct mxc_unifi_platform_data *get_unifi_plat_data(void)
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{
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return &unifi_data;
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}
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EXPORT_SYMBOL(get_unifi_plat_data);
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static int tsc2007_get_pendown_state(void)
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{
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return !gpio_get_value(IOMUX_TO_GPIO(MX35_PIN_CAPTURE));
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}
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static int tsc2007_init(void)
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{
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return 0;
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}
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static void tsc2007_exit(void)
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{
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}
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struct tsc2007_platform_data tsc2007_data = {
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.model = 2007,
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.x_plate_ohms = 400,
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.get_pendown_state = tsc2007_get_pendown_state,
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.init_platform_hw = tsc2007_init,
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.exit_platform_hw = tsc2007_exit,
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};
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static struct mxc_camera_platform_data camera_data = {
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.core_regulator = "SW1",
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.io_regulator = "VAUDIO",
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.analog_regulator = NULL,
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.gpo_regulator = "PWGT1",
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.mclk = 27000000,
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};
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void si4702_reset(void)
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{
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pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 4, 0);
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msleep(100);
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pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 4, 1);
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msleep(100);
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}
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void si4702_clock_ctl(int flag)
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{
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pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 7, flag);
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}
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static void si4702_gpio_get(void)
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{
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}
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static void si4702_gpio_put(void)
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{
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}
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static struct mxc_fm_platform_data si4702_data = {
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.reg_vio = "VSD",
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.reg_vdd = NULL,
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.gpio_get = si4702_gpio_get,
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.gpio_put = si4702_gpio_put,
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.reset = si4702_reset,
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.clock_ctl = si4702_clock_ctl,
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.sksnr = 0,
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.skcnt = 0,
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.band = 0,
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.space = 100,
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.seekth = 0xa,
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};
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static void adv7180_pwdn(int pwdn)
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{
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pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 1, ~pwdn);
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}
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static void adv7180_reset(void)
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{
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pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 6, 0);
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msleep(5);
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pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 6, 1);
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msleep(5);
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}
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static struct mxc_tvin_platform_data adv7180_data = {
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.dvddio_reg = NULL,
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.dvdd_reg = "SW3",
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.avdd_reg = "PWGT2",
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.pvdd_reg = NULL,
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.pwdn = adv7180_pwdn,
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.reset = adv7180_reset,
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};
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static struct i2c_board_info mxc_i2c_board_info[] __initdata = {
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{
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.type = "max8660",
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.addr = 0x34,
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},
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{
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.type = "tsc2007",
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.addr = 0x48,
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.platform_data = &tsc2007_data,
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.irq = IOMUX_TO_IRQ(MX35_PIN_CAPTURE),
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},
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{
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.type = "ov2640",
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.addr = 0x30,
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.platform_data = (void *)&camera_data,
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},
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{
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.type = "sgtl5000-i2c",
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.addr = 0x0a,
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},
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{
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.type = "ak4647-i2c",
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.addr = 0x12,
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},
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#if defined(CONFIG_I2C_SLAVE_CLIENT)
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{
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.type = "i2c-slave-client",
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.addr = 0x55,
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},
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#endif
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{
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.type = "si4702",
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.addr = 0x10,
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.platform_data = (void *)&si4702_data,
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},
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{
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.type = "adv7180",
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.addr = 0x21,
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.platform_data = (void *)&adv7180_data,
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},
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};
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static struct spi_board_info mxc_spi_board_info[] __initdata = {
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{
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.modalias = "wm8580_spi",
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.max_speed_hz = 8000000, /* max spi SCK clock speed in HZ */
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.bus_num = 1,
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.chip_select = 1,
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},
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};
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#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
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static struct resource smsc911x_resources[] = {
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{
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.start = LAN9217_BASE_ADDR,
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.end = LAN9217_BASE_ADDR + 0x100,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = LAN9217_IRQ,
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.end = LAN9217_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct smsc911x_platform_config smsc911x_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
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};
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static struct platform_device smsc_lan9217_device = {
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.name = "smsc911x",
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.id = 0,
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.dev = {
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.release = mxc_nop_release,
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.platform_data = &smsc911x_config,
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},
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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|
};
|
|
|
|
static void mxc_init_enet(void)
|
|
{
|
|
platform_device_register(&smsc_lan9217_device);
|
|
}
|
|
#else
|
|
static inline void mxc_init_enet(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
|
|
extern void gpio_fec_active(void);
|
|
extern void gpio_fec_inactive(void);
|
|
static int fec_enable(void);
|
|
static int fec_disable(void);
|
|
static struct resource mxc_fec_resources[] = {
|
|
{
|
|
.start = MXC_FEC_BASE_ADDR,
|
|
.end = MXC_FEC_BASE_ADDR + 0xfff,
|
|
.flags = IORESOURCE_MEM
|
|
}, {
|
|
.start = MXC_INT_FEC,
|
|
.end = MXC_INT_FEC,
|
|
.flags = IORESOURCE_IRQ
|
|
},
|
|
};
|
|
|
|
static struct fec_platform_data mxc_fec_data = {
|
|
.init = fec_enable,
|
|
.uninit = fec_disable,
|
|
};
|
|
|
|
struct platform_device mxc_fec_device = {
|
|
.name = "fec",
|
|
.id = 0,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &mxc_fec_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(mxc_fec_resources),
|
|
.resource = mxc_fec_resources,
|
|
};
|
|
|
|
static int fec_enable(void)
|
|
{
|
|
mxc_fec_data.vddio_reg = regulator_get(&mxc_fec_device.dev, "VGEN1");
|
|
|
|
if (IS_ERR(mxc_fec_data.vddio_reg))
|
|
return -EINVAL;
|
|
regulator_enable(mxc_fec_data.vddio_reg);
|
|
gpio_fec_active();
|
|
return 0;
|
|
}
|
|
|
|
static int fec_disable(void)
|
|
{
|
|
if (IS_ERR(mxc_fec_data.vddio_reg))
|
|
return -EINVAL;
|
|
|
|
gpio_fec_inactive();
|
|
regulator_disable(mxc_fec_data.vddio_reg);
|
|
regulator_put(mxc_fec_data.vddio_reg);
|
|
return 0;
|
|
}
|
|
|
|
static __init int mxc_init_fec(void)
|
|
{
|
|
return platform_device_register(&mxc_fec_device);
|
|
}
|
|
#else
|
|
static inline int mxc_init_fec(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
|
|
static struct mxc_mmc_platform_data mmc1_data = {
|
|
.ocr_mask = MMC_VDD_32_33,
|
|
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
|
|
.caps = MMC_CAP_4_BIT_DATA,
|
|
#else
|
|
.caps = MMC_CAP_8_BIT_DATA,
|
|
#endif
|
|
.min_clk = 150000,
|
|
.max_clk = 52000000,
|
|
.card_inserted_state = 0,
|
|
.status = sdhc_get_card_det_status,
|
|
.wp_status = sdhc_write_protect,
|
|
.clock_mmc = "sdhc_clk",
|
|
};
|
|
|
|
/*!
|
|
* Resource definition for the SDHC1
|
|
*/
|
|
static struct resource mxcsdhc1_resources[] = {
|
|
[0] = {
|
|
.start = MMC_SDHC1_BASE_ADDR,
|
|
.end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = MX35_INT_MMC_SDHC1,
|
|
.end = MX35_INT_MMC_SDHC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
[2] = {
|
|
.start = MXC_PSEUDO_IRQ_SD1_CD,
|
|
.end = MXC_PSEUDO_IRQ_SD1_CD,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
/*! Device Definition for MXC SDHC1 */
|
|
static struct platform_device mxcsdhc1_device = {
|
|
.name = "mxsdhci",
|
|
.id = 0,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &mmc1_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
|
|
.resource = mxcsdhc1_resources,
|
|
};
|
|
|
|
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
|
|
static struct mxc_mmc_platform_data mmc2_data = {
|
|
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
|
|
MMC_VDD_31_32,
|
|
.caps = MMC_CAP_4_BIT_DATA,
|
|
.min_clk = 150000,
|
|
.max_clk = 50000000,
|
|
.card_inserted_state = 0,
|
|
.status = sdhc_get_card_det_status,
|
|
.wp_status = sdhc_write_protect,
|
|
.clock_mmc = "sdhc_clk",
|
|
};
|
|
|
|
static struct resource mxcsdhc2_resources[] = {
|
|
[0] = {
|
|
.start = MMC_SDHC2_BASE_ADDR,
|
|
.end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = MXC_INT_MMC_SDHC2,
|
|
.end = MXC_INT_MMC_SDHC2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
[2] = {
|
|
.start = 0,
|
|
.end = 0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mxcsdhc2_device = {
|
|
.name = "mxsdhci",
|
|
.id = 1,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &mmc2_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(mxcsdhc2_resources),
|
|
.resource = mxcsdhc2_resources,
|
|
};
|
|
#endif
|
|
|
|
static inline void mxc_init_mmc(void)
|
|
{
|
|
(void)platform_device_register(&mxcsdhc1_device);
|
|
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
|
|
(void)platform_device_register(&mxcsdhc2_device);
|
|
#endif
|
|
}
|
|
#else
|
|
static inline void mxc_init_mmc(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MXC_PSEUDO_IRQS
|
|
/*! Device Definition for MXC SDHC1 */
|
|
static struct platform_device mxc_pseudo_irq_device = {
|
|
.name = "mxc_pseudo_irq",
|
|
.id = 0,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
},
|
|
};
|
|
|
|
static inline int mxc_init_pseudo_irq(void)
|
|
{
|
|
return platform_device_register(&mxc_pseudo_irq_device);
|
|
}
|
|
|
|
late_initcall(mxc_init_pseudo_irq);
|
|
|
|
/*!
|
|
* Power Key interrupt handler.
|
|
*/
|
|
static irqreturn_t power_key_int(int irq, void *dev_id)
|
|
{
|
|
pr_info(KERN_INFO "on-off key pressed\n");
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
* Power Key initialization.
|
|
*/
|
|
static int __init mxc_init_power_key(void)
|
|
{
|
|
if (!board_is_rev(BOARD_REV_2)) {
|
|
/*Set power key as wakeup resource */
|
|
int irq, ret;
|
|
irq = MXC_PSEUDO_IRQ_POWER_KEY;
|
|
set_irq_type(irq, IRQF_TRIGGER_RISING);
|
|
ret = request_irq(irq, power_key_int, 0, "power_key", 0);
|
|
if (ret)
|
|
pr_info("register on-off key interrupt failed\n");
|
|
else
|
|
enable_irq_wake(irq);
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(mxc_init_power_key);
|
|
#endif
|
|
|
|
#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
|
|
extern void gpio_ata_active(void);
|
|
extern void gpio_ata_inactive(void);
|
|
|
|
static int ata_init(struct platform_device *pdev)
|
|
{
|
|
/* Configure the pins */
|
|
gpio_ata_active();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ata_exit(void)
|
|
{
|
|
/* Free the pins */
|
|
gpio_ata_inactive();
|
|
}
|
|
|
|
static struct fsl_ata_platform_data ata_data = {
|
|
.adma_flag = 1, /* 0:smart dma, 1:ADMA */
|
|
.udma_mask = 0x3F,
|
|
.mwdma_mask = 0x1F,
|
|
.pio_mask = ATA_PIO4,
|
|
.fifo_alarm = MXC_IDE_DMA_WATERMARK / 2,
|
|
.max_sg = MXC_IDE_DMA_BD_NR,
|
|
.init = ata_init,
|
|
.exit = ata_exit,
|
|
.core_reg = NULL, /*"LDO2", */
|
|
.io_reg = NULL, /*"LDO3", */
|
|
};
|
|
|
|
static struct resource pata_fsl_resources[] = {
|
|
{
|
|
.start = ATA_BASE_ADDR,
|
|
.end = ATA_BASE_ADDR + 0x000000C8,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = MXC_INT_ATA,
|
|
.end = MXC_INT_ATA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device pata_fsl_device = {
|
|
.name = "pata_fsl",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(pata_fsl_resources),
|
|
.resource = pata_fsl_resources,
|
|
.dev = {
|
|
.platform_data = &ata_data,
|
|
.coherent_dma_mask = ~0,
|
|
},
|
|
};
|
|
|
|
static void __init mxc_init_pata(void)
|
|
{
|
|
(void)platform_device_register(&pata_fsl_device);
|
|
}
|
|
#else /* CONFIG_PATA_FSL */
|
|
static void __init mxc_init_pata(void)
|
|
{
|
|
}
|
|
#endif /* CONFIG_PATA_FSL */
|
|
|
|
#if defined(CONFIG_GPS_IOCTRL) || defined(CONFIG_GPS_IOCTRL_MODULE)
|
|
static struct mxc_gps_platform_data gps_data = {
|
|
.core_reg = "SW3",
|
|
.analog_reg = "PWGT2",
|
|
};
|
|
|
|
static struct platform_device mxc_gps_device = {
|
|
.name = "gps_ioctrl",
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &gps_data,
|
|
},
|
|
};
|
|
|
|
static void __init mxc_init_gps(void)
|
|
{
|
|
(void)platform_device_register(&mxc_gps_device);
|
|
}
|
|
#else
|
|
static void __init mxc_init_gps(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/*!
|
|
* Board specific fixup function. It is called by \b setup_arch() in
|
|
* setup.c file very early on during kernel starts. It allows the user to
|
|
* statically fill in the proper values for the passed-in parameters. None of
|
|
* the parameters is used currently.
|
|
*
|
|
* @param desc pointer to \b struct \b machine_desc
|
|
* @param tags pointer to \b struct \b tag
|
|
* @param cmdline pointer to the command line
|
|
* @param mi pointer to \b struct \b meminfo
|
|
*/
|
|
static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
|
|
char **cmdline, struct meminfo *mi)
|
|
{
|
|
mxc_cpu_init();
|
|
|
|
#ifdef CONFIG_DISCONTIGMEM
|
|
do {
|
|
int nid;
|
|
mi->nr_banks = MXC_NUMNODES;
|
|
for (nid = 0; nid < mi->nr_banks; nid++)
|
|
SET_NODE(mi, nid);
|
|
} while (0);
|
|
#endif
|
|
}
|
|
|
|
static void bt_reset(void)
|
|
{
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 2, 0);
|
|
msleep(5);
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 2, 1);
|
|
}
|
|
|
|
static struct mxc_bt_platform_data mxc_bt_data = {
|
|
.bt_vdd = "GPO2",
|
|
.bt_vdd_parent = NULL,
|
|
.bt_vusb = NULL,
|
|
.bt_vusb_parent = NULL,
|
|
.bt_reset = bt_reset,
|
|
};
|
|
|
|
static struct platform_device mxc_bt_device = {
|
|
.name = "mxc_bt",
|
|
.id = 0,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &mxc_bt_data,
|
|
},
|
|
};
|
|
|
|
static void mxc_init_bluetooth(void)
|
|
{
|
|
(void)platform_device_register(&mxc_bt_device);
|
|
}
|
|
|
|
#if defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) \
|
|
|| defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000_MODULE)
|
|
|
|
static int sgtl5000_headphone_det_status(void)
|
|
{
|
|
int ret = 0;
|
|
if (0 != pmic_gpio_get_designation_bit_val(0, &ret))
|
|
printk(KERN_ERR "Get headphone status error.");
|
|
return ret;
|
|
}
|
|
|
|
static int mxc_sgtl5000_plat_init(void);
|
|
static int mxc_sgtl5000_plat_finit(void);
|
|
static int mxc_sgtl5000_amp_enable(int enable);
|
|
|
|
static struct mxc_audio_platform_data sgtl5000_data = {
|
|
.ssi_num = 1,
|
|
.src_port = 1,
|
|
.ext_port = 4,
|
|
.hp_irq = MXC_PSEUDO_IRQ_HEADPHONE,
|
|
.hp_status = sgtl5000_headphone_det_status,
|
|
.amp_enable = mxc_sgtl5000_amp_enable,
|
|
.sysclk = 12000000,
|
|
.init = mxc_sgtl5000_plat_init,
|
|
.finit = mxc_sgtl5000_plat_finit,
|
|
};
|
|
|
|
static struct platform_device mxc_sgtl5000_device = {
|
|
.name = "imx-3stack-sgtl5000",
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &sgtl5000_data,
|
|
},
|
|
};
|
|
|
|
static int mxc_sgtl5000_plat_init(void)
|
|
{
|
|
struct regulator *reg;
|
|
reg = regulator_get(&mxc_sgtl5000_device.dev, "SPKR");
|
|
if (IS_ERR(reg))
|
|
return -EINVAL;
|
|
sgtl5000_data.priv = reg;
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_sgtl5000_plat_finit(void)
|
|
{
|
|
struct regulator *reg;
|
|
reg = sgtl5000_data.priv;
|
|
if (reg) {
|
|
regulator_put(reg);
|
|
sgtl5000_data.priv = NULL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_sgtl5000_amp_enable(int enable)
|
|
{
|
|
struct regulator *reg;
|
|
reg = sgtl5000_data.priv;
|
|
|
|
if (!reg)
|
|
return -EINVAL;
|
|
if (enable)
|
|
regulator_enable(reg);
|
|
else
|
|
regulator_disable(reg);
|
|
return 0;
|
|
}
|
|
|
|
static void mxc_init_sgtl5000(void)
|
|
{
|
|
struct clk *cko1, *parent;
|
|
unsigned long rate;
|
|
|
|
/* for board v1.1 do nothing */
|
|
if (!board_is_rev(BOARD_REV_2))
|
|
return;
|
|
|
|
cko1 = clk_get(NULL, "cko1_clk");
|
|
if (IS_ERR(cko1))
|
|
return;
|
|
parent = clk_get(NULL, "ckih");
|
|
if (IS_ERR(parent))
|
|
return;
|
|
clk_set_parent(cko1, parent);
|
|
rate = clk_round_rate(cko1, 12000000);
|
|
if (rate < 8000000 || rate > 27000000) {
|
|
printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n",
|
|
(unsigned int)rate);
|
|
clk_put(parent);
|
|
clk_put(cko1);
|
|
return;
|
|
}
|
|
clk_set_rate(cko1, rate);
|
|
clk_enable(cko1);
|
|
sgtl5000_data.sysclk = rate;
|
|
platform_device_register(&mxc_sgtl5000_device);
|
|
}
|
|
#else
|
|
static void mxc_init_sgtl5000(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SND_SOC_IMX_3STACK_AK4647) \
|
|
|| defined(CONFIG_SND_SOC_IMX_3STACK_AK4647_MODULE)
|
|
static int mxc_ak4647_amp_enable(int enable)
|
|
{
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, enable);
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_ak4647_plat_init(void)
|
|
{
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 1, 0);
|
|
msleep(1);
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 1, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int ak4647_headphone_det_status(void)
|
|
{
|
|
int ret = 0;
|
|
if (0 != pmic_gpio_get_designation_bit_val(0, &ret))
|
|
printk(KERN_ERR "Get headphone status error.");
|
|
return ret;
|
|
}
|
|
|
|
static struct mxc_audio_platform_data mxc_ak4647_data = {
|
|
.ssi_num = 1,
|
|
.src_port = 1,
|
|
.ext_port = 4,
|
|
.amp_enable = mxc_ak4647_amp_enable,
|
|
.init = mxc_ak4647_plat_init,
|
|
.hp_status = ak4647_headphone_det_status,
|
|
.intr_id_hp = MXC_PSEUDO_IRQ_HEADPHONE,
|
|
};
|
|
|
|
static struct platform_device mxc_alsa_device = {
|
|
.name = "imx-3stack-ak4647",
|
|
.id = 0,
|
|
.dev = {
|
|
.release = mxc_nop_release,
|
|
.platform_data = &mxc_ak4647_data,
|
|
},
|
|
|
|
};
|
|
|
|
static void mxc_init_ak4647(void)
|
|
{
|
|
platform_device_register(&mxc_alsa_device);
|
|
}
|
|
#else
|
|
static void mxc_init_ak4647(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
|
|
static void flexcan_xcvr_enable(int id, int en)
|
|
{
|
|
static int pwdn;
|
|
|
|
if (id < 0 || id > 1)
|
|
return;
|
|
|
|
if (en) {
|
|
if (!(pwdn++))
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2,
|
|
1, 0);
|
|
} else {
|
|
if (!(--pwdn))
|
|
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2,
|
|
1, 1);
|
|
}
|
|
}
|
|
|
|
struct flexcan_platform_data flexcan_data[] = {
|
|
{
|
|
.core_reg = "GPO2",
|
|
.io_reg = NULL,
|
|
.xcvr_enable = flexcan_xcvr_enable,
|
|
.active = gpio_can_active,
|
|
.inactive = gpio_can_inactive,
|
|
.br_clksrc = 1,
|
|
.br_rjw = 2,
|
|
.br_presdiv = 6,
|
|
.br_propseg = 4,
|
|
.br_pseg1 = 4,
|
|
.br_pseg2 = 7,
|
|
.bcc = 1,
|
|
.srx_dis = 1,
|
|
.smp = 1,
|
|
.boff_rec = 1,
|
|
.ext_msg = 1,
|
|
.std_msg = 1,},
|
|
{
|
|
.core_reg = "GPO2",
|
|
.io_reg = NULL,
|
|
.xcvr_enable = flexcan_xcvr_enable,
|
|
.active = gpio_can_active,
|
|
.inactive = gpio_can_inactive,
|
|
.br_clksrc = 1,
|
|
.br_rjw = 2,
|
|
.br_presdiv = 6,
|
|
.br_propseg = 4,
|
|
.br_pseg1 = 4,
|
|
.br_pseg2 = 7,
|
|
.bcc = 1,
|
|
.srx_dis = 1,
|
|
.smp = 1,
|
|
.boff_rec = 1,
|
|
.ext_msg = 1,
|
|
.std_msg = 1,},
|
|
};
|
|
#endif
|
|
|
|
/*!
|
|
* fixup for mx35 3stack board v1.0 (MAX8660)
|
|
*/
|
|
static void mx35_3stack_fixup_for_board_v1(void)
|
|
{
|
|
#if defined(CONFIG_MXC_MLB) || defined(CONFIG_MXC_MLB_MODULE)
|
|
mlb_data.reg_nvcc = "LDO6";
|
|
#endif
|
|
|
|
#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE)
|
|
unifi_data.reg_gpo1 = NULL;
|
|
unifi_data.reg_gpo2 = NULL;
|
|
unifi_data.reg_1v5_ana_bb = "SW4";
|
|
unifi_data.reg_vdd_vpa = "SW1";
|
|
unifi_data.reg_1v5_dd = "SW4";
|
|
#endif
|
|
camera_data.analog_regulator = "LDO7";
|
|
camera_data.core_regulator = NULL;
|
|
camera_data.io_regulator = NULL;
|
|
camera_data.gpo_regulator = NULL;
|
|
camera_data.mclk = 20000000;
|
|
|
|
adv7180_data.dvddio_reg = NULL;
|
|
adv7180_data.dvdd_reg = NULL;
|
|
adv7180_data.avdd_reg = NULL;
|
|
adv7180_data.pvdd_reg = NULL;
|
|
|
|
si4702_data.reg_vio = "SW1";
|
|
si4702_data.reg_vdd = NULL;
|
|
|
|
#if defined(CONFIG_GPS_IOCTRL) || defined(CONFIG_GPS_IOCTRL_MODULE)
|
|
gps_data.core_reg = "SW1";
|
|
gps_data.analog_reg = "SW2";
|
|
#endif
|
|
|
|
mxc_bt_data.bt_vdd = "SW1";
|
|
|
|
#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
|
|
flexcan_data[0].core_reg = "SW1";
|
|
flexcan_data[1].core_reg = "SW1";
|
|
#endif
|
|
}
|
|
|
|
/*!
|
|
* Board specific initialization.
|
|
*/
|
|
static void __init mxc_board_init(void)
|
|
{
|
|
mxc_cpu_common_init();
|
|
|
|
mxc_register_gpios();
|
|
mxc_init_devices();
|
|
if (!board_is_rev(BOARD_REV_2))
|
|
mx35_3stack_fixup_for_board_v1();
|
|
mx35_3stack_gpio_init();
|
|
mxc_init_enet();
|
|
mxc_init_nor_mtd();
|
|
mxc_init_nand_mtd();
|
|
|
|
mx35_3stack_init_mc13892();
|
|
mx35_3stack_init_mc9s08dz60();
|
|
mxc_init_lcd();
|
|
mxc_init_fb();
|
|
mxc_init_bl();
|
|
mxc_init_sgtl5000();
|
|
mxc_init_ak4647();
|
|
|
|
i2c_register_board_info(0, mxc_i2c_board_info,
|
|
ARRAY_SIZE(mxc_i2c_board_info));
|
|
|
|
spi_register_board_info(mxc_spi_board_info,
|
|
ARRAY_SIZE(mxc_spi_board_info));
|
|
mxc_init_mmc();
|
|
mxc_init_pata();
|
|
mxc_init_bluetooth();
|
|
mxc_init_gps();
|
|
mxc_init_mlb();
|
|
mxc_init_fec();
|
|
}
|
|
|
|
#define PLL_PCTL_REG(brmo, pd, mfd, mfi, mfn) \
|
|
(((brmo) << 31) + (((pd) - 1) << 26) + (((mfd) - 1) << 16) + \
|
|
((mfi) << 10) + mfn)
|
|
|
|
/* For 24MHz input clock */
|
|
#define PLL_665MHZ PLL_PCTL_REG(1, 1, 48, 13, 41)
|
|
#define PLL_532MHZ PLL_PCTL_REG(1, 1, 12, 11, 1)
|
|
#define PLL_399MHZ PLL_PCTL_REG(0, 1, 16, 8, 5)
|
|
|
|
/* working point(wp): 0,1 - 133MHz; 2,3 - 266MHz; 4,5 - 399MHz;*/
|
|
/* auto input clock table */
|
|
static struct cpu_wp cpu_wp_auto[] = {
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 133000000,
|
|
.pdr0_reg = (0x2 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 133000000,
|
|
.pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 266000000,
|
|
.pdr0_reg = (0x1 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 266000000,
|
|
.pdr0_reg = (0x5 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 399000000,
|
|
.pdr0_reg = (0x0 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_399MHZ,
|
|
.pll_rate = 399000000,
|
|
.cpu_rate = 399000000,
|
|
.pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),},
|
|
};
|
|
|
|
/* consumer input clock table */
|
|
static struct cpu_wp cpu_wp_con[] = {
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 133000000,
|
|
.pdr0_reg = (0x6 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 133000000,
|
|
.pdr0_reg = (0xE << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 266000000,
|
|
.pdr0_reg = (0x2 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 266000000,
|
|
.pdr0_reg = (0xA << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 399000000,
|
|
.pdr0_reg = (0x1 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 399000000,
|
|
.pdr0_reg = (0x9 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 532000000,
|
|
.pdr0_reg = (0x0 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_532MHZ,
|
|
.pll_rate = 532000000,
|
|
.cpu_rate = 532000000,
|
|
.pdr0_reg = (0x8 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
{
|
|
.pll_reg = PLL_665MHZ,
|
|
.pll_rate = 665000000,
|
|
.cpu_rate = 665000000,
|
|
.pdr0_reg = (0x7 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),},
|
|
};
|
|
|
|
struct cpu_wp *get_cpu_wp(int *wp)
|
|
{
|
|
if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) {
|
|
*wp = 9;
|
|
return cpu_wp_con;
|
|
} else {
|
|
if (__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON) {
|
|
*wp = 9;
|
|
return cpu_wp_con;
|
|
} else {
|
|
*wp = 6;
|
|
return cpu_wp_auto;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void __init mx35_3stack_timer_init(void)
|
|
{
|
|
struct clk *uart_clk;
|
|
|
|
mx35_clocks_init();
|
|
uart_clk = clk_get(NULL, "uart_clk.0");
|
|
early_console_setup(UART1_BASE_ADDR, uart_clk);
|
|
}
|
|
|
|
static struct sys_timer mxc_timer = {
|
|
.init = mx35_3stack_timer_init,
|
|
};
|
|
|
|
/*
|
|
* The following uses standard kernel macros define in arch.h in order to
|
|
* initialize __mach_desc_MX35_3DS data structure.
|
|
*/
|
|
/* *INDENT-OFF* */
|
|
MACHINE_START(MX35_3DS, "Freescale MX35 3-Stack Board")
|
|
/* Maintainer: Freescale Semiconductor, Inc. */
|
|
.phys_io = AIPS1_BASE_ADDR,
|
|
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
|
|
.boot_params = PHYS_OFFSET + 0x100,
|
|
.fixup = fixup_mxc_board,
|
|
.map_io = mx35_map_io,
|
|
.init_irq = mxc_init_irq,
|
|
.init_machine = mxc_board_init,
|
|
.timer = &mxc_timer,
|
|
MACHINE_END
|