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bd9d5d59ab
* Will now parse the mode list to: - Remove pixel clocks above 133MHz which the MX51 IPU DI cannot display (PLL limitation) - Remove modes from mode list that are interlaced (cannot display) - Find and save the best (native) panel mode and try and match a mode as close as possible instead of arbitrarily trying 1280x720 (unless EDID failed for some reason) * Reduce bus timeout default to 10ms as it always takes less (<4ms or so, but we want to handle slow monitors) * Comment out instrumentation until it returns reasonable values (jiffies aren't accurate enough) * Some variable renames for clearer code