Mike Frysinger fb4b5d3a37 Blackfin: handle BF561 Core B memory regions better when SMP=n ...

Rather than assume Core B is always run with caches turned on, let people
load into any of the on-chip memory regions.  It is their business how the
SRAM/Cache regions are utilized, so don't prevent them from being able to
load into them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2009-07-16 01:52:24 -04:00

13 KiB

Raw Blame History

View Raw