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Timer interrupts can now be cleared, fix palmCrystalCycles being read uninitalized in first call to recalculateCpuSpeed()

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This commit is contained in:
meepingsnesroms
2018-04-29 23:16:14 -07:00
parent 3a43cbad4b
commit 0f4c0a1e25
2 changed files with 18 additions and 11 deletions
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27
src/hardwareRegisters.c
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@@ -704,6 +704,22 @@ void setHwRegister16(unsigned int address, unsigned int value){
case TCTL2:
registerArrayWrite16(address, value & 0x01FF);
break;
case TSTAT1:
//preserve any unread bits
registerArrayWrite16(TSTAT1, (value & timerStatusReadAcknowledge[0]) | (registerArrayRead16(TSTAT1) & ~timerStatusReadAcknowledge[0]));
timerStatusReadAcknowledge[0] = 0x0000;//clear acknowledged reads
if(!(registerArrayRead16(TSTAT1) & 0x0001))
clearIprIsrBit(INT_TMR1);
break;
case TSTAT2:
//preserve any unread bits
registerArrayWrite16(TSTAT2, (value & timerStatusReadAcknowledge[1]) | (registerArrayRead16(TSTAT2) & ~timerStatusReadAcknowledge[1]));
timerStatusReadAcknowledge[1] = 0x0000;//clear acknowledged reads
if(!(registerArrayRead16(TSTAT2) & 0x0001))
clearIprIsrBit(INT_TMR2);
break;
case WATCHDOG:
//writing to the watchdog resets the counter bits(8 and 9) to 0
@@ -825,16 +841,6 @@ void setHwRegister16(unsigned int address, unsigned int value){
setSpiCont2(value);
break;
case TSTAT1:
//preserve any unread bits
registerArrayWrite16(TSTAT1, (value & timerStatusReadAcknowledge[0]) | (registerArrayRead16(TSTAT1) & ~timerStatusReadAcknowledge[0]));
break;
case TSTAT2:
//preserve any unread bits
registerArrayWrite16(TSTAT2, (value & timerStatusReadAcknowledge[1]) | (registerArrayRead16(TSTAT2) & ~timerStatusReadAcknowledge[1]));
break;
case TCMP1:
case TCMP2:
case TPRER1:
@@ -903,6 +909,7 @@ void setHwRegister32(unsigned int address, unsigned int value){
void resetHwRegisters(){
memset(palmReg, 0x00, REG_SIZE - BOOTLOADER_SIZE);
palmCrystalCycles = 0.0;
clk32Counter = 0;
pllWakeWait = -1;
timerCycleCounter[0] = 0.0;

2
unimplementedFeatures.txt
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@@ -9,7 +9,7 @@ RAM wait states
CPU I/O:
Timer capture events, I don't think there possible though with the Palms hardware
Peripheral Control Register, audio ppm mixing selection
Peripheral Control Register, audio ppm mixing selection and timer cascade mode
All edge triggered interrupts(currently always level triggered)
Port G SPI stuff
Setting the battery dead bit(PDDATA 0x80) if the emulated battery percent gets too low