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Code Issues 18 Packages Projects Releases 2 Wiki Activity

Provisional chipselect fix

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meepingsnesroms
2018-07-31 18:39:31 -07:00
parent 7246c7fc8b
commit 2d21e6fa46
8 changed files with 369 additions and 332 deletions
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qtBuildSystem/Mu/Mu.pro.user
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@@ -1,6 +1,6 @@
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2
src/debug/sandbox.c
View File

@@ -135,7 +135,7 @@ static uint32_t scanForPrivateFunctionAddress(const char* name){
//function name format [0x**(unknown), string(with null terminator), 0x00, 0x00(if last 0x00 was on an even address, protects opcode alignemnt)]
//this is not 100% accurate, it scans memory for a function address based on a string
//if a duplicate set of stings is found but not encasing a function a fatal error will occur on execution
uint32_t rangeEnd = chips[CHIP_A_ROM].start + chips[CHIP_A_ROM].size - 1;
uint32_t rangeEnd = chips[CHIP_A_ROM].start + chips[CHIP_A_ROM].lineSize - 1;
uint32_t address = find68kString(name, chips[CHIP_A_ROM].start, rangeEnd);
while(address < rangeEnd){

4
src/emulator.c
View File

@@ -276,7 +276,7 @@ void emulatorSaveState(uint8_t* data){
offset += sizeof(uint8_t);
writeStateValueUint32(data + offset, chips[chip].start);
offset += sizeof(uint32_t);
writeStateValueUint32(data + offset, chips[chip].size);
writeStateValueUint32(data + offset, chips[chip].lineSize);
offset += sizeof(uint32_t);
writeStateValueUint32(data + offset, chips[chip].mask);
offset += sizeof(uint32_t);
@@ -420,7 +420,7 @@ void emulatorLoadState(uint8_t* data){
offset += sizeof(uint8_t);
chips[chip].start = readStateValueUint32(data + offset);
offset += sizeof(uint32_t);
chips[chip].size = readStateValueUint32(data + offset);
chips[chip].lineSize = readStateValueUint32(data + offset);
offset += sizeof(uint32_t);
chips[chip].mask = readStateValueUint32(data + offset);
offset += sizeof(uint32_t);

80
src/hardwareRegisters.c
View File

@@ -790,28 +790,51 @@ void setHwRegister16(uint32_t address, uint16_t value){
registerArrayWrite16(address, value & 0xDC7F);
break;
case CSA:
setCsa(value);
if((value & 0x000F) != (registerArrayRead16(CSA) & 0x000F))
resetAddressSpace();//only reset address space if size changed or enabled/disabled
case CSA:{
uint16_t oldCsa = registerArrayRead16(CSA);
setCsa(value);
//only reset address space if size changed or enabled/disabled
if((value & 0x000F) != (oldCsa & 0x000F))
resetAddressSpace();
}
break;
case CSB:
setCsb(value);
if((value & 0x000F) != (registerArrayRead16(CSB) & 0x000F))
resetAddressSpace();//only reset address space if size changed or enabled/disabled
case CSB:{
uint16_t oldCsb = registerArrayRead16(CSB);
setCsb(value);
//only reset address space if size changed or enabled/disabled
if((value & 0x000F) != (oldCsb & 0x000F))
resetAddressSpace();
}
break;
case CSC:
setCsc(value);
if((value & 0x000F) != (registerArrayRead16(CSC) & 0x000F))
resetAddressSpace();//only reset address space if size changed or enabled/disabled
case CSC:{
uint16_t oldCsc = registerArrayRead16(CSC);
setCsc(value);
//only reset address space if size changed or enabled/disabled
if((value & 0x000F) != (oldCsc & 0x000F))
resetAddressSpace();
}
break;
case CSD:
setCsd(value);
if((value & 0x000F) != (registerArrayRead16(CSD) & 0x000F))
resetAddressSpace();//only reset address space if size changed or enabled/disabled
case CSD:{
uint16_t oldCsd = registerArrayRead16(CSD);
setCsd(value);
if((value & 0x0200) != (oldCsd & 0x0200))
setCsc(registerArrayRead16(CSC));//CSC may rely on CSD DRAM bit, untested
//only reset address space if size changed, enabled/disabled or DRAM bit changed
if((value & 0x020F) != (oldCsd & 0x020F))
resetAddressSpace();
}
break;
case CSGBA:
@@ -859,10 +882,19 @@ void setHwRegister16(uint32_t address, uint16_t value){
}
break;
case CSCTRL1:
if((value & 0x7F55) != registerArrayRead16(CSCTRL1)){
setCsctrl1(value);
resetAddressSpace();
case CSCTRL1:{
uint16_t oldCsctrl1 = registerArrayRead16(CSCTRL1);
registerArrayWrite16(CSCTRL1, value & 0x7F55);
if((value & 0x4055) != (oldCsctrl1 & 0x4055)){
//something important changed, update all chipselects
//CSA is not dependant on CSCTRL1
setCsb(registerArrayRead16(CSB));
setCsc(registerArrayRead16(CSC));
setCsd(registerArrayRead16(CSD));
resetAddressSpace();
}
}
break;
@@ -965,6 +997,14 @@ void resetHwRegisters(){
//all chipselects are disabled at boot and CSA is mapped to 0x00000000 and covers the entire address range until CSGBA set otherwise
chips[CHIP_A_ROM].inBootMode = true;
//default size, prevents divide by 0 crash in access checks
chips[CHIP_A_ROM].lineSize = 0x20000;
chips[CHIP_B_SED].lineSize = 0x20000;
chips[CHIP_C_USB].lineSize = 0x8000;
chips[CHIP_D_RAM].lineSize = 0x8000;
chips[CHIP_REGISTERS].lineSize = 0x10000;
chips[CHIP_NONE].lineSize = 0x1;
//masks for reading and writing
chips[CHIP_A_ROM].mask = 0x003FFFFF;//4mb
chips[CHIP_B_SED].mask = 0x0003FFFF;

2
src/hardwareRegisters.h
View File

@@ -43,7 +43,7 @@ enum{
typedef struct{
bool enable;
uint32_t start;
uint32_t size;
uint32_t lineSize;//the size of a single chip select line, multiply by 2 to get the range size
uint32_t mask;//the address lines the chip responds to, so 0x10000 on an chip with 16 address lines will return the value at 0x0000
//attributes

41
src/hardwareRegistersAccessors.c.h
View File

@@ -35,7 +35,7 @@ static inline void clearIprIsrBit(uint32_t interruptBit){
static inline void setCsa(uint16_t value){
chips[CHIP_A_ROM].enable = value & 0x0001;
chips[CHIP_A_ROM].readOnly = value & 0x8000;
chips[CHIP_A_ROM].size = 0x20000/*128kb*/ << (value >> 1 & 0x0007);
chips[CHIP_A_ROM].lineSize = 0x20000/*128kb*/ << (value >> 1 & 0x0007);
//CSA is now just a normal chipselect
if(chips[CHIP_A_ROM].enable && chips[CHIP_A_ROM].inBootMode)
@@ -49,33 +49,37 @@ static inline void setCsb(uint16_t value){
chips[CHIP_B_SED].enable = value & 0x0001;
chips[CHIP_B_SED].readOnly = value & 0x8000;
chips[CHIP_B_SED].size = 0x20000/*128kb*/ << (value >> 1 & 0x0007);
chips[CHIP_B_SED].lineSize = 0x20000/*128kb*/ << (value >> 1 & 0x0007);
//attributes
chips[CHIP_B_SED].supervisorOnlyProtectedMemory = value & 0x4000;
chips[CHIP_B_SED].readOnlyForProtectedMemory = value & 0x2000;
if(csControl1 & 0x4000 && csControl1 & 0x0001)
chips[CHIP_B_SED].unprotectedSize = 0x8000/*32kb*/ << ((value >> 11 & 0x0003) | 0x0004);
chips[CHIP_B_SED].unprotectedSize = chips[CHIP_B_SED].lineSize / (1 << 7 - ((value >> 11 & 0x0003) | 0x0004));
else
chips[CHIP_B_SED].unprotectedSize = 0x8000/*32kb*/ << (value >> 11 & 0x0003);
chips[CHIP_B_SED].unprotectedSize = chips[CHIP_B_SED].lineSize / (1 << 7 - (value >> 11 & 0x0003));
registerArrayWrite16(CSB, value & 0xF9FF);
}
static inline void setCsc(uint16_t value){
uint16_t csControl1 = registerArrayRead16(CSCTRL1);
bool csdDramBit = registerArrayRead16(CSD) & 0x0200;
chips[CHIP_C_USB].enable = value & 0x0001;
chips[CHIP_C_USB].readOnly = value & 0x8000;
chips[CHIP_C_USB].size = 0x8000/*32kb*/ << (value >> 1 & 0x0007);
if(csControl1 & 0x0040 && csdDramBit)
chips[CHIP_C_USB].lineSize = 0x800000/*8mb*/ << (value >> 1 & 0x0001);
else
chips[CHIP_C_USB].lineSize = 0x8000/*32kb*/ << (value >> 1 & 0x0007);
//attributes
chips[CHIP_C_USB].supervisorOnlyProtectedMemory = value & 0x4000;
chips[CHIP_C_USB].readOnlyForProtectedMemory = value & 0x2000;
if(csControl1 & 0x4000 && csControl1 & 0x0004)
chips[CHIP_C_USB].unprotectedSize = 0x8000/*32kb*/ << ((value >> 11 & 0x0003) | 0x0004);
chips[CHIP_C_USB].unprotectedSize = chips[CHIP_C_USB].lineSize / (1 << 7 - ((value >> 11 & 0x0003) | 0x0004));
else
chips[CHIP_C_USB].unprotectedSize = 0x8000/*32kb*/ << (value >> 11 & 0x0003);
chips[CHIP_C_USB].unprotectedSize = chips[CHIP_C_USB].lineSize / (1 << 7 - (value >> 11 & 0x0003));
registerArrayWrite16(CSC, value & 0xF9FF);
}
@@ -86,17 +90,17 @@ static inline void setCsd(uint16_t value){
chips[CHIP_D_RAM].enable = value & 0x0001;
chips[CHIP_D_RAM].readOnly = value & 0x8000;
if(csControl1 & 0x0040 && value & 0x0200)
chips[CHIP_D_RAM].size = 0x800000/*8mb*/ << (value >> 1 & 0x0001);
chips[CHIP_D_RAM].lineSize = 0x800000/*8mb*/ << (value >> 1 & 0x0001);
else
chips[CHIP_D_RAM].size = 0x8000/*32kb*/ << (value >> 1 & 0x0007);
chips[CHIP_D_RAM].lineSize = 0x8000/*32kb*/ << (value >> 1 & 0x0007);
//attributes
chips[CHIP_D_RAM].supervisorOnlyProtectedMemory = value & 0x4000;
chips[CHIP_D_RAM].readOnlyForProtectedMemory = value & 0x2000;
if(csControl1 & 0x4000 && csControl1 & 0x0010)
chips[CHIP_D_RAM].unprotectedSize = 0x8000/*32kb*/ << ((value >> 11 & 0x0003) | 0x0004);
chips[CHIP_D_RAM].unprotectedSize = chips[CHIP_D_RAM].lineSize / (1 << 7 - ((value >> 11 & 0x0003) | 0x0004));
else
chips[CHIP_D_RAM].unprotectedSize = 0x8000/*32kb*/ << (value >> 11 & 0x0003);
chips[CHIP_D_RAM].unprotectedSize = chips[CHIP_D_RAM].lineSize / (1 << 7 - (value >> 11 & 0x0003));
registerArrayWrite16(CSD, value);
}
@@ -149,21 +153,6 @@ static inline void setCsgbd(uint16_t value){
registerArrayWrite16(CSGBD, value & 0xFFFE);
}
static inline void setCsctrl1(uint16_t value){
uint16_t oldCsctrl1 = registerArrayRead16(CSCTRL1);
registerArrayWrite16(CSCTRL1, value & 0x7F55);
if((oldCsctrl1 & 0x4055) != (value & 0x4055)){
//something important changed, update all chipselects
//CSA is not dependant on CSCTRL1
setCsb(registerArrayRead16(CSB));
setCsc(registerArrayRead16(CSC));
setCsd(registerArrayRead16(CSD));
}
}
//csctrl 2 and 3 only deal with timing and bus transfer size
static inline void setPllfsr(uint16_t value){
uint16_t oldPllfsr = registerArrayRead16(PLLFSR);
if(!(oldPllfsr & 0x4000)){

38
src/memoryAccess.c
View File

@@ -81,9 +81,12 @@ static inline void sed1376Write32(uint32_t address, uint32_t value){
}
static inline bool probeRead(uint8_t bank, uint32_t address){
if(chips[bank].supervisorOnlyProtectedMemory && address >= chips[bank].unprotectedSize && !(m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)){
setPrivilegeViolation(address, false);
return false;
if(chips[bank].supervisorOnlyProtectedMemory){
uint32_t index = address - chips[bank].start % chips[bank].lineSize;//below size = CS*0 any value above size is considered CS*1
if(index >= chips[bank].unprotectedSize && !(m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)){
setPrivilegeViolation(address, false);
return false;
}
}
return true;
}
@@ -93,14 +96,17 @@ static inline bool probeWrite(uint8_t bank, uint32_t address){
setWriteProtectViolation(address);
return false;
}
else if(address >= chips[bank].unprotectedSize){
if(chips[bank].supervisorOnlyProtectedMemory && !(m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)){
setPrivilegeViolation(address, true);
return false;
}
if(chips[bank].readOnlyForProtectedMemory){
setWriteProtectViolation(address);
return false;
else if(chips[bank].supervisorOnlyProtectedMemory || chips[bank].readOnlyForProtectedMemory){
uint32_t index = address - chips[bank].start % chips[bank].lineSize;//below size = CS*0 any value above size is considered CS*1
if(index >= chips[bank].unprotectedSize){
if(chips[bank].supervisorOnlyProtectedMemory && !(m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)){
setPrivilegeViolation(address, true);
return false;
}
if(chips[bank].readOnlyForProtectedMemory){
setWriteProtectViolation(address);
return false;
}
}
}
return true;
@@ -343,16 +349,16 @@ static uint8_t getProperBankType(uint32_t bank){
//registers have first priority, they cover 0xFFFFF000 even if a chipselect overlaps this area or CHIP_A_ROM is in boot mode
return CHIP_REGISTERS;
}
else if(chips[CHIP_A_ROM].inBootMode || (chips[CHIP_A_ROM].enable && BANK_IN_RANGE(bank, chips[CHIP_A_ROM].start, chips[CHIP_A_ROM].size))){
else if(chips[CHIP_A_ROM].inBootMode || (chips[CHIP_A_ROM].enable && BANK_IN_RANGE(bank, chips[CHIP_A_ROM].start, chips[CHIP_A_ROM].lineSize * 2))){
return CHIP_A_ROM;
}
else if(chips[CHIP_B_SED].enable && BANK_IN_RANGE(bank, chips[CHIP_B_SED].start, chips[CHIP_B_SED].size) && sed1376ClockConnected()){
else if(chips[CHIP_B_SED].enable && BANK_IN_RANGE(bank, chips[CHIP_B_SED].start, chips[CHIP_B_SED].lineSize * 2) && sed1376ClockConnected()){
return CHIP_B_SED;
}
else if(chips[CHIP_C_USB].enable && BANK_IN_RANGE(bank, chips[CHIP_C_USB].start, chips[CHIP_C_USB].size)){
else if(chips[CHIP_C_USB].enable && BANK_IN_RANGE(bank, chips[CHIP_C_USB].start, chips[CHIP_C_USB].lineSize * 2)){
return CHIP_C_USB;
}
else if(chips[CHIP_D_RAM].enable && BANK_IN_RANGE(bank, chips[CHIP_D_RAM].start, chips[CHIP_D_RAM].size)){
else if(chips[CHIP_D_RAM].enable && BANK_IN_RANGE(bank, chips[CHIP_D_RAM].start, chips[CHIP_D_RAM].lineSize * 2)){
return CHIP_D_RAM;
}
@@ -373,7 +379,7 @@ void setRegisterFFFFAccessMode(){
void setSed1376Attached(bool attached){
if(chips[CHIP_B_SED].enable && bankType[START_BANK(chips[CHIP_B_SED].start)] != (attached ? CHIP_B_SED : CHIP_NONE))
memset(&bankType[START_BANK(chips[CHIP_B_SED].start)], attached ? CHIP_B_SED : CHIP_NONE, END_BANK(chips[CHIP_B_SED].start, chips[CHIP_B_SED].size) - START_BANK(chips[CHIP_B_SED].start) + 1);
memset(&bankType[START_BANK(chips[CHIP_B_SED].start)], attached ? CHIP_B_SED : CHIP_NONE, END_BANK(chips[CHIP_B_SED].start, chips[CHIP_B_SED].lineSize) - START_BANK(chips[CHIP_B_SED].start) + 1);
}
void resetAddressSpace(){

2
unimplementedHardware.txt
View File

@@ -47,6 +47,8 @@ USB chip may be swapped in to address space with a GPIO and reconfiguring CSC ch
EMUCS memory range is unemulated
CSD and CSC chaining to create a 16mb address space from 4x4mb chunks(the Palm m515 does this to create its 16mb RAM address space, verified with hardware test)
the second line on all the chip selects is not properly emulated, CS(ABCD)1 is missing, this halves the size of the ranges, if the ROM only uses one chip per chip select this will go unnoticed
CSC and CSD chaining may just be CSD using CSC lines an losing a chipselect, the CSC address space is never accessed, this further supports chaining or losing this chipselect
there is conflicting information on wether the DRAM bit effects CSC, needs a test made
SED1376:
swivelview register