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Fix how duty cycle is used
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@@ -120,7 +120,7 @@ typedef struct{
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//system constants
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#define CRYSTAL_FREQUENCY 32768
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#define AUDIO_AMPLITUDE INT16_MAX
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#define AUDIO_AMPLITUDE 1000000
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#define AUDIO_SAMPLES_PER_FRAME (AUDIO_SAMPLE_RATE / EMU_FPS)
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#define AUDIO_END_OF_FRAME 1000000000//used to convert the variable timing of SYSCLK and CLK32 to a fixed location in the current frame 0<->AUDIO_END_OF_FRAME
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#define AUDIO_WAIT_FOR_SAMPLE INT32_MIN
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@@ -85,19 +85,19 @@ int32_t pwm1FifoRunSample(int32_t now, int32_t clockOffset){
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uint8_t prescaler = (pwmc1 >> 8 & 0x7F) + 1;
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uint8_t clockDivider = 2 << (pwmc1 & 0x03);
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uint8_t repeat = 1 << (pwmc1 >> 2 & 0x03);
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double dutyCycle = dMin((double)sample / period, 1.0);
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int32_t audioStart = now + clockOffset;
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int32_t audioNow = audioStart;
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int32_t audioSampleDuration = usingClk32 ? audioGetFramePercentIncrementFromClk32s(period * prescaler * clockDivider) : audioGetFramePercentIncrementFromSysclks(period * prescaler * clockDivider);
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int32_t audioDutyCycle = audioSampleDuration * dutyCycle;
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int32_t audioDeew = dMin((double)sample / period, 1.0)/*dutyCycle*/ * AUDIO_AMPLITUDE;
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for(uint8_t times = 0; times < repeat; times++){
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//At the beginning of a sample period cycle, the PWMO pin is set to 1 and the counter begins counting up from 0x00.
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//The sample value is compared on each count of the prescaler clock.
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//When the sample and count values match, the PWMO signal is cleared to 0.
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//MC68VZ328UM.pdf
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blip_add_delta(palmAudioResampler, audioNow, AUDIO_AMPLITUDE);
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blip_add_delta(palmAudioResampler, audioNow + audioDutyCycle, -AUDIO_AMPLITUDE);
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//debugLog("Audio sample played, dutyCycle:%f, start:%d, end:%d\n", dutyCycle, audioNow, audioNow + audioDutyCycle);
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blip_add_delta(palmAudioResampler, audioNow, audioDeew);
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blip_add_delta(palmAudioResampler, audioNow + audioSampleDuration, -audioDeew);
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audioNow += audioSampleDuration;
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}
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