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https://github.com/libretro/Mu.git
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Share hardwareRegisterNames.h between tests and emulator, update emuFeatureRegisterSpec.h
This commit is contained in:
meepingsnesroms
@@ -1,5 +1,6 @@
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#ifndef EMU_FEATURE_REGISTERS_SPEC_HEADER
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#define EMU_FEATURE_REGISTERS_SPEC_HEADER
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/*
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All emu feature registers are 32 bit accessing them in any other way will be undefined behavior.
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These registers will do nothing it there corresponding feature bit is not set on launch.
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@@ -46,7 +47,7 @@ These registers will do nothing it there corresponding feature bit is not set on
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/*new system cmds go here*/
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#define CMD_IDLE_X_CLK32 0xFFFC/*used to remove idle loops*/
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#define CMD_RUN_AS_M68K 0xFFFD/*emulStateP is ignored, EMU_SRC = argsOnStackP, EMU_SIZE = argsSizeAndwantA0, EMU_VALUE = trapOrFunction, on exit EMU_VALUE = Call68KFuncType() return value*/
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#define CMD_RUN_AS_ARM 0xFFFE/*EMU_SRC = nativeFuncP, EMU_DST = userDataP, on exit EMU_VALUE = PceNativeCall() return value*/
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#define CMD_SET_CYCLE_COST 0xFFFF/*EMU_DST = HLE API number, EMU_VALUE = how many cycles it takes*/
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@@ -58,4 +59,5 @@ These registers will do nothing it there corresponding feature bit is not set on
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#define EXT_BUTTON_LEFT 0x01000000
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#define EXT_BUTTON_RIGHT 0x02000000
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#define EXT_BUTTON_SELECT 0x04000000
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#endif
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174
hwTestSuite/hardwareRegisterNames.h
Normal file
174
hwTestSuite/hardwareRegisterNames.h
Normal file
@@ -0,0 +1,174 @@
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#ifndef DRAGONBALL_VZ_REGISTER_H
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#define DRAGONBALL_VZ_REGISTER_H
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/*Dragonball VZ Hardware Register Definitions*/
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#define HW_REG_ADDR(x) (0xFFFFF000 | (x))
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/*SIM - System Integration Module*/
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#define SCR 0x000/*System Control Register*/
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#define PCR 0x003/*Peripheral control register*/
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#define IDR 0x004/*Silicon ID register*/
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#define IODCR 0x008/*I/O drive control register*/
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/*CS - Chip Select*/
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#define CSGBA 0x100/*Chip Select Group A Base Register*/
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#define CSGBB 0x102/*Chip Select Group B Base Register*/
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#define CSGBC 0x104/*Chip Select Group C Base Register*/
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#define CSGBD 0x106/*Chip Select Group D Base Register*/
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#define CSUGBA 0x108/*Chip Select Upper Group Address Register*/
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#define CSCTRL1 0x10A/*Chip Select Control Register 1*/
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#define CSCTRL2 0x10C/*Chip Select Control Register 2*/
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#define CSCTRL3 0x150/*Chip Select Control Register 3*/
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#define CSA 0x110/*Group A Chip Select Register*/
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#define CSB 0x112/*Group B Chip Select Register*/
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#define CSC 0x114/*Group C Chip Select Register*/
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#define CSD 0x116/*Group D Chip Select Register*/
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#define EMUCS 0x118/*Emulation chip-select register*/
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/*PLL - Phase Locked Loop*/
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#define PLLCR 0x200/*PLL Control Register*/
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#define PLLFSR 0x202/*PLL Frequency Select Register*/
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#define PCTLR 0x207/*Power Control Register*/
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/*INTR - Interrupt controller*/
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#define IVR 0x300/*Interrupt Vector Register*/
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#define ICR 0x302/*Interrupt Control Register*/
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#define IMR 0x304/*Interrupt Mask Register*/
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/*Reserved 0x308 Interrupt Wakeup Enable Register On Original Dragonball*/
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#define ISR 0x30C/*Interrupt Status Register*/
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#define IPR 0x310/*Interrupt Pending Register*/
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#define ILCR 0x314/*Interrupt Level Control Register*/
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/*PIO - Parallel IO*/
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#define PADIR 0x400/*Port A Direction Register*/
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#define PADATA 0x401/*Port A Data Register*/
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#define PAPUEN 0x402/*Port A Pull-Up Enable Register*/
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#define PBDIR 0x408/*Port B Direction Register*/
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#define PBDATA 0x409/*Port B Data Register*/
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#define PBPUEN 0x40A/*Port B Pull-Up Enable Register*/
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#define PBSEL 0x40B/*Port B Select Register*/
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#define PCDIR 0x410/*Port C Direction Register*/
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#define PCDATA 0x411/*Port C Data Register*/
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#define PCPDEN 0x412/*Port C Pull-Down Enable Register*/
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#define PCSEL 0x413/*Port C Select Register*/
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#define PDDIR 0x418/*Port D Direction Register*/
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#define PDDATA 0x419/*Port D Data Register*/
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#define PDPUEN 0x41A/*Port D Pull-Up Enable Register*/
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#define PDSEL 0x41B/*Port D Select Register*/
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#define PDPOL 0x41C/*Port D Polarity Register*/
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#define PDIRQEN 0x41D/*Port D IRQ Enable Register*/
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#define PDKBEN 0x41E/*Port D Keyboard Enable Register*/
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#define PDIRQEG 0x41F/*Port D IRQ Edge Register*/
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#define PEDIR 0x420/*Port E Direction Register*/
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#define PEDATA 0x421/*Port E Data Register*/
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#define PEPUEN 0x422/*Port E Pull-Up Enable Register*/
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#define PESEL 0x423/*Port E Select Register*/
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#define PFDIR 0x428/*Port F Direction Register*/
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#define PFDATA 0x429/*Port F Data Register*/
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#define PFPUEN 0x42A/*Port F Pull-Up Enable Register*/
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#define PFSEL 0x42B/*Port F Select Register*/
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#define PGDIR 0x430/*Port G Direction Register*/
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#define PGDATA 0x431/*Port G Data Register*/
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#define PGPUEN 0x432/*Port G Pull-Up Enable Register*/
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#define PGSEL 0x433/*Port G Select Register*/
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#define PJDIR 0x438/*Port J Direction Register*/
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#define PJDATA 0x439/*Port J Data Register*/
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#define PJPUEN 0x43A/*Port J Pull-Up Enable Register*/
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#define PJSEL 0x43B/*Port J Select Register*/
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#define PKDIR 0x440/*Port K Direction Register*/
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#define PKDATA 0x441/*Port K Data Register*/
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#define PKPUEN 0x442/*Port K Pull-Up Enable Register*/
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#define PKSEL 0x443/*Port K Select Register*/
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#define PMDIR 0x448/*Port M Direction Register*/
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#define PMDATA 0x449/*Port M Data Register*/
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#define PMPUEN 0x44A/*Port M Pull-Up Enable Register*/
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#define PMSEL 0x44B/*Port M Select Register*/
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/*PWM - Pulse Width Modulator*/
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#define PWMC1 0x500/*PWM Unit 1 Control Register*/
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#define PWMS1 0x502/*PWM Unit 1 Sample Register*/
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#define PWMP1 0x504/*PWM Unit 1 Period Register*/
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#define PWMCNT1 0x505/*PWM Unit 1 Counter Register*/
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/*Timer*/
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#define TCTL1 0x600/*Timer Unit 1 Control Register*/
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#define TPRER1 0x602/*Timer Unit 1 Prescaler Register*/
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#define TCMP1 0x604/*Timer Unit 1 Compare Register*/
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#define TCN1 0x608/*Timer Unit 1 Counter*/
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#define TSTAT1 0x60A/*Timer Unit 1 Status Register*/
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#define TCTL2 0x610/*Timer Unit 2 Control Register*/
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#define TPRER2 0x612/*Timer Unit 2 Prescaler Register*/
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#define TCMP2 0x614/*Timer Unit 2 Compare Register*/
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#define TCN2 0x618/*Timer Unit 2 Counter*/
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#define TSTAT2 0x61A/*Timer Unit 2 Status Register*/
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/*WD - Watchdog*/
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#define WATCHDOG 0xB0A/*Watchdog Timer Register*/
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/*SPI - Serial Peripheral Interface*/
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#define SPIRXD 0x700/*SPI 1 Receive Data Register*/
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#define SPITXD 0x702/*SPI 1 Transmit Data Register*/
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#define SPICONT1 0x704/*SPI 1 Control/Status Register*/
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#define SPIINTCS 0x706/*SPI 1 Interrupt Control/Status Register*/
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#define SPITEST 0x708/*SPI 1 Test Register*/
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#define SPISPC 0x70A/*SPI 1 Sample Period Control Register*/
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#define SPIDATA2 0x800/*SPI 2 Data Register*/
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#define SPICONT2 0x802/*SPI 2 Control/Status Register*/
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/*UART - Universal Asynchronous Receiver/Transmitter*/
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#define USTCNT1 0x900/*UART Unit 1 Status/Control Register*/
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#define UBAUD1 0x902/*UART Unit 1 Baud Control Register*/
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#define URX1 0x904/*UART Unit 1 RX Register*/
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#define UTX1 0x906/*UART Unit 1 TX Register*/
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#define UMISC1 0x908/*UART Unit 1 Misc Register*/
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#define USTCNT2 0x910/*UART Unit 2 Status/Control Register*/
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#define UBAUD2 0x912/*UART Unit 2 Baud Control Register*/
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#define URX2 0x914/*UART Unit 2 RX Register*/
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#define UTX2 0x916/*UART Unit 2 TX Register*/
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#define UMISC2 0x918/*UART Unit 2 Misc Register*/
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#define NIPR2 0x91A/*UART Unit 2 Non-Integer Prescaler Register*/
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#define HMARK 0x91C/*UART Unit 2 FIFO Half Mark Register*/
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/*LCDC - LCD Controller*/
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#define LSSA 0xA00/*Screen Starting Address Register*/
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#define LVPW 0xA05/*Virtual Page Width Register*/
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#define LXMAX 0xA08/*Screen Width Register*/
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#define LYMAX 0xA0A/*Screen Height Register*/
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#define LCXP 0xA18/*Cursor X Position*/
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#define LCYP 0xA1A/*Cursor Y Position*/
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#define LCWCH 0xA1C/*Cursor Width & Height Register*/
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#define LBLKC 0xA1F/*Blink Control Register*/
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#define LPICF 0xA20/*Panel Interface Config Register*/
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#define LPXCD 0xA25/*Pixel Clock Divider Register*/
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#define LCKCON 0xA27/*Clocking Control Register*/
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#define LRRA 0xA28/*LCD Refresh Rate Adjustment Register*/
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/*Reserved 0xA2B Octet Terminal Count Register On Original Dragonball*/
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#define LFRCM 0xA31/*Frame Rate Control Modulation Register*/
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#define LGPMR 0xA33/*Gray Palette Mapping Register*/
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#define DMACR 0xA39/*DMA Control Register*/
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/*RTC - Real Time Clock*/
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#define RTCTIME 0xB00/*RTC Time Of Day Register*/
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#define RTCALRM 0xB04/*RTC Alarm Register*/
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#define RTCCTL 0xB0C/*RTC Control Register*/
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#define RTCISR 0xB0E/*RTC Interrupt Status Register*/
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#define RTCIENR 0xB10/*RTC Interrupt Enable Register*/
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#define STPWCH 0xB12/*Stopwatch Minutes Register*/
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#define DAYR 0xB1A/*RTC Day Count Register*/
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/*RAM - (S)DRAM Control*/
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#define DRAMMC 0xC00/*DRAM Memory Configuration Register*/
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#define DRAMC 0xC02/*DRAM Control Register*/
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#define SDCTRL 0xC04/*SDRAM Control Register*/
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#endif
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@@ -1,5 +1,6 @@
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#ifndef EMU_FEATURE_REGISTERS_SPEC_HEADER
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#define EMU_FEATURE_REGISTERS_SPEC_HEADER
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/*
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All emu feature registers are 32 bit accessing them in any other way will be undefined behavior.
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These registers will do nothing it there corresponding feature bit is not set on launch.
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@@ -46,7 +47,7 @@ These registers will do nothing it there corresponding feature bit is not set on
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/*new system cmds go here*/
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#define CMD_IDLE_X_CLK32 0xFFFC/*used to remove idle loops*/
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#define CMD_RUN_AS_M68K 0xFFFD/*emulStateP is ignored, EMU_SRC = argsOnStackP, EMU_SIZE = argsSizeAndwantA0, EMU_VALUE = trapOrFunction, on exit EMU_VALUE = Call68KFuncType() return value*/
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#define CMD_RUN_AS_ARM 0xFFFE/*EMU_SRC = nativeFuncP, EMU_DST = userDataP, on exit EMU_VALUE = PceNativeCall() return value*/
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#define CMD_SET_CYCLE_COST 0xFFFF/*EMU_DST = HLE API number, EMU_VALUE = how many cycles it takes*/
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@@ -58,4 +59,5 @@ These registers will do nothing it there corresponding feature bit is not set on
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#define EXT_BUTTON_LEFT 0x01000000
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#define EXT_BUTTON_RIGHT 0x02000000
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#define EXT_BUTTON_SELECT 0x04000000
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#endif
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@@ -1,163 +1,174 @@
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#pragma once
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//Dragonball VZ Hardware Register Definitions
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#ifndef DRAGONBALL_VZ_REGISTER_H
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#define DRAGONBALL_VZ_REGISTER_H
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//SIM - System Integration Module
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#define SCR 0x000//System Control Register
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#define PCR 0x003//Peripheral control register
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#define IDR 0x004//Silicon ID register
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#define IODCR 0x008//I/O drive control register
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/*Dragonball VZ Hardware Register Definitions*/
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#define HW_REG_ADDR(x) (0xFFFFF000 | (x))
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//CS - Chip Select
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#define CSGBA 0x100//Chip Select Group A Base Register
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#define CSGBB 0x102//Chip Select Group B Base Register
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#define CSGBC 0x104//Chip Select Group C Base Register
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#define CSGBD 0x106//Chip Select Group D Base Register
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#define CSUGBA 0x108//Chip Select Upper Group Address Register
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#define CSCTRL1 0x10A//Chip Select Control Register 1
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#define CSCTRL2 0x10C//Chip Select Control Register 2
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#define CSCTRL3 0x150//Chip Select Control Register 3
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#define CSA 0x110//Group A Chip Select Register
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#define CSB 0x112//Group B Chip Select Register
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#define CSC 0x114//Group C Chip Select Register
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#define CSD 0x116//Group D Chip Select Register
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#define EMUCS 0x118//Emulation chip-select register
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/*SIM - System Integration Module*/
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#define SCR 0x000/*System Control Register*/
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#define PCR 0x003/*Peripheral control register*/
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#define IDR 0x004/*Silicon ID register*/
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#define IODCR 0x008/*I/O drive control register*/
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//PLL - Phase Locked Loop
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#define PLLCR 0x200//PLL Control Register
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#define PLLFSR 0x202//PLL Frequency Select Register
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#define PCTLR 0x207//Power Control Register
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/*CS - Chip Select*/
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#define CSGBA 0x100/*Chip Select Group A Base Register*/
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#define CSGBB 0x102/*Chip Select Group B Base Register*/
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#define CSGBC 0x104/*Chip Select Group C Base Register*/
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#define CSGBD 0x106/*Chip Select Group D Base Register*/
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#define CSUGBA 0x108/*Chip Select Upper Group Address Register*/
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#define CSCTRL1 0x10A/*Chip Select Control Register 1*/
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#define CSCTRL2 0x10C/*Chip Select Control Register 2*/
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#define CSCTRL3 0x150/*Chip Select Control Register 3*/
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#define CSA 0x110/*Group A Chip Select Register*/
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#define CSB 0x112/*Group B Chip Select Register*/
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#define CSC 0x114/*Group C Chip Select Register*/
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#define CSD 0x116/*Group D Chip Select Register*/
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#define EMUCS 0x118/*Emulation chip-select register*/
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//INTR - Interrupt controller
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#define IVR 0x300//Interrupt Vector Register
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#define ICR 0x302//Interrupt Control Register
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#define IMR 0x304//Interrupt Mask Register
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//Reserved 0x308//Interrupt Wakeup Enable Register On Original Dragonball
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#define ISR 0x30C//Interrupt Status Register
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#define IPR 0x310//Interrupt Pending Register
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#define ILCR 0x314//Interrupt Level Control Register
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/*PLL - Phase Locked Loop*/
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#define PLLCR 0x200/*PLL Control Register*/
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#define PLLFSR 0x202/*PLL Frequency Select Register*/
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#define PCTLR 0x207/*Power Control Register*/
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//PIO - Parallel IO
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#define PADIR 0x400//Port A Direction Register
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#define PADATA 0x401//Port A Data Register
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#define PAPUEN 0x402//Port A Pull-Up Enable Register
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/*INTR - Interrupt controller*/
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#define IVR 0x300/*Interrupt Vector Register*/
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#define ICR 0x302/*Interrupt Control Register*/
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#define IMR 0x304/*Interrupt Mask Register*/
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/*Reserved 0x308 Interrupt Wakeup Enable Register On Original Dragonball*/
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#define ISR 0x30C/*Interrupt Status Register*/
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#define IPR 0x310/*Interrupt Pending Register*/
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#define ILCR 0x314/*Interrupt Level Control Register*/
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#define PBDIR 0x408//Port B Direction Register
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#define PBDATA 0x409//Port B Data Register
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#define PBPUEN 0x40A//Port B Pull-Up Enable Register
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#define PBSEL 0x40B//Port B Select Register
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/*PIO - Parallel IO*/
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#define PADIR 0x400/*Port A Direction Register*/
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#define PADATA 0x401/*Port A Data Register*/
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#define PAPUEN 0x402/*Port A Pull-Up Enable Register*/
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#define PCDIR 0x410//Port C Direction Register
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#define PCDATA 0x411//Port C Data Register
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#define PCPDEN 0x412//Port C Pull-Down Enable Register
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#define PCSEL 0x413//Port C Select Register
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#define PBDIR 0x408/*Port B Direction Register*/
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#define PBDATA 0x409/*Port B Data Register*/
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#define PBPUEN 0x40A/*Port B Pull-Up Enable Register*/
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#define PBSEL 0x40B/*Port B Select Register*/
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#define PDDIR 0x418//Port D Direction Register
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#define PDDATA 0x419//Port D Data Register
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#define PDPUEN 0x41A//Port D Pull-Up Enable Register
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#define PDSEL 0x41B//Port D Select Register
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#define PDPOL 0x41C//Port D Polarity Register
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#define PDIRQEN 0x41D//Port D IRQ Enable Register
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#define PDKBEN 0x41E//Port D Keyboard Enable Register
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#define PDIRQEG 0x41F//Port D IRQ Edge Register
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#define PCDIR 0x410/*Port C Direction Register*/
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#define PCDATA 0x411/*Port C Data Register*/
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#define PCPDEN 0x412/*Port C Pull-Down Enable Register*/
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#define PCSEL 0x413/*Port C Select Register*/
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#define PEDIR 0x420//Port E Direction Register
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#define PEDATA 0x421//Port E Data Register
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#define PEPUEN 0x422//Port E Pull-Up Enable Register
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#define PESEL 0x423//Port E Select Register
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#define PDDIR 0x418/*Port D Direction Register*/
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#define PDDATA 0x419/*Port D Data Register*/
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#define PDPUEN 0x41A/*Port D Pull-Up Enable Register*/
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#define PDSEL 0x41B/*Port D Select Register*/
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#define PDPOL 0x41C/*Port D Polarity Register*/
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#define PDIRQEN 0x41D/*Port D IRQ Enable Register*/
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#define PDKBEN 0x41E/*Port D Keyboard Enable Register*/
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#define PDIRQEG 0x41F/*Port D IRQ Edge Register*/
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#define PFDIR 0x428//Port F Direction Register
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#define PFDATA 0x429//Port F Data Register
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#define PFPUEN 0x42A//Port F Pull-Up Enable Register
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#define PFSEL 0x42B//Port F Select Register
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#define PEDIR 0x420/*Port E Direction Register*/
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#define PEDATA 0x421/*Port E Data Register*/
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#define PEPUEN 0x422/*Port E Pull-Up Enable Register*/
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#define PESEL 0x423/*Port E Select Register*/
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#define PGDIR 0x430//Port G Direction Register
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#define PGDATA 0x431//Port G Data Register
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||||
#define PGPUEN 0x432//Port G Pull-Up Enable Register
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||||
#define PGSEL 0x433//Port G Select Register
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||||
#define PFDIR 0x428/*Port F Direction Register*/
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#define PFDATA 0x429/*Port F Data Register*/
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#define PFPUEN 0x42A/*Port F Pull-Up Enable Register*/
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#define PFSEL 0x42B/*Port F Select Register*/
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#define PJDIR 0x438//Port J Direction Register
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||||
#define PJDATA 0x439//Port J Data Register
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||||
#define PJPUEN 0x43A//Port J Pull-Up Enable Register
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||||
#define PJSEL 0x43B//Port J Select Register
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||||
#define PGDIR 0x430/*Port G Direction Register*/
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||||
#define PGDATA 0x431/*Port G Data Register*/
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||||
#define PGPUEN 0x432/*Port G Pull-Up Enable Register*/
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||||
#define PGSEL 0x433/*Port G Select Register*/
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||||
|
||||
#define PKDIR 0x440//Port K Direction Register
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||||
#define PKDATA 0x441//Port K Data Register
|
||||
#define PKPUEN 0x442//Port K Pull-Up Enable Register
|
||||
#define PKSEL 0x443//Port K Select Register
|
||||
#define PJDIR 0x438/*Port J Direction Register*/
|
||||
#define PJDATA 0x439/*Port J Data Register*/
|
||||
#define PJPUEN 0x43A/*Port J Pull-Up Enable Register*/
|
||||
#define PJSEL 0x43B/*Port J Select Register*/
|
||||
|
||||
#define PMDIR 0x448//Port M Direction Register
|
||||
#define PMDATA 0x449//Port M Data Register
|
||||
#define PMPUEN 0x44A//Port M Pull-Up Enable Register
|
||||
#define PMSEL 0x44B//Port M Select Register
|
||||
#define PKDIR 0x440/*Port K Direction Register*/
|
||||
#define PKDATA 0x441/*Port K Data Register*/
|
||||
#define PKPUEN 0x442/*Port K Pull-Up Enable Register*/
|
||||
#define PKSEL 0x443/*Port K Select Register*/
|
||||
|
||||
//PWM - Pulse Width Modulator
|
||||
#define PWMC1 0x500//PWM Unit 1 Control Register
|
||||
#define PWMS1 0x502//PWM Unit 1 Sample Register
|
||||
#define PWMP1 0x504//PWM Unit 1 Period Register
|
||||
#define PWMCNT1 0x505//PWM Unit 1 Counter Register
|
||||
#define PMDIR 0x448/*Port M Direction Register*/
|
||||
#define PMDATA 0x449/*Port M Data Register*/
|
||||
#define PMPUEN 0x44A/*Port M Pull-Up Enable Register*/
|
||||
#define PMSEL 0x44B/*Port M Select Register*/
|
||||
|
||||
//Timer
|
||||
#define TCTL1 0x600//Timer Unit 1 Control Register
|
||||
#define TPRER1 0x602//Timer Unit 1 Prescaler Register
|
||||
#define TCMP1 0x604//Timer Unit 1 Compare Register
|
||||
#define TCN1 0x608//Timer Unit 1 Counter
|
||||
#define TSTAT1 0x60A//Timer Unit 1 Status Register
|
||||
#define TCTL2 0x610//Timer Unit 2 Control Register
|
||||
#define TPRER2 0x612//Timer Unit 2 Prescaler Register
|
||||
#define TCMP2 0x614//Timer Unit 2 Compare Register
|
||||
#define TCN2 0x618//Timer Unit 2 Counter
|
||||
#define TSTAT2 0x61A//Timer Unit 2 Status Register
|
||||
/*PWM - Pulse Width Modulator*/
|
||||
#define PWMC1 0x500/*PWM Unit 1 Control Register*/
|
||||
#define PWMS1 0x502/*PWM Unit 1 Sample Register*/
|
||||
#define PWMP1 0x504/*PWM Unit 1 Period Register*/
|
||||
#define PWMCNT1 0x505/*PWM Unit 1 Counter Register*/
|
||||
|
||||
//WD - Watchdog
|
||||
#define WATCHDOG 0xB0A//Watchdog Timer Register
|
||||
/*Timer*/
|
||||
#define TCTL1 0x600/*Timer Unit 1 Control Register*/
|
||||
#define TPRER1 0x602/*Timer Unit 1 Prescaler Register*/
|
||||
#define TCMP1 0x604/*Timer Unit 1 Compare Register*/
|
||||
#define TCN1 0x608/*Timer Unit 1 Counter*/
|
||||
#define TSTAT1 0x60A/*Timer Unit 1 Status Register*/
|
||||
#define TCTL2 0x610/*Timer Unit 2 Control Register*/
|
||||
#define TPRER2 0x612/*Timer Unit 2 Prescaler Register*/
|
||||
#define TCMP2 0x614/*Timer Unit 2 Compare Register*/
|
||||
#define TCN2 0x618/*Timer Unit 2 Counter*/
|
||||
#define TSTAT2 0x61A/*Timer Unit 2 Status Register*/
|
||||
|
||||
//SPI - Serial Peripheral Interface
|
||||
#define SPIDATA2 0x800//SPI Unit 2 Data Register
|
||||
#define SPICONT2 0x802//SPI Unit 2 Control/Status Register
|
||||
/*WD - Watchdog*/
|
||||
#define WATCHDOG 0xB0A/*Watchdog Timer Register*/
|
||||
|
||||
//UART - Universal Asynchronous Receiver/Transmitter
|
||||
#define USTCNT1 0x900//UART Unit 1 Status/Control Register
|
||||
#define UBAUD1 0x902//UART Unit 1 Baud Control Register
|
||||
#define URX1 0x904//UART Unit 1 RX Register
|
||||
#define UTX1 0x906//UART Unit 1 TX Register
|
||||
#define UMISC1 0x908//UART Unit 1 Misc Register
|
||||
/*SPI - Serial Peripheral Interface*/
|
||||
#define SPIRXD 0x700/*SPI 1 Receive Data Register*/
|
||||
#define SPITXD 0x702/*SPI 1 Transmit Data Register*/
|
||||
#define SPICONT1 0x704/*SPI 1 Control/Status Register*/
|
||||
#define SPIINTCS 0x706/*SPI 1 Interrupt Control/Status Register*/
|
||||
#define SPITEST 0x708/*SPI 1 Test Register*/
|
||||
#define SPISPC 0x70A/*SPI 1 Sample Period Control Register*/
|
||||
#define SPIDATA2 0x800/*SPI 2 Data Register*/
|
||||
#define SPICONT2 0x802/*SPI 2 Control/Status Register*/
|
||||
|
||||
#define USTCNT2 0x910//UART Unit 2 Status/Control Register
|
||||
#define UBAUD2 0x912//UART Unit 2 Baud Control Register
|
||||
#define URX2 0x914//UART Unit 2 RX Register
|
||||
#define UTX2 0x916//UART Unit 2 TX Register
|
||||
#define UMISC2 0x918//UART Unit 2 Misc Register
|
||||
#define NIPR2 0x91A//UART Unit 2 Non-Integer Prescaler Register
|
||||
#define HMARK 0x91C//UART Unit 2 FIFO Half Mark Register
|
||||
/*UART - Universal Asynchronous Receiver/Transmitter*/
|
||||
#define USTCNT1 0x900/*UART Unit 1 Status/Control Register*/
|
||||
#define UBAUD1 0x902/*UART Unit 1 Baud Control Register*/
|
||||
#define URX1 0x904/*UART Unit 1 RX Register*/
|
||||
#define UTX1 0x906/*UART Unit 1 TX Register*/
|
||||
#define UMISC1 0x908/*UART Unit 1 Misc Register*/
|
||||
|
||||
//LCDC - LCD Controller
|
||||
#define LSSA 0xA00//Screen Starting Address Register
|
||||
#define LVPW 0xA05//Virtual Page Width Register
|
||||
#define LXMAX 0xA08//Screen Width Register
|
||||
#define LYMAX 0xA0A//Screen Height Register
|
||||
#define LCXP 0xA18//Cursor X Position
|
||||
#define LCYP 0xA1A//Cursor Y Position
|
||||
#define LCWCH 0xA1C//Cursor Width & Height Register
|
||||
#define LBLKC 0xA1F//Blink Control Register
|
||||
#define LPICF 0xA20//Panel Interface Config Register
|
||||
#define LPXCD 0xA25//Pixel Clock Divider Register
|
||||
#define LCKCON 0xA27//Clocking Control Register
|
||||
#define LRRA 0xA28//LCD Refresh Rate Adjustment Register
|
||||
//Reserved 0xA2B//Octet Terminal Count Register On Original Dragonball
|
||||
#define LFRCM 0xA31//Frame Rate Control Modulation Register
|
||||
#define LGPMR 0xA33//Gray Palette Mapping Register
|
||||
#define DMACR 0xA39//DMA Control Register
|
||||
#define USTCNT2 0x910/*UART Unit 2 Status/Control Register*/
|
||||
#define UBAUD2 0x912/*UART Unit 2 Baud Control Register*/
|
||||
#define URX2 0x914/*UART Unit 2 RX Register*/
|
||||
#define UTX2 0x916/*UART Unit 2 TX Register*/
|
||||
#define UMISC2 0x918/*UART Unit 2 Misc Register*/
|
||||
#define NIPR2 0x91A/*UART Unit 2 Non-Integer Prescaler Register*/
|
||||
#define HMARK 0x91C/*UART Unit 2 FIFO Half Mark Register*/
|
||||
|
||||
//RTC - Real Time Clock
|
||||
#define RTCTIME 0xB00//RTC Time Of Day Register
|
||||
#define RTCALRM 0xB04//RTC Alarm Register
|
||||
#define RTCCTL 0xB0C//RTC Control Register
|
||||
#define RTCISR 0xB0E//RTC Interrupt Status Register
|
||||
#define RTCIENR 0xB10//RTC Interrupt Enable Register
|
||||
#define STPWCH 0xB12//Stopwatch Minutes Register
|
||||
#define DAYR 0xB1A//RTC Day Count Register
|
||||
/*LCDC - LCD Controller*/
|
||||
#define LSSA 0xA00/*Screen Starting Address Register*/
|
||||
#define LVPW 0xA05/*Virtual Page Width Register*/
|
||||
#define LXMAX 0xA08/*Screen Width Register*/
|
||||
#define LYMAX 0xA0A/*Screen Height Register*/
|
||||
#define LCXP 0xA18/*Cursor X Position*/
|
||||
#define LCYP 0xA1A/*Cursor Y Position*/
|
||||
#define LCWCH 0xA1C/*Cursor Width & Height Register*/
|
||||
#define LBLKC 0xA1F/*Blink Control Register*/
|
||||
#define LPICF 0xA20/*Panel Interface Config Register*/
|
||||
#define LPXCD 0xA25/*Pixel Clock Divider Register*/
|
||||
#define LCKCON 0xA27/*Clocking Control Register*/
|
||||
#define LRRA 0xA28/*LCD Refresh Rate Adjustment Register*/
|
||||
/*Reserved 0xA2B Octet Terminal Count Register On Original Dragonball*/
|
||||
#define LFRCM 0xA31/*Frame Rate Control Modulation Register*/
|
||||
#define LGPMR 0xA33/*Gray Palette Mapping Register*/
|
||||
#define DMACR 0xA39/*DMA Control Register*/
|
||||
|
||||
//RAM - (S)DRAM Control
|
||||
#define DRAMMC 0xC00//DRAM Memory Configuration Register
|
||||
#define DRAMC 0xC02//DRAM Control Register
|
||||
#define SDCTRL 0xC04//SDRAM Control Register
|
||||
/*RTC - Real Time Clock*/
|
||||
#define RTCTIME 0xB00/*RTC Time Of Day Register*/
|
||||
#define RTCALRM 0xB04/*RTC Alarm Register*/
|
||||
#define RTCCTL 0xB0C/*RTC Control Register*/
|
||||
#define RTCISR 0xB0E/*RTC Interrupt Status Register*/
|
||||
#define RTCIENR 0xB10/*RTC Interrupt Enable Register*/
|
||||
#define STPWCH 0xB12/*Stopwatch Minutes Register*/
|
||||
#define DAYR 0xB1A/*RTC Day Count Register*/
|
||||
|
||||
/*RAM - (S)DRAM Control*/
|
||||
#define DRAMMC 0xC00/*DRAM Memory Configuration Register*/
|
||||
#define DRAMC 0xC02/*DRAM Control Register*/
|
||||
#define SDCTRL 0xC04/*SDRAM Control Register*/
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user