Add back unknown register debug handlers

src/emulator.c

@@ -20,11 +20,12 @@
 //Memory Map of Palm m515
 //0x00000000-0x00FFFFFF RAM, the first 256(0x100) bytes is copyed from the first 256 bytes of ROM before boot, this applys to all Palms with the 68k architecture
 //0x10000000-0x103FFFFF ROM, palmos41-en-m515.rom, substitute "en" for your language code
+//0x10400000-0x10C00000 USB, CSC0, 8mb range(if DSIZ3 applys when CSC is not an extension of CSD), actual size unknown
 //0x1FF80000-0x1FF800B3 SED1376(Display Controller) Registers
 //0x1FFA0000-0x1FFB3FFF SED1376(Display Controller) Framebuffer, this is not the same as the Palm framebuffer which is always 16 bit color,
 //this buffer must be processed depending on whats in the SED1376 registers, the result is the Palm framebuffer
 //0xFFFFF000-0xFFFFFDFF Hardware Registers
-//0xFFFFFF00-0xFFFFFFFF Bootloader, only reads from UART into RAM and jumps to it, never executed in consumer Palms
+//0xFFFFFE00-0xFFFFFFFF Bootloader, only reads from UART into RAM and jumps to it, never executed in consumer Palms
 //VGhpcyBlbXVsYXRvciBpcyBkZWRpY2F0ZWQgdG8gdGhlIGJvdmluZSBtb28gY293cyB0aGF0IG1vby4=
 
 

src/hardwareRegisters.c

@@ -74,6 +74,13 @@ void refreshInputState(){
    }
    */
 
+   /*
+   if(palmInput.touchscreenTouched)
+      setIprIsrBit(INT_IRQ5);
+   else
+      clearIprIsrBit(INT_IRQ5);
+   */
+
    //check for button presses and interrupts
    checkPortDInterrupts();//this calls checkInterrupts() so it doesnt need to be called above
 }
@@ -438,6 +445,8 @@ uint8_t getHwRegister8(uint32_t address){
          //bootloader
          if(address >= 0xE00)
             return registerArrayRead8(address);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, 0, 8, false);
          return 0x00;
    }
    
@@ -507,6 +516,8 @@ uint16_t getHwRegister16(uint32_t address){
          //bootloader
          if(address >= 0xE00)
             return registerArrayRead16(address);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, 0, 16, false);
          return 0x0000;
    }
    
@@ -542,6 +553,8 @@ uint32_t getHwRegister32(uint32_t address){
          //bootloader
          if(address >= 0xE00)
             return registerArrayRead32(address);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, 0, 32, false);
          return 0x00000000;
    }
    
@@ -675,6 +688,8 @@ void setHwRegister8(uint32_t address, uint8_t value){
          //writeable bootloader region
          if(address >= 0xFC0)
             registerArrayWrite32(address, value);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, value, 8, true);
          break;
    }
 }
@@ -933,6 +948,8 @@ void setHwRegister16(uint32_t address, uint16_t value){
          //writeable bootloader region
          if(address >= 0xFC0)
             registerArrayWrite16(address, value);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, value, 16, true);
          break;
    }
 }
@@ -979,6 +996,8 @@ void setHwRegister32(uint32_t address, uint32_t value){
          //writeable bootloader region
          if(address >= 0xFC0)
             registerArrayWrite32(address, value);
+         if(address < 0xE00)
+            printUnknownHwAccess(address, value, 32, true);
          break;
    }
 }

src/hardwareRegistersAccessors.c.h

@@ -269,6 +269,15 @@ static inline void setSpiCont2(uint16_t value){
    else
       clearIprIsrBit(INT_SPI2);
 
+   /*
+   if(value & 0x0200 && !(oldSpiCont2 & 0x0200)){
+      //there may be some random shifing when enableing/disableing the register
+      for(uint8_t skip = 0; skip < 20; skip++)
+         ads7846ExchangeBit(false);
+      //this for some reason prevents the battery from shooting up to 100% after a few seconds?
+   }
+   */
+
    //do a transfer
    if(value & oldSpiCont2 & 0x0200 && value & 0x0100){
       //enabled and exchange set

unimplementedHardware.txt

@@ -46,6 +46,7 @@ the second line on all the chip selects is not properly emulated, they should be
 the CSC address space is never accessed, this may be because the DRAM controller takes it over
 there is conflicting information on wether the DRAM bit effects CSC, needs a test made
 chipselect mirroring is wrong(CS*0 and CS*1 are considered continuous when mapped with more address space than memory, mirroring is currently [CS*0, CS*1, repeat alternating till the end of address space] it should be [CS*0, repeat CS*0 until half way through CS* address space, CS*1, repeat CS*1 until end of CS* address space])
+CSC0 and CSA1 ranges overlap, something specifically stated as what not to do(the CSA1 pin is disabled though)
 
 SED1376:
 swivelview register