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https://github.com/libretro/Mu.git
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Add more USB port registers
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@@ -10,6 +10,8 @@
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//...
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#define UICR0 0x0050
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#define UICR1 0x0054
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#define USIR0 0x0058
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#define USIR1 0x005C
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//...
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#define UFNHR 0x0060
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@@ -18,6 +20,8 @@ uint8_t pxa260UdcUdccr;
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uint8_t pxa260UdcUdccs0;
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uint8_t pxa260UdcUicr0;
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uint8_t pxa260UdcUicr1;
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uint8_t pxa260UdcUsir0;
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uint8_t pxa260UdcUsir1;
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uint8_t pxa260UdcUfnhr;
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@@ -28,6 +32,8 @@ void pxa260UdcReset(void){
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//...
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pxa260UdcUicr0 = 0xFF;
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pxa260UdcUicr1 = 0xFF;
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pxa260UdcUsir0 = 0x00;
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pxa260UdcUsir1 = 0x00;
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//...
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pxa260UdcUfnhr = 0x40;
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}
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@@ -43,15 +49,27 @@ uint32_t pxa260UdcReadWord(uint32_t address){
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case UDCCS0:
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//TODO: need to | with RECEIVE FIFO NOT EMPTY
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debugLog("PXA260 UDC UDCCS0 read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUdccs0;
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case UICR0:
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debugLog("PXA260 UDC UICR0 read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUicr0;
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case UICR1:
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return pxa260UdcUicr0;
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debugLog("PXA260 UDC UICR1 read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUicr1;
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case USIR0:
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debugLog("PXA260 UDC USIR0 read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUsir0;
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case USIR1:
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debugLog("PXA260 UDC USIR1 read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUsir1;
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case UFNHR:
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debugLog("PXA260 UDC UFNHR read, PC:0x%08X\n", pxa260GetPc());
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return pxa260UdcUfnhr;
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default:
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@@ -65,27 +83,60 @@ void pxa260UdcWriteWord(uint32_t address, uint32_t value){
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switch(address){
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case UDCCR:
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//TODO: is incomplete
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debugLog("PXA260 UDC UDCCR write:0x%08X\n", value);
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pxa260UdcUdccr = value & 0xFF;
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debugLog("PXA260 UDC UDCCR write:0x%02X\n", value & 0xFF);
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if(value & 0x01){
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if(value & 0x04)
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debugLog("PXA260 UDC DEVICE RESUME SET\n");
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pxa260UdcUdccr = pxa260UdcUdccr & 0x5E | value & 0xA1;//write normal bits
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pxa260UdcUdccr &= ~(value & 0x58);//clear clear on 1 bits
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pxa260UdcUdccr |= value & 0x04;//set set on 1 bits
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}
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else{
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debugLog("PXA260 UDC reset\n");
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pxa260UdcReset();
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}
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//TODO: need to update interrupts
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return;
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case UDCCS0:
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debugLog("PXA260 UDC UDCCS0 write:0x%02X\n", value & 0xFF);
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pxa260UdcUdccs0 &= ~(value & 0x91);//clear clear on 1 bits
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pxa260UdcUdccs0 |= value & 0x26;//set set on 1 bits
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//TODO: need to update interrupts
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return;
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case UICR0:
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debugLog("PXA260 UDC UICR0 write:0x%02X\n", value & 0xFF);
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pxa260UdcUicr0 = value & 0xFF;
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//TODO: need to update interrupts
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return;
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case UICR1:
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debugLog("PXA260 UDC UICR1 write:0x%02X\n", value & 0xFF);
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pxa260UdcUicr1 = value & 0xFF;
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//TODO: need to update interrupts
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return;
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case USIR0:
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debugLog("PXA260 UDC USIR0 write:0x%02X\n", value & 0xFF);
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pxa260UdcUsir0 &= ~(value & 0xFF);
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//TODO: need to update interrupts
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return;
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case USIR1:
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debugLog("PXA260 UDC USIR1 write:0x%02X\n", value & 0xFF);
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pxa260UdcUicr1 &= ~(value & 0xFF);
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//TODO: need to update interrupts
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return;
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case UFNHR:
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debugLog("PXA260 UDC UFNHR write:0x%02X\n", value & 0xFF);
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pxa260UdcUfnhr = pxa260UdcUfnhr & 0xBF | value & 0x40;//write normal bits
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pxa260UdcUfnhr &= ~(value & 0xB8);//clear clear on 1 bits
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//TODO: need to update interrupts
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return;
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default:
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debugLog("Unimplimented 32 bit PXA260 UDC register write:0x%04X, value:0x%02X\n", address, value);
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return;
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