mirror of
https://github.com/libretro/Mu.git
synced 2026-09-24 15:46:20 +00:00
SYSCLKs are now separeate from CLK32
This commit is contained in:
meepingsnesroms
@@ -43,7 +43,7 @@ uint16_t* palmExtendedFramebuffer;
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int16_t palmAudio[AUDIO_SAMPLES * 2];
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uint32_t palmAudioSampleIndex;
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uint32_t palmSpecialFeatures;
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double palmCrystalCycles;//how many cycles before toggling the 32.768 kHz crystal
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double palmSysclksPerClk32;//how many SYSCLK cycles before toggling the 32.768 kHz crystal
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double palmCycleCounter;//can be greater then 0 if too many cycles where run
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double palmClockMultiplier;//used by the emulator to overclock the emulated Palm
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@@ -167,6 +167,7 @@ uint64_t emulatorGetStateSize(){
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size += sizeof(uint64_t) * 4;//32.32 fixed point double, timerXCycleCounter and CPU cycle timers
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size += sizeof(int32_t);//pllWakeWait
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size += sizeof(uint32_t);//clk32Counter
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size += sizeof(uint64_t);//pctlrCpuClockDivider
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size += sizeof(uint16_t) * 2;//timerStatusReadAcknowledge
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size += sizeof(uint32_t);//interruptEdgeTriggered
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size += sizeof(uint16_t) * 9;//RX 8 * 16 SPI1 FIFO, 1 index is for FIFO full
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@@ -247,7 +248,7 @@ bool emulatorSaveState(buffer_t buffer){
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}
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//timing
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writeStateValueDouble(buffer.data + offset, palmCrystalCycles);
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writeStateValueDouble(buffer.data + offset, palmSysclksPerClk32);
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offset += sizeof(uint64_t);
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writeStateValueDouble(buffer.data + offset, palmCycleCounter);
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offset += sizeof(uint64_t);
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@@ -255,6 +256,8 @@ bool emulatorSaveState(buffer_t buffer){
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offset += sizeof(int32_t);
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writeStateValueUint32(buffer.data + offset, clk32Counter);
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offset += sizeof(uint32_t);
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writeStateValueDouble(buffer.data + offset, pctlrCpuClockDivider);
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offset += sizeof(uint64_t);
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writeStateValueDouble(buffer.data + offset, timerCycleCounter[0]);
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offset += sizeof(uint64_t);
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writeStateValueDouble(buffer.data + offset, timerCycleCounter[1]);
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@@ -392,7 +395,7 @@ bool emulatorLoadState(buffer_t buffer){
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}
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//timing
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palmCrystalCycles = readStateValueDouble(buffer.data + offset);
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palmSysclksPerClk32 = readStateValueDouble(buffer.data + offset);
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offset += sizeof(uint64_t);
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palmCycleCounter = readStateValueDouble(buffer.data + offset);
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offset += sizeof(uint64_t);
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@@ -400,6 +403,8 @@ bool emulatorLoadState(buffer_t buffer){
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offset += sizeof(int32_t);
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clk32Counter = readStateValueUint32(buffer.data + offset);
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offset += sizeof(uint32_t);
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pctlrCpuClockDivider = readStateValueDouble(buffer.data + offset);
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offset += sizeof(uint64_t);
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timerCycleCounter[0] = readStateValueDouble(buffer.data + offset);
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offset += sizeof(uint64_t);
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timerCycleCounter[1] = readStateValueDouble(buffer.data + offset);
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@@ -525,8 +530,8 @@ void emulateFrame(){
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palmAudioSampleIndex = 0;
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while(palmCycleCounter < (double)CRYSTAL_FREQUENCY / EMU_FPS){
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if(palmCrystalCycles > 0.0)
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m68k_execute(palmCrystalCycles * palmClockMultiplier);
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m68k_execute(palmSysclksPerClk32 * pctlrCpuClockDivider * palmClockMultiplier);
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sysclks(palmSysclksPerClk32);
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clk32();
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palmCycleCounter += 1.0;
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}
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@@ -132,7 +132,7 @@ extern uint16_t* palmExtendedFramebuffer;//read allowed if FEATURE_320x320 is on
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extern int16_t palmAudio[];//read allowed, 2 channel signed 16 bit audio
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extern uint32_t palmAudioSampleIndex;//dont touch
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extern uint32_t palmSpecialFeatures;//read allowed
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extern double palmCrystalCycles;//dont touch
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extern double palmSysclksPerClk32;//dont touch
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extern double palmCycleCounter;//dont touch
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extern double palmClockMultiplier;//read/write allowed
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@@ -18,6 +18,7 @@
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chip_t chips[CHIP_END];
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int32_t pllWakeWait;
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uint32_t clk32Counter;
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double pctlrCpuClockDivider;
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double timerCycleCounter[2];
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uint16_t timerStatusReadAcknowledge[2];
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uint32_t interruptEdgeTriggered;
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@@ -35,8 +36,8 @@ uint8_t pwm1WritePosition;
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static void checkInterrupts();
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static void checkPortDInterrupts();
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static void recalculateCpuSpeed();
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static void pllWakeCpuIfOff();
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static double sysclksPerClk32();
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#include "hardwareRegistersAccessors.c.h"
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#include "hardwareRegistersTiming.c.h"
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@@ -112,30 +113,6 @@ void setWriteProtectViolation(uint32_t address){
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m68328BusError(address, true);
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}
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static void recalculateCpuSpeed(){
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double newCpuSpeed = sysclksPerClk32();
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uint8_t pctlr = registerArrayRead8(PCTLR);
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//power control burst mode
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if(pctlr & 0x80)
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newCpuSpeed *= (pctlr & 0x1F) / 31.0;
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/*
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if(newCpuSpeed != palmCrystalCycles){
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debugLog("New CPU frequency of:%f cycles per second.\n", newCpuSpeed * CRYSTAL_FREQUENCY);
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debugLog("New CLK32 cycle count of:%f.\n", newCpuSpeed);
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if(newCpuSpeed == 0.0){
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if(pllIsOn())
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debugLog("CPU turned off with PCTLR.\n");
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else
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debugLog("CPU turned off with DISPLL bit.\n");
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}
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}
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*/
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palmCrystalCycles = newCpuSpeed;
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}
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static void pllWakeCpuIfOff(){
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if(!pllIsOn() && pllWakeWait == -1){
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//PLL is off and not already in the process of waking up
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@@ -214,7 +191,7 @@ static void checkInterrupts(){
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//even masked interrupts turn off PCTLR, Chapter 4.5.4 MC68VZ328UM.pdf
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if(intLevel > 0 && registerArrayRead8(PCTLR) & 0x80){
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registerArrayWrite8(PCTLR, registerArrayRead8(PCTLR) & 0x1F);
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recalculateCpuSpeed();
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pctlrCpuClockDivider = 1.0;
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}
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m68k_set_irq(intLevel);//should be called even if intLevel is 0, that is how the interrupt state gets cleared
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@@ -647,7 +624,8 @@ void setHwRegister8(uint32_t address, uint8_t value){
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case PCTLR:
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registerArrayWrite8(address, value & 0x9F);
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recalculateCpuSpeed();
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if(value & 0x80)
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pctlrCpuClockDivider = (value & 0x1F) / 31.0;
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break;
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case IVR:
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@@ -836,7 +814,7 @@ void setHwRegister16(uint32_t address, uint16_t value){
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case PLLCR:
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//CLKEN is required for SED1376 operation
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registerArrayWrite16(PLLCR, value & 0x3FBB);
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recalculateCpuSpeed();
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palmSysclksPerClk32 = sysclksPerClk32();
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setSed1376Attached(sed1376ClockConnected());
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if(value & 0x0008){
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@@ -1090,8 +1068,9 @@ void resetHwRegisters(){
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uint16_t oldDayr = registerArrayRead16(DAYR);//preserve DAYR
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memset(palmReg, 0x00, REG_SIZE - BOOTLOADER_SIZE);
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palmCrystalCycles = 0.0;
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palmSysclksPerClk32 = 0.0;
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clk32Counter = 0;
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pctlrCpuClockDivider = 1.0;
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pllWakeWait = -1;
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timerCycleCounter[0] = 0.0;
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timerCycleCounter[1] = 0.0;
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@@ -1230,7 +1209,7 @@ void resetHwRegisters(){
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updateAds7846ChipSelectStatus();
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updateBacklightAmplifierStatus();
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recalculateCpuSpeed();
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palmSysclksPerClk32 = sysclksPerClk32();
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}
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void setRtc(uint16_t days, uint8_t hours, uint8_t minutes, uint8_t seconds){
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@@ -28,11 +28,9 @@
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#define INT_SPI2 0x00000001//level 4
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//reasons a timer is triggered
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#define TIMER_REASON_STOP 0x0000
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#define TIMER_REASON_SYSCLK 0x0001
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#define TIMER_REASON_SYSCLK16 0x0002
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#define TIMER_REASON_TIN 0x0003
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#define TIMER_REASON_CLK32 0x0004
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#define TIMER_REASON_SYSCLK 0x0000
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#define TIMER_REASON_TIN 0x0001
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#define TIMER_REASON_CLK32 0x0002
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//chip names
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enum{
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@@ -67,6 +65,7 @@ typedef struct{
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extern chip_t chips[];
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extern int32_t pllWakeWait;
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extern uint32_t clk32Counter;
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extern double pctlrCpuClockDivider;
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extern double timerCycleCounter[];
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extern uint16_t timerStatusReadAcknowledge[];
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extern uint32_t interruptEdgeTriggered;
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@@ -82,7 +81,8 @@ extern uint8_t pwm1ReadPosition;
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extern uint8_t pwm1WritePosition;
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//timing
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void clk32();//also checks all interrupts
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void clk32();
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void sysclks(double value);
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//CPU
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bool pllIsOn();
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@@ -230,7 +230,7 @@ static inline void setPllfsr(uint16_t value){
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if(!(oldPllfsr & 0x4000)){
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//frequency protect bit not set
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registerArrayWrite16(PLLFSR, (value & 0x4FFF) | (oldPllfsr & 0x8000));//preserve CLK32 bit
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recalculateCpuSpeed();
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palmSysclksPerClk32 = sysclksPerClk32();
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}
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}
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@@ -1,7 +1,139 @@
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static void timer1(uint8_t reason, double sysclks);
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static void timer2(uint8_t reason, double sysclks)
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static void timer2(uint8_t reason, double sysclks);
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static inline double dmaclksPerClk32(){
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static void timer1(uint8_t reason, double sysclks){
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uint16_t timer1Control = registerArrayRead16(TCTL1);
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uint16_t timer1Compare = registerArrayRead16(TCMP1);
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double timer1OldCount = timerCycleCounter[0];
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double timer1Prescaler = (registerArrayRead16(TPRER1) & 0x00FF) + 1;
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bool timer1Enabled = timer1Control & 0x0001;
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if(timer1Enabled){
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switch((timer1Control & 0x000E) >> 1){
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case 0x0000://stop counter
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//do nothing
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return;
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case 0x0001://SYSCLK / timer prescaler
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if(reason != TIMER_REASON_SYSCLK)
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return;
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timerCycleCounter[0] += sysclks / timer1Prescaler;
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break;
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case 0x0002://SYSCLK / 16 / timer prescaler
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if(reason != TIMER_REASON_SYSCLK)
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return;
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timerCycleCounter[0] += sysclks / 16.0 / timer1Prescaler;
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break;
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case 0x0003://TIN/TOUT pin / timer prescaler, the other timer can be attached to TIN/TOUT
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if(reason != TIMER_REASON_TIN)
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return;
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timerCycleCounter[0] += 1.0 / timer1Prescaler;
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break;
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default://CLK32 / timer prescaler
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if(reason != TIMER_REASON_CLK32)
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return;
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timerCycleCounter[0] += 1.0 / timer1Prescaler;
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break;
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}
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if(timer1OldCount < timer1Compare && timerCycleCounter[0] >= timer1Compare){
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//the comparison against the old value is to prevent an interrupt on every increment in free running mode
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//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
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uint8_t pcrTinToutConfig = registerArrayRead8(PCR) & 0x03;//TIN/TOUT seems not to be physicaly connected but cascaded timers still need to be supported
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//interrupt enabled
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if(timer1Control & 0x0010)
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setIprIsrBit(INT_TMR1);
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//set timer triggered bit
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registerArrayWrite16(TSTAT1, registerArrayRead16(TSTAT1) | 0x0001);
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timerStatusReadAcknowledge[0] &= 0xFFFE;//lock bit until next read
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//increment other timer if enabled
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if(pcrTinToutConfig == 0x03)
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timer2(TIMER_REASON_TIN, 0);
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//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
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if(!(timer1Control & 0x0100))
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timerCycleCounter[0] -= timer1Compare;
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}
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if(timerCycleCounter[0] > 0xFFFF)
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timerCycleCounter[0] -= 0xFFFF;
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registerArrayWrite16(TCN1, (uint16_t)timerCycleCounter[0]);
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}
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}
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static void timer2(uint8_t reason, double sysclks){
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uint16_t timer2Control = registerArrayRead16(TCTL2);
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uint16_t timer2Compare = registerArrayRead16(TCMP2);
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double timer2OldCount = timerCycleCounter[1];
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double timer2Prescaler = (registerArrayRead16(TPRER2) & 0x00FF) + 1;
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bool timer2Enabled = timer2Control & 0x0001;
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if(timer2Enabled){
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switch((timer2Control & 0x000E) >> 1){
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case 0x0000://stop counter
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//do nothing
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return;
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case 0x0001://SYSCLK / timer prescaler
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if(reason != TIMER_REASON_SYSCLK)
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return;
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timerCycleCounter[1] += sysclks / timer2Prescaler;
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break;
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case 0x0002://SYSCLK / 16 / timer prescaler
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if(reason != TIMER_REASON_SYSCLK)
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return;
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timerCycleCounter[1] += sysclks / 16.0 / timer2Prescaler;
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break;
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case 0x0003://TIN/TOUT pin / timer prescaler, the other timer can be attached to TIN/TOUT
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if(reason != TIMER_REASON_TIN)
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return;
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timerCycleCounter[1] += 1.0 / timer2Prescaler;
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break;
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default://CLK32 / timer prescaler
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if(reason != TIMER_REASON_CLK32)
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return;
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timerCycleCounter[1] += 1.0 / timer2Prescaler;
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break;
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}
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if(timer2OldCount < timer2Compare && timerCycleCounter[1] >= timer2Compare){
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//the comparison against the old value is to prevent an interrupt on every increment in free running mode
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//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
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uint8_t pcrTinToutConfig = registerArrayRead8(PCR) & 0x03;//TIN/TOUT seems not to be physicaly connected but cascaded timers still need to be supported
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//interrupt enabled
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if(timer2Control & 0x0010)
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setIprIsrBit(INT_TMR2);
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//set timer triggered bit
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registerArrayWrite16(TSTAT2, registerArrayRead16(TSTAT2) | 0x0001);
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timerStatusReadAcknowledge[1] &= 0xFFFE;//lock bit until next read
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//increment other timer if enabled
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if(pcrTinToutConfig == 0x02)
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timer1(TIMER_REASON_TIN, 0);
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//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
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if(!(timer2Control & 0x0100))
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timerCycleCounter[1] -= timer2Compare;
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}
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if(timerCycleCounter[1] > 0xFFFF)
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timerCycleCounter[1] -= 0xFFFF;
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registerArrayWrite16(TCN2, (uint16_t)timerCycleCounter[1]);
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}
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}
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static double dmaclksPerClk32(){
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double dmaclks;
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if(pllIsOn()){
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@@ -26,7 +158,7 @@ static inline double dmaclksPerClk32(){
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return dmaclks;
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}
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static inline double sysclksPerClk32(){
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static double sysclksPerClk32(){
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uint8_t sysclkSelect = registerArrayRead16(PLLCR) >> 8 & 0x0003;
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//> 4 means run at full speed, no divider
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@@ -81,265 +213,6 @@ static inline void rtiInterruptClk32(){
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}
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}
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static void timer1(uint8_t reason, double sysclks){
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uint16_t timer1Control = registerArrayRead16(TCTL1);
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uint16_t timer1Compare = registerArrayRead16(TCMP1);
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double timer1OldCount = timerCycleCounter[0];
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double timer1Prescaler = (registerArrayRead16(TPRER1) & 0x00FF) + 1;
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bool timer1Enabled = timer1Control & 0x0001;
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if(timer1Enabled){
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uint8_t timer1Source = (timer1Control & 0x000E) >> 1;
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//all CLK32 modes compare to 0x0004
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if(timer1Source > 0x0004)
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timer1Source = TIMER_REASON_CLK32;
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if(timer1Source != reason)
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return;
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switch(timer1Source){
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case TIMER_REASON_STOP://stop counter
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//do nothing
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return;
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case TIMER_REASON_SYSCLK://SYSCLK / timer prescaler
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timerCycleCounter[0] += sysclks / timer1Prescaler;
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break;
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case TIMER_REASON_SYSCLK16://SYSCLK / 16 / timer prescaler
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timerCycleCounter[0] += sysclks / 16.0 / timer1Prescaler;
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break;
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case TIMER_REASON_TIN://TIN/TOUT pin / timer prescaler, the other timer can be attached to TIN/TOUT
|
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case TIMER_REASON_CLK32://CLK32 / timer prescaler
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timerCycleCounter[0] += 1.0 / timer1Prescaler;
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break;
|
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}
|
||||
|
||||
if(timer1OldCount < timer1Compare && timerCycleCounter[0] >= timer1Compare){
|
||||
//the comparison against the old value is to prevent an interrupt on every increment in free running mode
|
||||
//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
|
||||
uint8_t pcrTinToutConfig = registerArrayRead8(PCR) & 0x03;//TIN/TOUT seems not to be physicaly connected but cascaded timers still need to be supported
|
||||
|
||||
//interrupt enabled
|
||||
if(timer1Control & 0x0010)
|
||||
setIprIsrBit(INT_TMR1);
|
||||
|
||||
//set timer triggered bit
|
||||
registerArrayWrite16(TSTAT1, registerArrayRead16(TSTAT1) | 0x0001);
|
||||
timerStatusReadAcknowledge[0] &= 0xFFFE;//lock bit until next read
|
||||
|
||||
if(pcrTinToutConfig == 0x03)
|
||||
timer2(TIMER_REASON_TIN, 0);
|
||||
|
||||
//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
|
||||
if(!(timer1Control & 0x0100))
|
||||
timerCycleCounter[0] -= timer1Compare;
|
||||
}
|
||||
|
||||
if(timerCycleCounter[0] > 0xFFFF)
|
||||
timerCycleCounter[0] -= 0xFFFF;
|
||||
registerArrayWrite16(TCN1, (uint16_t)timerCycleCounter[0]);
|
||||
}
|
||||
}
|
||||
|
||||
static void timer2(uint8_t reason, double sysclks){
|
||||
uint16_t timer2Control = registerArrayRead16(TCTL2);
|
||||
uint16_t timer2Compare = registerArrayRead16(TCMP2);
|
||||
double timer2OldCount = timerCycleCounter[1];
|
||||
double timer2Prescaler = (registerArrayRead16(TPRER2) & 0x00FF) + 1;
|
||||
bool timer2Enabled = timer2Control & 0x0001;
|
||||
|
||||
if(timer2Enabled){
|
||||
uint8_t timer2Source = (timer2Control & 0x000E) >> 1;
|
||||
|
||||
//all CLK32 modes compare to 0x0004
|
||||
if(timer2Source > 0x0004)
|
||||
timer2Source = 0x0004;
|
||||
|
||||
if(timer2Source != reason)
|
||||
return;
|
||||
|
||||
switch(timer2Source){
|
||||
case TIMER_REASON_STOP://stop counter
|
||||
//do nothing
|
||||
return;
|
||||
|
||||
case TIMER_REASON_SYSCLK://SYSCLK / timer prescaler
|
||||
timerCycleCounter[1] += sysclks / timer2Prescaler;
|
||||
break;
|
||||
|
||||
case TIMER_REASON_SYSCLK16://SYSCLK / 16 / timer prescaler
|
||||
timerCycleCounter[1] += sysclks / 16.0 / timer2Prescaler;
|
||||
break;
|
||||
|
||||
case TIMER_REASON_TIN://TIN/TOUT pin / timer prescaler, the other timer can be attached to TIN/TOUT
|
||||
case TIMER_REASON_CLK32://CLK32 / timer prescaler
|
||||
timerCycleCounter[1] += 1.0 / timer2Prescaler;
|
||||
break;
|
||||
}
|
||||
|
||||
if(timer2OldCount < timer2Compare && timerCycleCounter[1] >= timer2Compare){
|
||||
//the comparison against the old value is to prevent an interrupt on every increment in free running mode
|
||||
//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
|
||||
uint8_t pcrTinToutConfig = registerArrayRead8(PCR) & 0x03;//TIN/TOUT seems not to be physicaly connected but cascaded timers still need to be supported
|
||||
|
||||
//interrupt enabled
|
||||
if(timer2Control & 0x0010)
|
||||
setIprIsrBit(INT_TMR2);
|
||||
|
||||
//set timer triggered bit
|
||||
registerArrayWrite16(TSTAT2, registerArrayRead16(TSTAT2) | 0x0001);
|
||||
timerStatusReadAcknowledge[1] &= 0xFFFE;//lock bit until next read
|
||||
|
||||
if(pcrTinToutConfig == 0x02)
|
||||
timer1(TIMER_REASON_TIN, 0);
|
||||
|
||||
//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
|
||||
if(!(timer2Control & 0x0100))
|
||||
timerCycleCounter[1] -= timer2Compare;
|
||||
}
|
||||
|
||||
if(timerCycleCounter[1] > 0xFFFF)
|
||||
timerCycleCounter[1] -= 0xFFFF;
|
||||
registerArrayWrite16(TCN2, (uint16_t)timerCycleCounter[1]);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void timer12Clk32(){
|
||||
//this function is part of clk32();
|
||||
uint16_t timer1Control = registerArrayRead16(TCTL1);
|
||||
uint16_t timer1Compare = registerArrayRead16(TCMP1);
|
||||
double timer1OldCount = timerCycleCounter[0];
|
||||
double timer1Prescaler = (registerArrayRead16(TPRER1) & 0x00FF) + 1;
|
||||
bool timer1Enabled = timer1Control & 0x0001;
|
||||
uint16_t timer2Control = registerArrayRead16(TCTL2);
|
||||
uint16_t timer2Compare = registerArrayRead16(TCMP2);
|
||||
double timer2OldCount = timerCycleCounter[0];
|
||||
double timer2Prescaler = (registerArrayRead16(TPRER2) & 0x00FF) + 1;
|
||||
bool timer2Enabled = timer2Control & 0x0001;
|
||||
uint8_t pcrTinToutConfig = registerArrayRead8(PCR) & 0x03;//TIN/TOUT seems not to be physicaly connected but cascaded timers still need to be supported
|
||||
double sysclks = sysclksPerClk32();
|
||||
|
||||
if(timer1Enabled && pcrTinToutConfig != 0x02){
|
||||
switch((timer1Control & 0x000E) >> 1){
|
||||
case 0x0000://stop counter
|
||||
//do nothing
|
||||
break;
|
||||
|
||||
case 0x0001://SYSCLK / timer prescaler
|
||||
timerCycleCounter[0] += sysclks / timer1Prescaler;
|
||||
break;
|
||||
|
||||
case 0x0002://SYSCLK / 16 / timer prescaler
|
||||
timerCycleCounter[0] += sysclks / 16.0 / timer1Prescaler;
|
||||
break;
|
||||
|
||||
case 0x0003://TIN/TOUT pin / timer prescaler, nothing is attached to TIN/TOUT
|
||||
//do nothing
|
||||
break;
|
||||
|
||||
default://CLK32 / timer prescaler
|
||||
timerCycleCounter[0] += 1.0 / timer1Prescaler;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(timer2Enabled && pcrTinToutConfig != 0x03){
|
||||
switch((timer2Control & 0x000E) >> 1){
|
||||
case 0x0000://stop counter
|
||||
//do nothing
|
||||
break;
|
||||
|
||||
case 0x0001://SYSCLK / timer prescaler
|
||||
timerCycleCounter[1] += sysclks / timer2Prescaler;
|
||||
break;
|
||||
|
||||
case 0x0002://SYSCLK / 16 / timer prescaler
|
||||
timerCycleCounter[1] += sysclks / 16.0 / timer2Prescaler;
|
||||
break;
|
||||
|
||||
case 0x0003://TIN/TOUT pin / timer prescaler, nothing is attached to TIN/TOUT
|
||||
//do nothing
|
||||
break;
|
||||
|
||||
default://CLK32 / timer prescaler
|
||||
timerCycleCounter[1] += 1.0 / timer2Prescaler;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(timer1Enabled && timer1OldCount < timer1Compare && timerCycleCounter[0] >= timer1Compare){
|
||||
//the comparison against the old value is to prevent an interrupt on every increment in free running mode
|
||||
//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
|
||||
|
||||
//interrupt enabled
|
||||
if(timer1Control & 0x0010)
|
||||
setIprIsrBit(INT_TMR1);
|
||||
|
||||
//set timer triggered bit
|
||||
registerArrayWrite16(TSTAT1, registerArrayRead16(TSTAT1) | 0x0001);
|
||||
timerStatusReadAcknowledge[0] &= 0xFFFE;//lock bit until next read
|
||||
|
||||
//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
|
||||
if(!(timer1Control & 0x0100))
|
||||
timerCycleCounter[0] -= timer1Compare;
|
||||
}
|
||||
|
||||
if(timer2Enabled && timer2OldCount < timer2Compare && timerCycleCounter[1] >= timer2Compare){
|
||||
//the comparison against the old value is to prevent an interrupt on every increment in free running mode
|
||||
//the timer is not cycle accurate and may not hit the value in the compare register perfectly so check if it would have during in the emulated time
|
||||
|
||||
//interrupt enabled
|
||||
if(timer2Control & 0x0010)
|
||||
setIprIsrBit(INT_TMR2);
|
||||
|
||||
//set timer triggered bit
|
||||
registerArrayWrite16(TSTAT2, registerArrayRead16(TSTAT2) | 0x0001);
|
||||
timerStatusReadAcknowledge[1] &= 0xFFFE;//lock bit until next read
|
||||
|
||||
//not free running, reset to 0, to prevent loss of ticks after compare event just subtract timerXCompare
|
||||
if(!(timer2Control & 0x0100))
|
||||
timerCycleCounter[1] -= timer2Compare;
|
||||
}
|
||||
|
||||
if(timer1Enabled && timer2Enabled){
|
||||
switch(pcrTinToutConfig){
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
//do nothing
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
//PCR T field, 0x02 = Timer 2 OUT -> Timer 1 IN; TIN -> Timer 2 (DIR6 = 0), or TOUT -> Timer 1 (DIR6 = 1).
|
||||
if(timerCycleCounter[1] > 0xFFFF)
|
||||
timerCycleCounter[0] += 1.0;
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
//PCR T field, 0x03 = Timer 1 OUT -> Timer 2 IN; TIN -> Timer 1 (DIR6 = 0), or TOUT -> Timer 2 (DIR6 = 1)
|
||||
if(timerCycleCounter[0] > 0xFFFF)
|
||||
timerCycleCounter[1] += 1.0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//if timer chaining causes an interrupt the actual interrupt takes place the next time this function is called
|
||||
|
||||
if(timer1Enabled){
|
||||
if(timerCycleCounter[0] > 0xFFFF)
|
||||
timerCycleCounter[0] -= 0xFFFF;
|
||||
registerArrayWrite16(TCN1, (uint16_t)timerCycleCounter[0]);
|
||||
}
|
||||
|
||||
if(timer2Enabled){
|
||||
if(timerCycleCounter[1] > 0xFFFF)
|
||||
timerCycleCounter[1] -= 0xFFFF;
|
||||
registerArrayWrite16(TCN2, (uint16_t)timerCycleCounter[1]);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void watchdogSecondTickClk32(){
|
||||
//this function is part of clk32();
|
||||
uint16_t watchdogState = registerArrayRead16(WATCHDOG);
|
||||
@@ -447,7 +320,8 @@ void clk32(){
|
||||
if(registerArrayRead16(RTCCTL) & 0x0080 || registerArrayRead16(WATCHDOG) & 0x01)
|
||||
rtiInterruptClk32();
|
||||
|
||||
timer12Clk32();
|
||||
timer1(TIMER_REASON_CLK32, 0);
|
||||
timer2(TIMER_REASON_CLK32, 0);
|
||||
samplePwmXClk32();
|
||||
|
||||
//PLLCR wake select wait
|
||||
@@ -455,7 +329,7 @@ void clk32(){
|
||||
if(pllWakeWait == 0){
|
||||
//reenable PLL and CPU
|
||||
registerArrayWrite16(PLLCR, registerArrayRead16(PLLCR) & 0xFFF7);
|
||||
recalculateCpuSpeed();
|
||||
palmSysclksPerClk32 = sysclksPerClk32();
|
||||
debugLog("PLL reenabled, CPU is on!\n");
|
||||
}
|
||||
pllWakeWait--;
|
||||
@@ -463,3 +337,8 @@ void clk32(){
|
||||
|
||||
checkInterrupts();
|
||||
}
|
||||
|
||||
void sysclks(double count){
|
||||
timer1(TIMER_REASON_SYSCLK, count);
|
||||
timer2(TIMER_REASON_SYSCLK, count);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user