mirror of
https://github.com/decaf-emu/decaf-emu.git
synced 2026-02-04 05:34:48 +00:00
Add hardware test tools.
This commit is contained in:
James Benton
3
.gitmodules
vendored
3
.gitmodules
vendored
@@ -22,3 +22,6 @@
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[submodule "libraries/gsl"]
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path = libraries/gsl
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164
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164
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39
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39
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Normal file
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156
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22
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22
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@@ -0,0 +1,22 @@
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1
libraries/ovsocket
Submodule
1
libraries/ovsocket
Submodule
Submodule libraries/ovsocket added at 863b8892dd
280
src/hardwaretests.cpp
Executable file
280
src/hardwaretests.cpp
Executable file
@@ -0,0 +1,280 @@
|
||||
#include <cassert>
|
||||
#include <experimental/filesystem>
|
||||
#include <fstream>
|
||||
#include "cpu/cpu.h"
|
||||
#include "cpu/disassembler.h"
|
||||
#include "hardwaretests.h"
|
||||
#include "mem/mem.h"
|
||||
#include "utils/floatutils.h"
|
||||
#include "utils/log.h"
|
||||
#include "utils/strutils.h"
|
||||
|
||||
namespace fs = std::experimental::filesystem;
|
||||
static const auto TEST_FPSCR = false;
|
||||
|
||||
namespace hwtest
|
||||
{
|
||||
|
||||
static void
|
||||
printTestField(Field field, Instruction instr, RegisterState *input, RegisterState *output, ThreadState *state)
|
||||
{
|
||||
auto printGPR = [&](uint32_t reg) {
|
||||
assert(reg >= GPR_BASE);
|
||||
|
||||
gLog->debug("r{:02d} = {:08X} {:08X} {:08X}", reg,
|
||||
input->gpr[reg - GPR_BASE],
|
||||
output->gpr[reg - GPR_BASE],
|
||||
state->gpr[reg]);
|
||||
};
|
||||
|
||||
auto printFPR = [&](uint32_t reg) {
|
||||
assert(reg >= FPR_BASE);
|
||||
|
||||
gLog->debug("f{:02d} = {:16e} {:16e} {:16e}", reg,
|
||||
input->fr[reg - FPR_BASE],
|
||||
output->fr[reg - FPR_BASE],
|
||||
state->fpr[reg].paired0);
|
||||
|
||||
gLog->debug(" {:16X} {:16X} {:16X}",
|
||||
bit_cast<uint64_t>(input->fr[reg - FPR_BASE]),
|
||||
bit_cast<uint64_t>(output->fr[reg - FPR_BASE]),
|
||||
bit_cast<uint64_t>(state->fpr[reg].paired0));
|
||||
};
|
||||
|
||||
switch (field) {
|
||||
case Field::rA:
|
||||
printGPR(instr.rA);
|
||||
break;
|
||||
case Field::rB:
|
||||
printGPR(instr.rB);
|
||||
break;
|
||||
case Field::rD:
|
||||
printGPR(instr.rS);
|
||||
break;
|
||||
case Field::rS:
|
||||
printGPR(instr.rS);
|
||||
break;
|
||||
case Field::frA:
|
||||
printFPR(instr.frA);
|
||||
break;
|
||||
case Field::frB:
|
||||
printFPR(instr.frB);
|
||||
break;
|
||||
case Field::frC:
|
||||
printFPR(instr.frC);
|
||||
break;
|
||||
case Field::frD:
|
||||
printFPR(instr.frD);
|
||||
break;
|
||||
case Field::frS:
|
||||
printFPR(instr.frS);
|
||||
break;
|
||||
case Field::XERC:
|
||||
gLog->debug("xer.ca = {:08X} {:08X} {:08X}", input->xer.ca, output->xer.ca, state->xer.ca);
|
||||
break;
|
||||
case Field::XERSO:
|
||||
gLog->debug("xer.so = {:08X} {:08X} {:08X}", input->xer.so, output->xer.so, state->xer.so);
|
||||
break;
|
||||
case Field::FPSCR:
|
||||
//gLog->debug("fpscr = {:08X} {:08x} {:08X}", input->fpscr.value, output->fpscr.value, state->fpscr.value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#define CompareFPSCRField(field) \
|
||||
if (result.field != expected.field) { \
|
||||
gLog->debug("fpscr." #field " = {} {} {}", input.field, expected.field, result.field); \
|
||||
failed = true; \
|
||||
}
|
||||
|
||||
// Compare all individual fields in fpscr
|
||||
static bool
|
||||
compareFPSCR(fpscr_t input, fpscr_t expected, fpscr_t result)
|
||||
{
|
||||
auto failed = false;
|
||||
CompareFPSCRField(rn);
|
||||
CompareFPSCRField(ni);
|
||||
CompareFPSCRField(xe);
|
||||
CompareFPSCRField(ze);
|
||||
CompareFPSCRField(ue);
|
||||
CompareFPSCRField(oe);
|
||||
CompareFPSCRField(ve);
|
||||
CompareFPSCRField(vxcvi);
|
||||
CompareFPSCRField(vxsqrt);
|
||||
CompareFPSCRField(vxsoft);
|
||||
CompareFPSCRField(fprf);
|
||||
CompareFPSCRField(fi);
|
||||
CompareFPSCRField(fr);
|
||||
CompareFPSCRField(vxvc);
|
||||
CompareFPSCRField(vximz);
|
||||
CompareFPSCRField(vxzdz);
|
||||
CompareFPSCRField(vxidi);
|
||||
CompareFPSCRField(vxisi);
|
||||
CompareFPSCRField(vxsnan);
|
||||
CompareFPSCRField(xx);
|
||||
CompareFPSCRField(zx);
|
||||
CompareFPSCRField(ux);
|
||||
CompareFPSCRField(ox);
|
||||
CompareFPSCRField(vx);
|
||||
CompareFPSCRField(fex);
|
||||
CompareFPSCRField(fx);
|
||||
return failed;
|
||||
}
|
||||
|
||||
static const std::vector<std::string>
|
||||
excludeTests = {
|
||||
"fmadds",
|
||||
"fmsub", "fmsubs",
|
||||
"fnmadd", "fnmadds",
|
||||
"fnmsub", "fnmsubs",
|
||||
};
|
||||
|
||||
bool runTests()
|
||||
{
|
||||
uint32_t testsFailed = 0, testsPassed = 0;
|
||||
uint32_t baseAddress = 0x02000000;
|
||||
|
||||
// Allocate some memory to write code to
|
||||
if (!mem::alloc(baseAddress, 4096)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
Instruction bclr = gInstructionTable.encode(InstructionID::bclr);
|
||||
bclr.bo = 0x1f;
|
||||
mem::write(baseAddress + 4, bclr.value);
|
||||
|
||||
// Read all tests
|
||||
for (auto &entry : fs::directory_iterator("tests/cpu/wiiu")) {
|
||||
std::ifstream file(entry.path().string(), std::ifstream::in | std::ifstream::binary);
|
||||
cereal::BinaryInputArchive cerealInput(file);
|
||||
TestFile testFile;
|
||||
|
||||
// Parse test file with cereal
|
||||
testFile.name = entry.path().filename().string();
|
||||
cerealInput(testFile);
|
||||
|
||||
// Skip excluded tests
|
||||
if (std::find(excludeTests.begin(), excludeTests.end(), testFile.name) != excludeTests.end()) {
|
||||
gLog->info("Skipping {}", testFile.name);
|
||||
continue;
|
||||
}
|
||||
|
||||
// Run tests
|
||||
gLog->info("Checking {}", testFile.name);
|
||||
|
||||
for (auto &test : testFile.tests) {
|
||||
ThreadState state;
|
||||
bool failed = false;
|
||||
|
||||
// Setup thread state from test input
|
||||
memset(&state, 0, sizeof(ThreadState));
|
||||
state.cia = 0;
|
||||
state.nia = baseAddress;
|
||||
state.xer = test.input.xer;
|
||||
state.cr = test.input.cr;
|
||||
state.fpscr = test.input.fpscr;
|
||||
state.ctr = test.input.ctr;
|
||||
|
||||
for (auto i = 0; i < 4; ++i) {
|
||||
state.gpr[i + 3] = test.input.gpr[i];
|
||||
state.fpr[i + 1].paired0 = test.input.fr[i];
|
||||
}
|
||||
|
||||
// Execute test
|
||||
mem::write(baseAddress, test.instr.value);
|
||||
cpu::executeSub(&state);
|
||||
|
||||
// Check XER (all bits)
|
||||
if (state.xer.value != test.output.xer.value) {
|
||||
gLog->error("Test failed, xer expected {:08X} found {:08X}", test.output.xer.value, state.xer.value);
|
||||
failed = true;
|
||||
}
|
||||
|
||||
// Check Condition Register (all bits)
|
||||
if (state.cr.value != test.output.cr.value) {
|
||||
gLog->error("Test failed, cr expected {:08X} found {:08X}", test.output.cr.value, state.cr.value);
|
||||
failed = true;
|
||||
}
|
||||
|
||||
// Check FPSCR (all bits)
|
||||
if (TEST_FPSCR) {
|
||||
if (state.fpscr.value != test.output.fpscr.value) {
|
||||
gLog->error("Test failed, fpscr {:08X} found {:08X}", test.output.fpscr.value, state.fpscr.value);
|
||||
failed = true;
|
||||
}
|
||||
}
|
||||
|
||||
// Check CTR
|
||||
if (state.ctr != test.output.ctr) {
|
||||
gLog->error("Test failed, ctr expected {:08X} found {:08X}", test.output.ctr, state.ctr);
|
||||
failed = true;
|
||||
}
|
||||
|
||||
// Check all GPR
|
||||
for (auto i = 0; i < 4; ++i) {
|
||||
auto reg = i + hwtest::GPR_BASE;
|
||||
auto value = state.gpr[reg];
|
||||
auto expected = test.output.gpr[i];
|
||||
|
||||
if (value != expected) {
|
||||
gLog->error("Test failed, r{} expected {:08X} found {:08X}", reg, expected, value);
|
||||
failed = true;
|
||||
}
|
||||
}
|
||||
|
||||
// Check all FPR
|
||||
for (auto i = 0; i < 4; ++i) {
|
||||
auto reg = i + hwtest::FPR_BASE;
|
||||
auto value = state.fpr[reg].paired0;
|
||||
auto expected = test.output.fr[i];
|
||||
|
||||
if (!is_nan(value) && !is_nan(test.output.fr[i]) && !is_infinity(value) && !is_infinity(expected)) {
|
||||
double dval = value / expected;
|
||||
|
||||
if (dval < 0.999 || dval > 1.001) {
|
||||
gLog->error("Test failed, f{} expected {:16f} found {:16f}", reg, expected, value);
|
||||
failed = true;
|
||||
}
|
||||
} else {
|
||||
if (bit_cast<uint64_t>(value) != bit_cast<uint64_t>(expected)) {
|
||||
gLog->error("Test failed, f{} expected {:16X} found {:16X}", reg, bit_cast<uint64_t>(expected), bit_cast<uint64_t>(value));
|
||||
failed = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (failed) {
|
||||
Disassembly dis;
|
||||
|
||||
// Print disassembly
|
||||
gDisassembler.disassemble(test.instr, dis, baseAddress);
|
||||
gLog->debug(dis.text);
|
||||
|
||||
// Print all test fields
|
||||
gLog->debug("{:08x} Input Hardware Interp", test.instr.value);
|
||||
|
||||
for (auto field : dis.instruction->read) {
|
||||
printTestField(field, test.instr, &test.input, &test.output, &state);
|
||||
}
|
||||
|
||||
for (auto field : dis.instruction->write) {
|
||||
printTestField(field, test.instr, &test.input, &test.output, &state);
|
||||
}
|
||||
|
||||
for (auto field : dis.instruction->flags) {
|
||||
printTestField(field, test.instr, &test.input, &test.output, &state);
|
||||
}
|
||||
|
||||
gLog->debug("");
|
||||
++testsFailed;
|
||||
} else {
|
||||
++testsPassed;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
gLog->info("Passed: {}, Failed: {}", testsPassed, testsFailed);
|
||||
return true;
|
||||
}
|
||||
|
||||
} // namespace hwtest
|
||||
73
src/hardwaretests.h
Executable file
73
src/hardwaretests.h
Executable file
@@ -0,0 +1,73 @@
|
||||
#pragma once
|
||||
#include <cereal/types/vector.hpp>
|
||||
#include <cereal/archives/binary.hpp>
|
||||
#include <vector>
|
||||
#include "cpu/state.h"
|
||||
#include "cpu/instructiondata.h"
|
||||
#include "utils/be_val.h"
|
||||
|
||||
namespace hwtest
|
||||
{
|
||||
|
||||
static const auto GPR_BASE = 3;
|
||||
static const auto FPR_BASE = 1;
|
||||
static const auto CRF_BASE = 2;
|
||||
static const auto CRB_BASE = 8;
|
||||
|
||||
struct RegisterState
|
||||
{
|
||||
xer_t xer;
|
||||
cr_t cr;
|
||||
fpscr_t fpscr;
|
||||
uint32_t ctr;
|
||||
uint32_t gpr[4];
|
||||
double fr[4];
|
||||
|
||||
template <class Archive>
|
||||
void serialize(Archive & ar)
|
||||
{
|
||||
ar(xer.value);
|
||||
ar(cr.value);
|
||||
ar(fpscr.value);
|
||||
ar(ctr);
|
||||
|
||||
for (auto i = 0; i < 4; ++i) {
|
||||
ar(gpr[i]);
|
||||
}
|
||||
|
||||
for (auto i = 0; i < 4; ++i) {
|
||||
ar(fr[i]);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
struct TestData
|
||||
{
|
||||
Instruction instr;
|
||||
RegisterState input;
|
||||
RegisterState output;
|
||||
|
||||
template <class Archive>
|
||||
void serialize(Archive & ar)
|
||||
{
|
||||
ar(instr.value);
|
||||
ar(input);
|
||||
ar(output);
|
||||
}
|
||||
};
|
||||
|
||||
struct TestFile
|
||||
{
|
||||
std::string name;
|
||||
std::vector<TestData> tests;
|
||||
|
||||
template <class Archive>
|
||||
void serialize(Archive & ar)
|
||||
{
|
||||
ar(tests);
|
||||
}
|
||||
};
|
||||
|
||||
bool runTests();
|
||||
|
||||
} // namespace hwtest
|
||||
@@ -6,6 +6,7 @@
|
||||
#include "debugger.h"
|
||||
#include "fuzztests.h"
|
||||
#include "filesystem/filesystem.h"
|
||||
#include "hardwaretests.h"
|
||||
#include "processor.h"
|
||||
#include "loader.h"
|
||||
#include "mem/mem.h"
|
||||
@@ -50,6 +51,7 @@ Usage:
|
||||
wiiu play [--jit | --jitdebug] [--logfile] [--log-async] [--log-level=<log-level>] <game directory>
|
||||
wiiu test [--jit | --jitdebug] [--logfile] [--log-async] [--log-level=<log-level>] [--as=<ppcas>] <test directory>
|
||||
wiiu fuzz
|
||||
wiiu hwtest [--logfile]
|
||||
wiiu (-h | --help)
|
||||
wiiu --version
|
||||
|
||||
@@ -95,6 +97,8 @@ int main(int argc, char **argv)
|
||||
file = getGameName(args["<game directory>"].asString());
|
||||
} else if (args["test"].asBool()) {
|
||||
file = "tests";
|
||||
} else if (args["hwtest"].asBool()) {
|
||||
file = "hwtest";
|
||||
}
|
||||
|
||||
sinks.push_back(std::make_shared<spdlog::sinks::daily_file_sink_st>(file, "txt", 23, 59, true));
|
||||
@@ -123,6 +127,9 @@ int main(int argc, char **argv)
|
||||
} else if (args["fuzz"].asBool()) {
|
||||
gLog->set_pattern("%v");
|
||||
result = fuzzTest();
|
||||
} else if (args["hwtest"].asBool()) {
|
||||
gLog->set_pattern("%v");
|
||||
result = hwtest::runTests();
|
||||
} else if (args["test"].asBool()) {
|
||||
gLog->set_pattern("%v");
|
||||
result = test(args["--as"].asString(), args["<test directory>"].asString());
|
||||
|
||||
@@ -53,6 +53,17 @@ join_string(IteratorType begin, IteratorType end, char delim, std::string &out)
|
||||
}
|
||||
}
|
||||
|
||||
// Returns true if source begins with prefix
|
||||
static inline bool
|
||||
begins_with(const std::string &source, const std::string &prefix)
|
||||
{
|
||||
if (prefix.size() > source.size()) {
|
||||
return false;
|
||||
} else {
|
||||
return std::equal(prefix.begin(), prefix.end(), source.begin());
|
||||
}
|
||||
}
|
||||
|
||||
// Returns true if source ends with suffix
|
||||
static inline bool
|
||||
ends_with(const std::string &source, const std::string &suffix)
|
||||
|
||||
428
tools/hardware-tests/generator.cpp
Executable file
428
tools/hardware-tests/generator.cpp
Executable file
@@ -0,0 +1,428 @@
|
||||
#define NOMINMAX
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
#include <spdlog/spdlog.h>
|
||||
#include "cpu/state.h"
|
||||
#include "cpu/instructiondata.h"
|
||||
#include "utils/be_val.h"
|
||||
#include "utils/bitutils.h"
|
||||
#include "hardwaretests.h"
|
||||
#include "generator_testlist.h"
|
||||
#include "generator_valuelist.h"
|
||||
|
||||
static void
|
||||
setCRB(hwtest::RegisterState &state, uint32_t bit, uint32_t value)
|
||||
{
|
||||
state.cr.value = set_bit_value(state.cr.value, 31 - bit, value);
|
||||
}
|
||||
|
||||
static void
|
||||
generateTests(InstructionData *data)
|
||||
{
|
||||
std::vector<size_t> indexCur, indexMax;
|
||||
std::vector<bool> flagSet;
|
||||
hwtest::TestFile testFile;
|
||||
auto complete = false;
|
||||
auto completeIndices = false;
|
||||
|
||||
for (auto i = 0; i < data->read.size(); ++i) {
|
||||
auto &field = data->read[i];
|
||||
indexCur.push_back(0);
|
||||
|
||||
switch (field) {
|
||||
case Field::rA:
|
||||
case Field::rB:
|
||||
case Field::rS:
|
||||
indexMax.push_back(gValuesGPR.size());
|
||||
break;
|
||||
case Field::frA:
|
||||
case Field::frB:
|
||||
case Field::frC:
|
||||
case Field::frS:
|
||||
indexMax.push_back(gValuesFPR.size());
|
||||
break;
|
||||
case Field::crbA:
|
||||
case Field::crbB:
|
||||
indexMax.push_back(gValuesCRB.size());
|
||||
break;
|
||||
case Field::simm:
|
||||
indexMax.push_back(gValuesSIMM.size());
|
||||
break;
|
||||
case Field::sh:
|
||||
indexMax.push_back(gValuesSH.size());
|
||||
break;
|
||||
case Field::mb:
|
||||
indexMax.push_back(gValuesMB.size());
|
||||
break;
|
||||
case Field::me:
|
||||
indexMax.push_back(gValuesME.size());
|
||||
break;
|
||||
case Field::uimm:
|
||||
indexMax.push_back(gValuesUIMM.size());
|
||||
break;
|
||||
case Field::XERC:
|
||||
indexMax.push_back(gValuesXERC.size());
|
||||
break;
|
||||
case Field::XERSO:
|
||||
indexMax.push_back(gValuesXERSO.size());
|
||||
break;
|
||||
default:
|
||||
assert(false);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto i = 0; i < data->flags.size(); ++i) {
|
||||
flagSet.push_back(false);
|
||||
}
|
||||
|
||||
while (!complete) {
|
||||
uint32_t gpr = 0, fpr = 0, crf = 0, crb = 0;
|
||||
hwtest::TestData test;
|
||||
memset(&test, 0, sizeof(hwtest::TestData));
|
||||
|
||||
test.instr = gInstructionTable.encode(data->id);
|
||||
|
||||
for (auto i = 0; i < data->read.size(); ++i) {
|
||||
auto index = indexCur[i];
|
||||
|
||||
// Generate read field values
|
||||
switch (data->read[i]) {
|
||||
case Field::rA:
|
||||
test.instr.rA = gpr + hwtest::GPR_BASE;
|
||||
test.input.gpr[gpr++] = gValuesGPR[index];
|
||||
break;
|
||||
case Field::rB:
|
||||
test.instr.rB = gpr + hwtest::GPR_BASE;
|
||||
test.input.gpr[gpr++] = gValuesGPR[index];
|
||||
break;
|
||||
case Field::rS:
|
||||
test.instr.rS = gpr + hwtest::GPR_BASE;
|
||||
test.input.gpr[gpr++] = gValuesGPR[index];
|
||||
break;
|
||||
case Field::frA:
|
||||
test.instr.frA = fpr + hwtest::FPR_BASE;
|
||||
test.input.fr[fpr++] = gValuesFPR[index];
|
||||
break;
|
||||
case Field::frB:
|
||||
test.instr.frB = fpr + hwtest::FPR_BASE;
|
||||
test.input.fr[fpr++] = gValuesFPR[index];
|
||||
break;
|
||||
case Field::frC:
|
||||
test.instr.frC = fpr + hwtest::FPR_BASE;
|
||||
test.input.fr[fpr++] = gValuesFPR[index];
|
||||
break;
|
||||
case Field::frS:
|
||||
test.instr.frS = fpr + hwtest::FPR_BASE;
|
||||
test.input.fr[fpr++] = gValuesFPR[index];
|
||||
break;
|
||||
case Field::crbA:
|
||||
test.instr.crbA = (crb++) + hwtest::CRB_BASE;
|
||||
setCRB(test.input, test.instr.crbA, gValuesCRB[index]);
|
||||
break;
|
||||
case Field::crbB:
|
||||
test.instr.crbB = (crb++) + hwtest::CRB_BASE;
|
||||
setCRB(test.input, test.instr.crbB, gValuesCRB[index]);
|
||||
break;
|
||||
case Field::simm:
|
||||
test.instr.simm = gValuesSIMM[index];
|
||||
break;
|
||||
case Field::sh:
|
||||
test.instr.sh = gValuesSH[index];
|
||||
break;
|
||||
case Field::mb:
|
||||
test.instr.mb = gValuesMB[index];
|
||||
break;
|
||||
case Field::me:
|
||||
test.instr.me = gValuesME[index];
|
||||
break;
|
||||
case Field::uimm:
|
||||
test.instr.uimm = gValuesUIMM[index];
|
||||
break;
|
||||
case Field::XERC:
|
||||
test.input.xer.ca = gValuesXERC[index];
|
||||
break;
|
||||
case Field::XERSO:
|
||||
test.input.xer.so = gValuesXERSO[index];
|
||||
break;
|
||||
default:
|
||||
assert(false);
|
||||
}
|
||||
}
|
||||
|
||||
// Generate write field values
|
||||
for (auto field : data->write) {
|
||||
switch (field) {
|
||||
case Field::rA:
|
||||
test.instr.rA = gpr + hwtest::GPR_BASE;
|
||||
gpr++;
|
||||
break;
|
||||
case Field::rD:
|
||||
test.instr.rD = gpr + hwtest::GPR_BASE;
|
||||
gpr++;
|
||||
break;
|
||||
case Field::frD:
|
||||
test.instr.frD = fpr + hwtest::FPR_BASE;
|
||||
fpr++;
|
||||
break;
|
||||
case Field::crfD:
|
||||
test.instr.crfD = crf + hwtest::CRF_BASE;
|
||||
crf++;
|
||||
break;
|
||||
case Field::crbD:
|
||||
test.instr.crbD = crb + hwtest::CRB_BASE;
|
||||
crb++;
|
||||
break;
|
||||
case Field::XERC:
|
||||
case Field::XERSO:
|
||||
case Field::FCRISI:
|
||||
case Field::FCRZDZ:
|
||||
case Field::FCRIDI:
|
||||
case Field::FCRSNAN:
|
||||
break;
|
||||
default:
|
||||
assert(false);
|
||||
}
|
||||
}
|
||||
|
||||
testFile.tests.emplace_back(test);
|
||||
|
||||
// Increase indices
|
||||
for (auto i = 0; i < indexCur.size(); ++i) {
|
||||
indexCur[i]++;
|
||||
|
||||
if (indexCur[i] < indexMax[i]) {
|
||||
break;
|
||||
} else if (indexCur[i] == indexMax[i]) {
|
||||
indexCur[i] = 0;
|
||||
|
||||
if (i == indexCur.size() - 1) {
|
||||
completeIndices = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (completeIndices) {
|
||||
if (flagSet.size() == 0) {
|
||||
complete = true;
|
||||
break;
|
||||
}
|
||||
|
||||
completeIndices = false;
|
||||
|
||||
// Do next flag!
|
||||
for (auto i = 0; i < flagSet.size(); ++i) {
|
||||
if (!flagSet[i]) {
|
||||
flagSet[i] = true;
|
||||
break;
|
||||
} else {
|
||||
flagSet[i] = false;
|
||||
|
||||
if (i == flagSet.size() - 1) {
|
||||
complete = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Save tests to file
|
||||
auto filename = std::string("tests/cpu/input/") + data->name;
|
||||
std::ofstream out { filename, std::ofstream::out | std::ofstream::binary };
|
||||
cereal::BinaryOutputArchive archive(out);
|
||||
archive(testFile);
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
gInstructionTable.initialise();
|
||||
|
||||
for (auto &group : gTestInstructions) {
|
||||
for (auto id : group) {
|
||||
auto data = gInstructionTable.find(id);
|
||||
generateTests(data);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Unimplemented instructions:
|
||||
|
||||
// Floating-Point Status and Control Register
|
||||
INS(mcrfs, (crfD), (crfS), (), (opcd == 63, xo1 == 64, !_9_10, !_14_15, !_16_20, !_31), "")
|
||||
INS(mffs, (frD), (), (rc), (opcd == 63, xo1 == 583, !_11_15, !_16_20), "")
|
||||
INS(mtfsf, (), (fm, frB), (rc), (opcd == 63, xo1 == 711, !_6, !_15), "")
|
||||
INS(mtfsfi, (crfD), (), (rc, imm), (opcd == 63, xo1 == 134, !_9_10, !_11_15, !_20), "")
|
||||
|
||||
// Integer Load
|
||||
INS(lbz, (rD), (rA, d), (), (opcd == 34), "Load Byte and Zero")
|
||||
INS(lbzu, (rD, rA), (rA, d), (), (opcd == 35), "Load Byte and Zero with Update")
|
||||
INS(lbzx, (rD), (rA, rB), (), (opcd == 31, xo1 == 87, !_31), "Load Byte and Zero Indexed")
|
||||
INS(lbzux, (rD, rA), (rA, rB), (), (opcd == 31, xo1 == 119, !_31), "Load Byte and Zero with Update Indexed")
|
||||
INS(lha, (rD), (rA, d), (), (opcd == 42), "Load Half Word Algebraic")
|
||||
INS(lhau, (rD, rA), (rA, d), (), (opcd == 43), "Load Half Word Algebraic with Update")
|
||||
INS(lhax, (rD), (rA, rB), (), (opcd == 31, xo1 == 343, !_31), "Load Half Word Algebraic Indexed")
|
||||
INS(lhaux, (rD, rA), (rA, rB), (), (opcd == 31, xo1 == 375, !_31), "Load Half Word Algebraic with Update Indexed")
|
||||
INS(lhz, (rD), (rA, d), (), (opcd == 40), "Load Half Word and Zero")
|
||||
INS(lhzu, (rD, rA), (rA, d), (), (opcd == 41), "Load Half Word and Zero with Update")
|
||||
INS(lhzx, (rD), (rA, rB), (), (opcd == 31, xo1 == 279, !_31), "Load Half Word and Zero Indexed")
|
||||
INS(lhzux, (rD, rA), (rA, rB), (), (opcd == 31, xo1 == 311, !_31), "Load Half Word and Zero with Update Indexed")
|
||||
INS(lwz, (rD), (rA, d), (), (opcd == 32), "Load Word and Zero")
|
||||
INS(lwzu, (rD, rA), (rA, d), (), (opcd == 33), "Load Word and Zero with Update")
|
||||
INS(lwzx, (rD), (rA, rB), (), (opcd == 31, xo1 == 23, !_31), "Load Word and Zero Indexed")
|
||||
INS(lwzux, (rD, rA), (rA, rB), (), (opcd == 31, xo1 == 55, !_31), "Load Word and Zero with Update Indexed")
|
||||
|
||||
// Integer Store
|
||||
INS(stb, (), (rS, rA, d), (), (opcd == 38), "Store Byte")
|
||||
INS(stbu, (rA), (rS, rA, d), (), (opcd == 39), "Store Byte with Update")
|
||||
INS(stbx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 215, !_31), "Store Byte Indexed")
|
||||
INS(stbux, (rA), (rS, rA, rB), (), (opcd == 31, xo1 == 247, !_31), "Store Byte with Update Indexed")
|
||||
INS(sth, (), (rS, rA, d), (), (opcd == 44), "Store Half Word")
|
||||
INS(sthu, (rA), (rS, rA, d), (), (opcd == 45), "Store Half Word with Update")
|
||||
INS(sthx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 407, !_31), "Store Half Word Indexed")
|
||||
INS(sthux, (rA), (rS, rA, rB), (), (opcd == 31, xo1 == 439, !_31), "Store Half Word with Update Indexed")
|
||||
INS(stw, (), (rS, rA, d), (), (opcd == 36), "Store Word")
|
||||
INS(stwu, (rA), (rS, rA, d), (), (opcd == 37), "Store Word with Update")
|
||||
INS(stwx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 151, !_31), "Store Word Indexed")
|
||||
INS(stwux, (rA), (rS, rA, rB), (), (opcd == 31, xo1 == 183, !_31), "Store Word with Update Indexed")
|
||||
|
||||
// Integer Load and Store with Byte Reverse
|
||||
INS(lhbrx, (rD), (rA, rB), (), (opcd == 31, xo1 == 790, !_31), "Load Half Word Byte-Reverse Indexed")
|
||||
INS(lwbrx, (rD), (rA, rB), (), (opcd == 31, xo1 == 534, !_31), "Load Word Byte-Reverse Indexed")
|
||||
INS(sthbrx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 918, !_31), "Store Half Word Byte-Reverse Indexed")
|
||||
INS(stwbrx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 662, !_31), "Store Word Byte-Reverse Indexed")
|
||||
|
||||
// Integer Load and Store Multiple
|
||||
INS(lmw, (rD), (rA, d), (), (opcd == 46), "Load Multiple Words")
|
||||
INS(stmw, (), (rS, rA, d), (), (opcd == 47), "Store Multiple Words")
|
||||
|
||||
// Integer Load and Store String
|
||||
INS(lswi, (rD), (rA, nb), (), (opcd == 31, xo1 == 597, !_31), "Load String Word Immediate")
|
||||
INS(lswx, (rD), (rA, rB), (), (opcd == 31, xo1 == 533, !_31), "Load String Word Indexed")
|
||||
INS(stswi, (), (rS, rA, nb), (), (opcd == 31, xo1 == 725, !_31), "Store String Word Immediate")
|
||||
INS(stswx, (), (rS, rA, rB), (), (opcd == 31, xo1 == 661, !_31), "Store String Word Indexed")
|
||||
|
||||
// Memory Synchronisation
|
||||
INS(eieio, (), (), (), (opcd == 31, xo1 == 854, !_6_10, !_11_15, !_16_20, !_31), "Enforce In-Order Execution of I/O")
|
||||
INS(isync, (), (), (), (opcd == 19, xo1 == 150, !_6_10, !_11_15, !_16_20, !_31), "Instruction Synchronise")
|
||||
INS(lwarx, (rD, RSRV), (rA, rB), (), (opcd == 31, xo1 == 20, !_31), "Load Word and Reserve Indexed")
|
||||
INS(stwcx, (RSRV), (rS, rA, rB), (), (opcd == 31, xo1 == 150, _31 == 1), "Store Word Conditional Indexed")
|
||||
INS(sync, (), (), (), (opcd == 31, xo1 == 598, !_6_10, !_11_15, !_16_20, !_31), "Synchronise")
|
||||
|
||||
// Floating-Point Load
|
||||
INS(lfd, (frD), (rA, d), (), (opcd == 50), "Load Floating-Point Double")
|
||||
INS(lfdu, (frD, rA), (rA, d), (), (opcd == 51), "Load Floating-Point Double with Update")
|
||||
INS(lfdx, (frD), (rA, rB), (), (opcd == 31, xo1 == 599, !_31), "Load Floating-Point Double Indexed")
|
||||
INS(lfdux, (frD, rA), (rA, rB), (), (opcd == 31, xo1 == 631, !_31), "Load Floating-Point Double with Update Indexed")
|
||||
INS(lfs, (frD), (rA, d), (), (opcd == 48), "Load Floating-Point Single")
|
||||
INS(lfsu, (frD, rA), (rA, d), (), (opcd == 49), "Load Floating-Point Single with Update")
|
||||
INS(lfsx, (frD), (rA, rB), (), (opcd == 31, xo1 == 535, !_31), "Load Floating-Point Single Indexed")
|
||||
INS(lfsux, (frD, rA), (rA, rB), (), (opcd == 31, xo1 == 567, !_31), "Load Floating-Point Single with Update Indexed")
|
||||
|
||||
// Floating-Point Store
|
||||
INS(stfd, (), (frS, rA, d), (), (opcd == 54), "Store Floating-Point Double")
|
||||
INS(stfdu, (rA), (frS, rA, d), (), (opcd == 55), "Store Floating-Point Double with Update")
|
||||
INS(stfdx, (), (frS, rA, rB), (), (opcd == 31, xo1 == 727, !_31), "Store Floating-Point Double Indexed")
|
||||
INS(stfdux, (rA), (frS, rA, rB), (), (opcd == 31, xo1 == 759, !_31), "Store Floating-Point Double with Update Indexed")
|
||||
INS(stfiwx, (), (frS, rA, rB), (), (opcd == 31, xo1 == 983, !_31), "Store Floating-Point as Integer Word Indexed")
|
||||
INS(stfs, (), (frS, rA, d), (), (opcd == 52), "Store Floating-Point Single")
|
||||
INS(stfsu, (rA), (frS, rA, d), (), (opcd == 53), "Store Floating-Point Single with Update")
|
||||
INS(stfsx, (), (frS, rA, rB), (), (opcd == 31, xo1 == 663, !_31), "Store Floating-Point Single Indexed")
|
||||
INS(stfsux, (rA), (frS, rA, rB), (), (opcd == 31, xo1 == 695, !_31), "Store Floating-Point Single with Update Indexed")
|
||||
|
||||
// Branch
|
||||
INS(b, (), (li), (aa, lk), (opcd == 18), "Branch")
|
||||
INS(bc, (bo), (bi, bd), (aa, lk), (opcd == 16), "Branch Conditional")
|
||||
INS(bcctr, (bo), (bi, CTR), (lk), (opcd == 19, xo1 == 528, !_16_20), "Branch Conditional to CTR")
|
||||
INS(bclr, (bo), (bi, LR), (lk), (opcd == 19, xo1 == 16, !_16_20), "Branch Conditional to LR")
|
||||
|
||||
// System Linkage
|
||||
INS(rfi, (), (), (), (opcd == 19, xo1 == 50, !_6_10, !_11_15, !_16_20, !_31), "")
|
||||
INS(sc, (), (), (), (opcd == 17, !_6_10, !_11_15, !_16_29, _30 == 1, !_31), "Syscall")
|
||||
INS(kc, (), (kcn), (), (opcd == 1), "krncall")
|
||||
|
||||
// Trap
|
||||
INS(tw, (), (to, rA, rB), (), (opcd == 31, xo1 == 4, !_31), "")
|
||||
INS(twi, (), (to, rA, simm), (), (opcd == 3), "")
|
||||
|
||||
// Processor Control
|
||||
INS(mcrxr, (crfD), (XERO), (), (opcd == 31, xo1 == 512, !_9_10, !_11_15, !_16_20, !_31), "Move to Condition Register from XERO")
|
||||
INS(mfcr, (rD), (), (), (opcd == 31, xo1 == 19, !_11_15, !_16_20, !_31), "Move from Condition Register")
|
||||
INS(mfmsr, (rD), (), (), (opcd == 31, xo1 == 83, !_11_15, !_16_20, !_31), "Move from Machine State Register")
|
||||
INS(mfspr, (rD), (spr), (), (opcd == 31, xo1 == 339, !_31), "Move from Special Purpose Register")
|
||||
INS(mftb, (rD), (tbr), (), (opcd == 31, xo1 == 371, !_31), "Move from Time Base Register")
|
||||
INS(mtcrf, (crm), (rS), (), (opcd == 31, xo1 == 144, !_11, !_20, !_31), "Move to Condition Register Fields")
|
||||
INS(mtmsr, (), (rS), (), (opcd == 31, xo1 == 146, !_11_15, !_16_20, !_31), "Move to Machine State Register")
|
||||
INS(mtspr, (spr), (rS), (), (opcd == 31, xo1 == 467, !_31), "Move to Special Purpose Register")
|
||||
|
||||
// Cache Management
|
||||
INS(dcbf, (), (rA, rB), (), (opcd == 31, xo1 == 86, !_6_10, !_31), "")
|
||||
INS(dcbi, (), (rA, rB), (), (opcd == 31, xo1 == 470, !_6_10, !_31), "")
|
||||
INS(dcbst, (), (rA, rB), (), (opcd == 31, xo1 == 54, !_6_10, !_31), "")
|
||||
INS(dcbt, (), (rA, rB), (), (opcd == 31, xo1 == 278, !_6_10, !_31), "")
|
||||
INS(dcbtst, (), (rA, rB), (), (opcd == 31, xo1 == 246, !_6_10, !_31), "")
|
||||
INS(dcbz, (), (rA, rB), (), (opcd == 31, xo1 == 1014, !_6_10, !_31), "")
|
||||
INS(icbi, (), (rA, rB), (), (opcd == 31, xo1 == 982, !_6_10, !_31), "")
|
||||
INS(dcbz_l, (), (rA, rB), (), (opcd == 4, xo1 == 1014, !_6_10, !_31), "")
|
||||
|
||||
// Segment Register Manipulation
|
||||
INS(mfsr, (rD), (sr), (), (opcd == 31, xo1 == 595, !_11, !_16_20, !_31), "Move from Segment Register")
|
||||
INS(mfsrin, (rD), (rB), (), (opcd == 31, xo1 == 659, !_11_15, !_31), "Move from Segment Register Indirect")
|
||||
INS(mtsr, (), (rD, sr), (), (opcd == 31, xo1 == 210, !_11, !_16_20, !_31), "Move to Segment Register")
|
||||
INS(mtsrin, (), (rD, rB), (), (opcd == 31, xo1 == 242, !_11_15, !_31), "Move to Segment Register Indirect")
|
||||
|
||||
// Lookaside Buffer Management
|
||||
INS(tlbie, (), (rB), (), (opcd == 31, xo1 == 306, !_6_10, !_11_15, !_31), "")
|
||||
INS(tlbsync, (), (), (), (opcd == 31, xo1 == 566, !_6_10, !_11_15, !_16_20, !_31), "")
|
||||
|
||||
// External Control
|
||||
INS(eciwx, (rD), (rA, rB), (), (opcd == 31, xo1 == 310, !_31), "")
|
||||
INS(ecowx, (rD), (rA, rB), (), (opcd == 31, xo1 == 438, !_31), "")
|
||||
|
||||
// Paired-Single Load and Store
|
||||
INS(psq_l, (frD), (rA, qd), (w, i), (opcd == 56), "Paired Single Load")
|
||||
INS(psq_lu, (frD), (rA, qd), (w, i), (opcd == 57), "Paired Single Load with Update")
|
||||
INS(psq_lx, (frD), (rA, rB), (qw, qi), (opcd == 4, xo3 == 6, !_31), "Paired Single Load Indexed")
|
||||
INS(psq_lux, (frD), (rA, rB), (qw, qi), (opcd == 4, xo3 == 38, !_31), "Paired Single Load with Update Indexed")
|
||||
INS(psq_st, (frD), (rA, qd), (w, i), (opcd == 60), "Paired Single Store")
|
||||
INS(psq_stu, (frD), (rA, qd), (w, i), (opcd == 61), "Paired Single Store with Update")
|
||||
INS(psq_stx, (frS), (rA, rB), (qw, qi), (opcd == 4, xo3 == 7, !_31), "Paired Single Store Indexed")
|
||||
INS(psq_stux, (frS), (rA, rB), (qw, qi), (opcd == 4, xo3 == 39, !_31), "Paired Single Store with Update Indexed")
|
||||
|
||||
// Paired-Single Floating Point Arithmetic
|
||||
INS(ps_add, (frD, FPSCR), (frA, frB), (rc), (opcd == 4, xo4 == 21, !_21_25), "Paired Single Add")
|
||||
INS(ps_div, (frD, FPSCR), (frA, frB), (rc), (opcd == 4, xo4 == 18, !_21_25), "Paired Single Divide")
|
||||
INS(ps_mul, (frD, FPSCR), (frA, frC), (rc), (opcd == 4, xo4 == 25, !_16_20), "Paired Single Multiply")
|
||||
INS(ps_sub, (frD, FPSCR), (frA, frB), (rc), (opcd == 4, xo4 == 20, !_21_25), "Paired Single Subtract")
|
||||
INS(ps_abs, (frD), (frB), (rc), (opcd == 4, xo1 == 264, !_11_15), "Paired Single Absolute")
|
||||
INS(ps_nabs, (frD), (frB), (rc), (opcd == 4, xo1 == 136, !_11_15), "Paired Single Negate Absolute")
|
||||
INS(ps_neg, (frD), (frB), (rc), (opcd == 4, xo1 == 40, !_11_15), "Paired Single Negate")
|
||||
INS(ps_sel, (frD), (frA, frB, frC), (rc), (opcd == 4, xo4 == 23), "Paired Single Select")
|
||||
INS(ps_res, (frD, FPSCR), (frB), (rc), (opcd == 4, xo4 == 24, !_11_15, !_21_25), "Paired Single Reciprocal")
|
||||
INS(ps_rsqrte, (frD, FPSCR), (frB), (rc), (opcd == 4, xo4 == 26, !_11_15, !_21_25), "Paired Single Reciprocal Square Root Estimate")
|
||||
INS(ps_msub, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 28), "Paired Single Multiply and Subtract")
|
||||
INS(ps_madd, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 29), "Paired Single Multiply and Add")
|
||||
INS(ps_nmsub, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 30), "Paired Single Negate Multiply and Subtract")
|
||||
INS(ps_nmadd, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 31), "Paired Single Negate Multiply and Add")
|
||||
INS(ps_mr, (frD), (frB), (rc), (opcd == 4, xo1 == 72, !_11_15), "Paired Single Move Register")
|
||||
INS(ps_sum0, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 10), "Paired Single Sum High")
|
||||
INS(ps_sum1, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 11), "Paired Single Sum Low")
|
||||
INS(ps_muls0, (frD, FPSCR), (frA, frC), (rc), (opcd == 4, xo4 == 12, !_16_20), "Paired Single Multiply Scalar High")
|
||||
INS(ps_muls1, (frD, FPSCR), (frA, frC), (rc), (opcd == 4, xo4 == 13, !_16_20), "Paired Single Multiply Scalar Low")
|
||||
INS(ps_madds0, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 14), "Paired Single Multiply and Add Scalar High")
|
||||
INS(ps_madds1, (frD, FPSCR), (frA, frB, frC), (rc), (opcd == 4, xo4 == 15), "Paired Single Multiply and Add Scalar Low")
|
||||
INS(ps_cmpu0, (crfD, FPSCR), (frA, frB), (), (opcd == 4, xo1 == 0, !_9_10, !_31), "Paired Single Compare Unordered High")
|
||||
INS(ps_cmpo0, (crfD, FPSCR), (frA, frB), (), (opcd == 4, xo1 == 32, !_9_10, !_31), "Paired Single Compare Ordered High")
|
||||
INS(ps_cmpu1, (crfD, FPSCR), (frA, frB), (), (opcd == 4, xo1 == 64, !_9_10, !_31), "Paired Single Compare Unordered Low")
|
||||
INS(ps_cmpo1, (crfD, FPSCR), (frA, frB), (), (opcd == 4, xo1 == 96, !_9_10, !_31), "Paired Single Compare Ordered Low")
|
||||
INS(ps_merge00, (frD), (frA, frB), (rc), (opcd == 4, xo1 == 528), "Paired Single Merge High")
|
||||
INS(ps_merge01, (frD), (frA, frB), (rc), (opcd == 4, xo1 == 560), "Paired Single Merge Direct")
|
||||
INS(ps_merge10, (frD), (frA, frB), (rc), (opcd == 4, xo1 == 592), "Paired Single Merge Swapped")
|
||||
INS(ps_merge11, (frD), (frA, frB), (rc), (opcd == 4, xo1 == 624), "Paired Single Merge Low")
|
||||
*/
|
||||
147
tools/hardware-tests/generator_testlist.h
Executable file
147
tools/hardware-tests/generator_testlist.h
Executable file
@@ -0,0 +1,147 @@
|
||||
#pragma once
|
||||
#include <vector>
|
||||
#include "cpu/instructiondata.h"
|
||||
|
||||
static const auto gIntegerArithmetic =
|
||||
{
|
||||
InstructionID::add,
|
||||
InstructionID::addc,
|
||||
InstructionID::adde,
|
||||
InstructionID::addi,
|
||||
InstructionID::addic,
|
||||
InstructionID::addicx,
|
||||
InstructionID::addis,
|
||||
InstructionID::addme,
|
||||
InstructionID::addze,
|
||||
InstructionID::divw,
|
||||
InstructionID::divwu,
|
||||
InstructionID::mulhw,
|
||||
InstructionID::mulhwu,
|
||||
InstructionID::mulli,
|
||||
InstructionID::mullw,
|
||||
InstructionID::neg,
|
||||
InstructionID::subf,
|
||||
InstructionID::subfc,
|
||||
InstructionID::subfe,
|
||||
InstructionID::subfic,
|
||||
InstructionID::subfme,
|
||||
InstructionID::subfze,
|
||||
};
|
||||
|
||||
static const auto gIntegerLogical =
|
||||
{
|
||||
InstructionID::and_,
|
||||
InstructionID::andc,
|
||||
InstructionID::andi,
|
||||
InstructionID::andis,
|
||||
InstructionID::cntlzw,
|
||||
InstructionID::eqv,
|
||||
InstructionID::extsb,
|
||||
InstructionID::extsh,
|
||||
InstructionID::nand,
|
||||
InstructionID::nor,
|
||||
InstructionID::or_,
|
||||
InstructionID::orc,
|
||||
InstructionID::ori,
|
||||
InstructionID::oris,
|
||||
InstructionID::xor_,
|
||||
InstructionID::xori,
|
||||
InstructionID::xoris,
|
||||
};
|
||||
|
||||
static const auto gIntegerCompare =
|
||||
{
|
||||
InstructionID::cmp,
|
||||
InstructionID::cmpi,
|
||||
InstructionID::cmpl,
|
||||
InstructionID::cmpli,
|
||||
};
|
||||
|
||||
static const auto gIntegerShift =
|
||||
{
|
||||
InstructionID::slw,
|
||||
InstructionID::sraw,
|
||||
InstructionID::srawi,
|
||||
InstructionID::srw,
|
||||
};
|
||||
|
||||
static const auto gIntegerRotate =
|
||||
{
|
||||
InstructionID::rlwimi,
|
||||
InstructionID::rlwinm,
|
||||
InstructionID::rlwnm,
|
||||
};
|
||||
|
||||
static const auto gConditionRegisterLogical =
|
||||
{
|
||||
InstructionID::crand,
|
||||
InstructionID::crandc,
|
||||
InstructionID::creqv,
|
||||
InstructionID::crnand,
|
||||
InstructionID::crnor,
|
||||
InstructionID::cror,
|
||||
InstructionID::crorc,
|
||||
InstructionID::crxor,
|
||||
//InstructionID::mcrf,
|
||||
};
|
||||
|
||||
static const auto gFloatArithmetic =
|
||||
{
|
||||
InstructionID::fadd,
|
||||
InstructionID::fadds,
|
||||
InstructionID::fdiv,
|
||||
InstructionID::fdivs,
|
||||
InstructionID::fmul,
|
||||
InstructionID::fmuls,
|
||||
InstructionID::fres,
|
||||
InstructionID::fsub,
|
||||
InstructionID::fsubs,
|
||||
InstructionID::fsel,
|
||||
};
|
||||
|
||||
static const auto gFloatArithmeticMuladd =
|
||||
{
|
||||
InstructionID::fmadd,
|
||||
InstructionID::fmadds,
|
||||
InstructionID::fmsub,
|
||||
InstructionID::fmsubs,
|
||||
InstructionID::fnmadd,
|
||||
InstructionID::fnmadds,
|
||||
InstructionID::fnmsub,
|
||||
InstructionID::fnmsubs,
|
||||
};
|
||||
|
||||
static const auto gFloatRound =
|
||||
{
|
||||
InstructionID::fctiw,
|
||||
InstructionID::fctiwz,
|
||||
InstructionID::frsp,
|
||||
};
|
||||
|
||||
static const auto gFloatMove =
|
||||
{
|
||||
InstructionID::fabs,
|
||||
InstructionID::fmr,
|
||||
InstructionID::fnabs,
|
||||
InstructionID::fneg,
|
||||
};
|
||||
|
||||
static const auto gFloatCompare =
|
||||
{
|
||||
InstructionID::fcmpo,
|
||||
InstructionID::fcmpu,
|
||||
};
|
||||
|
||||
static const auto gTestInstructions =
|
||||
{
|
||||
gIntegerArithmetic,
|
||||
gIntegerLogical,
|
||||
gIntegerCompare,
|
||||
gIntegerShift,
|
||||
gIntegerRotate,
|
||||
gConditionRegisterLogical,
|
||||
gFloatArithmetic,
|
||||
gFloatArithmeticMuladd,
|
||||
gFloatRound,
|
||||
gFloatMove,
|
||||
};
|
||||
84
tools/hardware-tests/generator_valuelist.h
Executable file
84
tools/hardware-tests/generator_valuelist.h
Executable file
@@ -0,0 +1,84 @@
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include <vector>
|
||||
|
||||
static const std::vector<uint32_t> gValuesCRB =
|
||||
{
|
||||
0,
|
||||
1,
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesGPR =
|
||||
{
|
||||
0,
|
||||
1,
|
||||
static_cast<uint32_t>(-1),
|
||||
static_cast<uint32_t>(std::numeric_limits<int32_t>::min()),
|
||||
static_cast<uint32_t>(std::numeric_limits<int32_t>::max()),
|
||||
53, 0x12345678, 0x87654321
|
||||
};
|
||||
|
||||
static const std::vector<int16_t> gValuesSIMM =
|
||||
{
|
||||
0,
|
||||
1,
|
||||
-1,
|
||||
std::numeric_limits<int16_t>::min(),
|
||||
std::numeric_limits<int16_t>::max(),
|
||||
53, 0x1234, static_cast<int16_t>(0x8765u)
|
||||
};
|
||||
|
||||
static const std::vector<uint16_t> gValuesUIMM =
|
||||
{
|
||||
0,
|
||||
1,
|
||||
static_cast<uint16_t>(-1),
|
||||
static_cast<uint16_t>(std::numeric_limits<int16_t>::min()),
|
||||
static_cast<uint16_t>(std::numeric_limits<int16_t>::max()),
|
||||
53, 0x1234, 0x8765
|
||||
};
|
||||
|
||||
static const std::vector<double> gValuesFPR =
|
||||
{
|
||||
0.0,
|
||||
-0.0,
|
||||
1.0,
|
||||
-1.0,
|
||||
std::numeric_limits<double>::min(),
|
||||
std::numeric_limits<double>::max(),
|
||||
std::numeric_limits<double>::lowest(),
|
||||
std::numeric_limits<double>::infinity(),
|
||||
-std::numeric_limits<double>::infinity(),
|
||||
std::numeric_limits<double>::quiet_NaN(),
|
||||
std::numeric_limits<double>::signaling_NaN(),
|
||||
std::numeric_limits<double>::denorm_min(),
|
||||
std::numeric_limits<double>::epsilon(),
|
||||
33525.78
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesXERC =
|
||||
{
|
||||
0,
|
||||
1
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesXERSO =
|
||||
{
|
||||
0,
|
||||
1
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesSH =
|
||||
{
|
||||
0, 15, 23, 31
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesMB =
|
||||
{
|
||||
0, 15, 23, 31
|
||||
};
|
||||
|
||||
static const std::vector<uint32_t> gValuesME =
|
||||
{
|
||||
0, 15, 23, 31
|
||||
};
|
||||
337
tools/hardware-tests/server.cpp
Executable file
337
tools/hardware-tests/server.cpp
Executable file
@@ -0,0 +1,337 @@
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iostream>
|
||||
#include <experimental/filesystem>
|
||||
#include <fstream>
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
#include <ovsocket/socket.h>
|
||||
#include <ovsocket/networkthread.h>
|
||||
#include "cpu/instructiondata.h"
|
||||
#include "hardwaretests.h"
|
||||
#include "utils/be_val.h"
|
||||
|
||||
#pragma comment(lib, "ws2_32.lib")
|
||||
#pragma comment(lib, "ovsocket.lib")
|
||||
|
||||
using namespace ovs;
|
||||
using namespace std::placeholders;
|
||||
namespace fs = std::experimental::filesystem;
|
||||
|
||||
// Deal with it.
|
||||
static std::vector<hwtest::TestFile>
|
||||
gTestSet;
|
||||
|
||||
#pragma pack(push, 1)
|
||||
struct HWRegisterState
|
||||
{
|
||||
be_val<uint32_t> xer;
|
||||
be_val<uint32_t> cr;
|
||||
be_val<uint32_t> ctr;
|
||||
be_val<uint32_t> _;
|
||||
be_val<uint32_t> r3;
|
||||
be_val<uint32_t> r4;
|
||||
be_val<uint32_t> r5;
|
||||
be_val<uint32_t> r6;
|
||||
be_val<uint64_t> fpscr;
|
||||
be_val<double> f1;
|
||||
be_val<double> f2;
|
||||
be_val<double> f3;
|
||||
be_val<double> f4;
|
||||
};
|
||||
|
||||
struct PacketHeader
|
||||
{
|
||||
enum Commands
|
||||
{
|
||||
Version = 1,
|
||||
ExecuteGeneralTest = 10,
|
||||
ExecutePairedTest = 20,
|
||||
TestsFinished = 50,
|
||||
};
|
||||
|
||||
be_val<uint16_t> size;
|
||||
be_val<uint16_t> command;
|
||||
};
|
||||
|
||||
struct VersionPacket : PacketHeader
|
||||
{
|
||||
VersionPacket(uint32_t value)
|
||||
{
|
||||
size = sizeof(VersionPacket);
|
||||
command = PacketHeader::Version;
|
||||
version = value;
|
||||
}
|
||||
|
||||
be_val<uint32_t> version;
|
||||
};
|
||||
|
||||
struct ExecuteGeneralTestPacket : PacketHeader
|
||||
{
|
||||
ExecuteGeneralTestPacket()
|
||||
{
|
||||
size = sizeof(ExecuteGeneralTestPacket);
|
||||
command = PacketHeader::ExecuteGeneralTest;
|
||||
memset(&state, 0, sizeof(HWRegisterState));
|
||||
}
|
||||
|
||||
be_val<uint32_t> instr;
|
||||
HWRegisterState state;
|
||||
};
|
||||
|
||||
struct TestFinishedPacket : PacketHeader
|
||||
{
|
||||
TestFinishedPacket()
|
||||
{
|
||||
size = sizeof(VersionPacket);
|
||||
command = PacketHeader::TestsFinished;
|
||||
}
|
||||
};
|
||||
#pragma pack(pop)
|
||||
|
||||
class TestServer
|
||||
{
|
||||
static const uint32_t Version = 1;
|
||||
|
||||
public:
|
||||
TestServer(Socket *socket) :
|
||||
mSocket(socket)
|
||||
{
|
||||
mSocket->addErrorListener(std::bind(&TestServer::onSocketError, this, _1, _2));
|
||||
mSocket->addDisconnectListener(std::bind(&TestServer::onSocketDisconnect, this, _1));
|
||||
mSocket->addReceiveListener(std::bind(&TestServer::onSocketReceive, this, _1, _2, _3));
|
||||
|
||||
// Send version
|
||||
VersionPacket version { Version };
|
||||
mSocket->send(reinterpret_cast<const char *>(&version), sizeof(VersionPacket));
|
||||
|
||||
// Read first packet
|
||||
mSocket->recvFill(sizeof(PacketHeader));
|
||||
|
||||
// Initialise test iterators
|
||||
mTestFile = gTestSet.begin();
|
||||
mTestData = mTestFile->tests.begin();
|
||||
}
|
||||
|
||||
private:
|
||||
void saveTestFile()
|
||||
{
|
||||
// Save test result
|
||||
std::ofstream out("tests/cpu/wiiu/" + mTestFile->name, std::ofstream::out | std::ofstream::binary);
|
||||
cereal::BinaryOutputArchive ar(out);
|
||||
ar(*mTestFile);
|
||||
|
||||
std::cout << "Wrote file tests/cpu/wiiu/" << mTestFile->name << std::endl;
|
||||
}
|
||||
|
||||
void sendNextTest()
|
||||
{
|
||||
if (mTestData == mTestFile->tests.end()) {
|
||||
// Save current test file
|
||||
saveTestFile();
|
||||
|
||||
// To the next test!
|
||||
++mTestFile;
|
||||
|
||||
if (mTestFile == gTestSet.end()) {
|
||||
std::cout << "Tests finished." << std::endl;
|
||||
|
||||
// Notify client tests have finished
|
||||
TestFinishedPacket pak;
|
||||
mSocket->send(reinterpret_cast<const char *>(&pak), sizeof(TestFinishedPacket));
|
||||
} else {
|
||||
// Start next test file
|
||||
mTestData = mTestFile->tests.begin();
|
||||
}
|
||||
}
|
||||
|
||||
// Copy test input
|
||||
ExecuteGeneralTestPacket packet;
|
||||
packet.instr = mTestData->instr.value;
|
||||
packet.state.xer = mTestData->input.xer.value;
|
||||
packet.state.cr = mTestData->input.cr.value;
|
||||
packet.state.ctr = mTestData->input.ctr;
|
||||
packet.state.r3 = mTestData->input.gpr[0];
|
||||
packet.state.r4 = mTestData->input.gpr[1];
|
||||
packet.state.r5 = mTestData->input.gpr[2];
|
||||
packet.state.r6 = mTestData->input.gpr[3];
|
||||
packet.state.fpscr = mTestData->input.fpscr.value;
|
||||
packet.state.f1 = mTestData->input.fr[0];
|
||||
packet.state.f2 = mTestData->input.fr[1];
|
||||
packet.state.f3 = mTestData->input.fr[2];
|
||||
packet.state.f4 = mTestData->input.fr[3];
|
||||
|
||||
mSocket->send(reinterpret_cast<const char *>(&packet), sizeof(ExecuteGeneralTestPacket));
|
||||
}
|
||||
|
||||
void handleTestResult(ExecuteGeneralTestPacket *result)
|
||||
{
|
||||
// Sanity check
|
||||
assert(mTestData->instr.value == result->instr.value());
|
||||
|
||||
// Copy the output
|
||||
mTestData->output.xer.value = result->state.xer;
|
||||
mTestData->output.cr.value = result->state.cr;
|
||||
mTestData->output.ctr = result->state.ctr;
|
||||
mTestData->output.gpr[0] = result->state.r3;
|
||||
mTestData->output.gpr[1] = result->state.r4;
|
||||
mTestData->output.gpr[2] = result->state.r5;
|
||||
mTestData->output.gpr[3] = result->state.r6;
|
||||
mTestData->output.fpscr.value = static_cast<uint32_t>(result->state.fpscr);
|
||||
mTestData->output.fr[0] = result->state.f1;
|
||||
mTestData->output.fr[1] = result->state.f2;
|
||||
mTestData->output.fr[2] = result->state.f3;
|
||||
mTestData->output.fr[3] = result->state.f4;
|
||||
|
||||
// Start next test
|
||||
mTestData++;
|
||||
sendNextTest();
|
||||
}
|
||||
|
||||
void onReceivePacket(PacketHeader *packet)
|
||||
{
|
||||
VersionPacket *version;
|
||||
ExecuteGeneralTestPacket *result;
|
||||
|
||||
switch (packet->command) {
|
||||
case PacketHeader::Version:
|
||||
// Receive version, begin tests
|
||||
version = reinterpret_cast<VersionPacket *>(packet);
|
||||
std::cout << "Server Version: " << Version << ", Client Version: " << version->version << std::endl;
|
||||
std::cout << "Running tests..." << std::endl;
|
||||
sendNextTest();
|
||||
break;
|
||||
case PacketHeader::ExecuteGeneralTest:
|
||||
// Receive test result
|
||||
result = reinterpret_cast<ExecuteGeneralTestPacket *>(packet);
|
||||
handleTestResult(result);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void onSocketError(Socket *socket, int code)
|
||||
{
|
||||
assert(mSocket == socket);
|
||||
std::cout << "Socket error: " << code << std::endl;
|
||||
}
|
||||
|
||||
void onSocketDisconnect(Socket *socket)
|
||||
{
|
||||
assert(mSocket == socket);
|
||||
std::cout << "Socket Disconnected" << std::endl;
|
||||
}
|
||||
|
||||
void onSocketReceive(Socket *socket, const char *buffer, size_t size)
|
||||
{
|
||||
PacketHeader *header;
|
||||
assert(mSocket == socket);
|
||||
|
||||
if (mCurrentPacket.size() == 0) {
|
||||
assert(size == sizeof(PacketHeader));
|
||||
|
||||
// Copy packet to buffer
|
||||
mCurrentPacket.resize(size);
|
||||
header = reinterpret_cast<PacketHeader *>(mCurrentPacket.data());
|
||||
std::memcpy(header, buffer, size);
|
||||
|
||||
// Read rest of packet
|
||||
auto read = header->size - size;
|
||||
socket->recvFill(read);
|
||||
} else {
|
||||
// Check we have read rest of packet
|
||||
header = reinterpret_cast<PacketHeader *>(mCurrentPacket.data());
|
||||
auto totalSize = size + sizeof(PacketHeader);
|
||||
assert(totalSize == header->size);
|
||||
|
||||
// Read rest of packet
|
||||
mCurrentPacket.resize(totalSize);
|
||||
header = reinterpret_cast<PacketHeader *>(mCurrentPacket.data());
|
||||
std::memcpy(mCurrentPacket.data() + sizeof(PacketHeader), buffer, size);
|
||||
|
||||
onReceivePacket(header);
|
||||
|
||||
// Read next packet
|
||||
mCurrentPacket.clear();
|
||||
socket->recvFill(sizeof(PacketHeader));
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
Socket *mSocket;
|
||||
std::vector<char> mCurrentPacket;
|
||||
std::vector<hwtest::TestFile>::iterator mTestFile;
|
||||
std::vector<hwtest::TestData>::iterator mTestData;
|
||||
};
|
||||
|
||||
static std::vector<std::unique_ptr<TestServer>>
|
||||
gTestServers;
|
||||
|
||||
static void
|
||||
loadTests()
|
||||
{
|
||||
fs::create_directories("tests/cpu/wiiu");
|
||||
|
||||
// Read all tests
|
||||
for (auto &entry : fs::directory_iterator("tests/cpu/input")) {
|
||||
std::ifstream file { entry.path().string(), std::ifstream::in | std::ifstream::binary };
|
||||
gTestSet.emplace_back();
|
||||
auto &test = gTestSet.back();
|
||||
test.name = entry.path().filename().string();
|
||||
|
||||
// Parse cereal data
|
||||
cereal::BinaryInputArchive input(file);
|
||||
input(test);
|
||||
}
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
WSADATA wsaData;
|
||||
WSAStartup(MAKEWORD(2, 2), &wsaData);
|
||||
|
||||
loadTests();
|
||||
gInstructionTable.initialise();
|
||||
|
||||
NetworkThread thread;
|
||||
auto socket = new Socket();
|
||||
auto ip = "0.0.0.0";
|
||||
auto port = "8008";
|
||||
|
||||
// On socket error
|
||||
socket->addErrorListener([](Socket *socket, int code) {
|
||||
std::cout << "Listen Socket Error: " << code << std::endl;
|
||||
});
|
||||
|
||||
socket->addDisconnectListener([](Socket *socket) {
|
||||
std::cout << "Listen Socket Disconnected" << std::endl;
|
||||
});
|
||||
|
||||
// On socket connected, accept pls
|
||||
socket->addAcceptListener([&thread](Socket *socket) {
|
||||
auto newSock = socket->accept();
|
||||
|
||||
if (!newSock) {
|
||||
std::cout << "Failed to accept new connection" << std::endl;
|
||||
return;
|
||||
} else {
|
||||
std::cout << "New Connection Accepted" << std::endl;
|
||||
}
|
||||
|
||||
gTestServers.emplace_back(new TestServer(socket));
|
||||
thread.addSocket(newSock);
|
||||
});
|
||||
|
||||
// Start server
|
||||
if (!socket->listen(ip, port)) {
|
||||
std::cout << "Error starting connect!" << std::endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Run network thread in main thread
|
||||
std::cout << "Listening on " << ip << ":" << port << std::endl;
|
||||
thread.addSocket(socket);
|
||||
thread.start();
|
||||
|
||||
WSACleanup();
|
||||
return 0;
|
||||
}
|
||||
53
wiiu.sln
53
wiiu.sln
@@ -27,56 +27,106 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "tools", "tools", "{4E2164E9
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "gsh-disassemble", "build\gsh-disassemble.vcxproj", "{07C14E4C-41E6-4359-934E-7FA06D9800C1}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "hardware-test-server", "build\hardware-test-server.vcxproj", "{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "hardware-test-generator", "build\hardware-test-generator.vcxproj", "{CDFC321E-07C6-44E1-B145-02749935DDFE}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ovsocket", "build\ovsocket.vcxproj", "{01016351-42D4-4D49-A433-00CF4E1F7A8C}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Any CPU = Debug|Any CPU
|
||||
Debug|x64 = Debug|x64
|
||||
Debug|x86 = Debug|x86
|
||||
Release|Any CPU = Release|Any CPU
|
||||
Release|x64 = Release|x64
|
||||
Release|x86 = Release|x86
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Debug|x64.Build.0 = Debug|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Release|x64.ActiveCfg = Release|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Release|x64.Build.0 = Release|x64
|
||||
{C0166DC5-84C8-466C-BD6C-037951915569}.Release|x86.ActiveCfg = Release|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Debug|x64.Build.0 = Debug|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Release|x64.ActiveCfg = Release|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Release|x64.Build.0 = Release|x64
|
||||
{94C92AF7-B8C5-4F0B-A7F4-F80A32DCEC8E}.Release|x86.ActiveCfg = Release|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Debug|x64.Build.0 = Debug|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Release|x64.ActiveCfg = Release|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Release|x64.Build.0 = Release|x64
|
||||
{2808B8EB-ACC1-4EC3-B22E-8D2C16AB7DF6}.Release|x86.ActiveCfg = Release|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Debug|x64.Build.0 = Debug|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Release|x64.ActiveCfg = Release|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Release|x64.Build.0 = Release|x64
|
||||
{D528F1B0-3DA2-496D-9E59-CE80141BD149}.Release|x86.ActiveCfg = Release|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Debug|x64.Build.0 = Debug|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Release|x64.ActiveCfg = Release|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Release|x64.Build.0 = Release|x64
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363}.Release|x86.ActiveCfg = Release|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Debug|x64.Build.0 = Debug|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Release|x64.ActiveCfg = Release|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Release|x64.Build.0 = Release|x64
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458}.Release|x86.ActiveCfg = Release|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Debug|x64.Build.0 = Debug|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Release|x64.ActiveCfg = Release|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Release|x64.Build.0 = Release|x64
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1}.Release|x86.ActiveCfg = Release|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Debug|Any CPU.ActiveCfg = Debug|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Debug|x64.Build.0 = Debug|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Debug|x86.ActiveCfg = Debug|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Release|Any CPU.ActiveCfg = Release|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Release|x64.ActiveCfg = Release|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Release|x64.Build.0 = Release|x64
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8}.Release|x86.ActiveCfg = Release|x64
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Debug|Any CPU.ActiveCfg = Debug|Win32
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Debug|x64.Build.0 = Debug|x64
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Debug|x86.Build.0 = Debug|Win32
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Release|Any CPU.ActiveCfg = Release|Win32
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Release|x64.ActiveCfg = Release|x64
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Release|x64.Build.0 = Release|x64
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Release|x86.ActiveCfg = Release|Win32
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE}.Release|x86.Build.0 = Release|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Debug|Any CPU.ActiveCfg = Debug|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Debug|x64.Build.0 = Debug|x64
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Debug|x86.Build.0 = Debug|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Release|Any CPU.ActiveCfg = Release|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Release|x64.ActiveCfg = Release|x64
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Release|x64.Build.0 = Release|x64
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Release|x86.ActiveCfg = Release|Win32
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C}.Release|x86.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
@@ -88,5 +138,8 @@ Global
|
||||
{7CA9594F-8EC3-4CC2-821B-F87D5DAB6363} = {A7137181-83E5-46FB-A880-B4FB4F4BF3C3}
|
||||
{33466072-B1EB-4404-87E6-7DDD5DBBA458} = {A7137181-83E5-46FB-A880-B4FB4F4BF3C3}
|
||||
{07C14E4C-41E6-4359-934E-7FA06D9800C1} = {4E2164E9-068E-44D0-BC5B-E8A68B30D4CE}
|
||||
{CD2AFBB6-5A6C-4FC6-B76B-F618193AEFC8} = {4E2164E9-068E-44D0-BC5B-E8A68B30D4CE}
|
||||
{CDFC321E-07C6-44E1-B145-02749935DDFE} = {4E2164E9-068E-44D0-BC5B-E8A68B30D4CE}
|
||||
{01016351-42D4-4D49-A433-00CF4E1F7A8C} = {A7137181-83E5-46FB-A880-B4FB4F4BF3C3}
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
|
||||
Reference in New Issue
Block a user