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efikamx-headers: Another dirty ebuild for Efika MX support

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Got tired of not having headers in place, lets move them out of
$kernel_dir and into /usr/include/linux
This commit is contained in:
Steev Klimaszewski
2010-03-22 16:39:40 -05:00
parent e51f38d647
commit f32491e6f1
12 changed files with 3976 additions and 0 deletions
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11
sys-kernel/efikamx-headers/Manifest Normal file
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AUX ipu.h 35632 RMD160 24a862a6ca37a77a2fe7242024581669784441d3 SHA1 cedf4ac5cf211378b2035bfb971c7c2276802b9b SHA256 cb9fec3c57475f20fcc5392190ea7c47fd0f5f2e641b341c5735f2422c0255ef
AUX mxc_asrc.h 5557 RMD160 f38f1e97bbef74e4ec50155f836efeb156f8719e SHA1 843ae33935a1017b6d63ed72a2795af8b67bbb8c SHA256 565b58ea7fa2fc24117df41706d4a07c743f1e70e8aec2d8b9c0efc244a197cb
AUX mxc_mlb.h 1399 RMD160 23a27a28adb11f5217f3084197798a7f2814a344 SHA1 fc6998fd393f90f1d1db6419d29a08e49a7cf67a SHA256 8735770aa464485b068898b1d88806baa6dea924f8de1b79dcbb2d84b3fc9dd5
AUX mxc_pf.h 3509 RMD160 a36d9d748f02bb2f0073ce2d6dfbdde7c0fe3ddb SHA1 b74b3d89ff5c33f7c87fa943b060504143c08a27 SHA256 7c71d9baa119262ef7ad68592ea2977407dead300773e795cc21a5e17ac3b293
AUX mxc_scc2_driver.h 38728 RMD160 91d46d015fa04bc991e993bd9c27d12a77d42291 SHA1 fc57f39bfc87f88265ebe4e5f1086575f27296b9 SHA256 3ec4ccd3cacbf71710679c589a835f24be5c11ca717e124cad6ad8a8d99be8d7
AUX mxc_scc_driver.h 39805 RMD160 f8132d32251a4f2955cd734235852e027a6dd39f SHA1 2ecb5fc12545fbdca6376d6fe30b5810ed163360 SHA256 5c69a463e2e3f29fe580ba44a365f997e3b2f9bdefb8ce19a70a9f59bc1151f8
AUX mxc_si4702.h 970 RMD160 f8b098db20f2c9cc7e820f58bb294e2bec609eac SHA1 17e4e8426a4c7af637d2225a56e34eea5e3df669 SHA256 ccf578823108377b20c2ebfd86552167089939464be6ff17563a76b51e91d6b1
AUX mxc_sim_interface.h 3671 RMD160 d0b6882149a160556d10a95b9f5f5005bb813c3e SHA1 cf2665482877a22362db3d3cf4451ddf5f7fc6b3 SHA256 f19b5ca6c23f00339e8f9415c7f96aa62e216cbad1f6545936c5daa5ebfa41b5
AUX mxc_v4l2.h 1320 RMD160 61d0827a39b0e63c2f1bcd6b1fcb2d989bb8d1d5 SHA1 c4b764740d62d5b50e1624da185b7de98d366218 SHA256 bdc7354dfde7ace0ca27187fc294de1a1cbbdfc1cac10c42f30e435329693ada
AUX mxcfb.h 2085 RMD160 07e88c88afe015369a8e8d2340c508534d7c01bc SHA1 f8ec3f1938aa6ef185363d77e07e1c5bba7ace76 SHA256 af87c8dcee55d674a12b9ff27c4608724dc1c4b77dc8c051a325b8961c7ead2f
EBUILD efikamx-headers-2.6.31.ebuild 357 RMD160 ca3d751e40691feb0caf6a768b8be5d7a47ddf54 SHA1 f6aa5e2549d3850fb9c7b91667a05f3518069fa0 SHA256 1bf4197276e13dabc1ce34f5bf15a9c3b88f062383d3a4ac3a1dcd0b6debd715

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sys-kernel/efikamx-headers/efikamx-headers-2.6.31.ebuild Normal file
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# Copyright 1999-2010 Gentoo Foundation
# Distributed under the terms of the GNU General Public License v2
# $Header: $
EAPI=3
DESCRIPTION="Efika MX system headers from the kernel"
HOMEPAGE=""
SRC_URI=""
LICENSE="GPL-2"
SLOT="0"
KEYWORDS="~arm"
IUSE=""
DEPEND=""
RDEPEND="${DEPEND}"
src_install() {
insinto /usr/include/linux
doins "${FILESDIR}"/*
}

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sys-kernel/efikamx-headers/files/ipu.h Normal file
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sys-kernel/efikamx-headers/files/mxc_asrc.h Normal file
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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mx35_asrc.h
*
* @brief MX35 Asynchronous Sample Rate Converter
*
* @ingroup ??
*/
#ifndef __MXC_ASRC_H__
#define __MXC_ASRC_H__
#define ASRC_IOC_MAGIC 'C'
#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req)
#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config)
#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index)
#define ASRC_QUERYBUF _IOWR(ASRC_IOC_MAGIC, 3, struct asrc_buffer)
#define ASRC_Q_INBUF _IOW(ASRC_IOC_MAGIC, 4, struct asrc_buffer)
#define ASRC_DQ_INBUF _IOW(ASRC_IOC_MAGIC, 5, struct asrc_buffer)
#define ASRC_Q_OUTBUF _IOW(ASRC_IOC_MAGIC, 6, struct asrc_buffer)
#define ASRC_DQ_OUTBUF _IOW(ASRC_IOC_MAGIC, 7, struct asrc_buffer)
#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 8, enum asrc_pair_index)
#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 9, enum asrc_pair_index)
#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 10, struct asrc_status_flags)
#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 11, enum asrc_pair_index)
enum asrc_pair_index {
ASRC_PAIR_A,
ASRC_PAIR_B,
ASRC_PAIR_C
};
enum asrc_inclk {
INCLK_NONE = 0x03,
INCLK_ESAI_RX = 0x00,
INCLK_SSI1_RX = 0x01,
INCLK_SSI2_RX = 0x02,
INCLK_SPDIF_RX = 0x04,
INCLK_MLB_CLK = 0x05,
INCLK_ESAI_TX = 0x08,
INCLK_SSI1_TX = 0x09,
INCLK_SSI2_TX = 0x0a,
INCLK_SPDIF_TX = 0x0c,
INCLK_ASRCK1_CLK = 0x0f,
};
enum asrc_outclk {
OUTCLK_NONE = 0x03,
OUTCLK_ESAI_TX = 0x00,
OUTCLK_SSI1_TX = 0x01,
OUTCLK_SSI2_TX = 0x02,
OUTCLK_SPDIF_TX = 0x04,
OUTCLK_MLB_CLK = 0x05,
OUTCLK_ESAI_RX = 0x08,
OUTCLK_SSI1_RX = 0x09,
OUTCLK_SSI2_RX = 0x0a,
OUTCLK_SPDIF_RX = 0x0c,
OUTCLK_ASRCK1_CLK = 0x0f,
};
struct asrc_config {
enum asrc_pair_index pair;
unsigned int channel_num;
unsigned int buffer_num;
unsigned int dma_buffer_size;
unsigned int input_sample_rate;
unsigned int output_sample_rate;
unsigned int word_width;
enum asrc_inclk inclk;
enum asrc_outclk outclk;
};
struct asrc_pair {
unsigned int start_channel;
unsigned int chn_num;
unsigned int chn_max;
unsigned int active;
unsigned int overload_error;
};
struct asrc_req {
unsigned int chn_num;
enum asrc_pair_index index;
};
struct asrc_querybuf {
unsigned int buffer_index;
unsigned int input_length;
unsigned int output_length;
unsigned long input_offset;
unsigned long output_offset;
};
struct asrc_buffer {
unsigned int index;
unsigned int length;
int buf_valid;
};
struct asrc_status_flags {
enum asrc_pair_index index;
unsigned int overload_error;
};
#define ASRC_BUF_NA -35 /* ASRC DQ's buffer is NOT available */
#define ASRC_BUF_AV 35 /* ASRC DQ's buffer is available */
enum asrc_error_status {
ASRC_TASK_Q_OVERLOAD = 0x01,
ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
ASRC_INPUT_TASK_OVERLOAD = 0x04,
ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
};
#ifdef __KERNEL__
#define ASRC_DMA_BUFFER_NUM 8
#define ASRC_ASRCTR_REG 0x00
#define ASRC_ASRIER_REG 0x04
#define ASRC_ASRCNCR_REG 0x0C
#define ASRC_ASRCFG_REG 0x10
#define ASRC_ASRCSR_REG 0x14
#define ASRC_ASRCDR1_REG 0x18
#define ASRC_ASRCDR2_REG 0x1C
#define ASRC_ASRSTR_REG 0x20
#define ASRC_ASRRA_REG 0x24
#define ASRC_ASRRB_REG 0x28
#define ASRC_ASRRC_REG 0x2C
#define ASRC_ASRPM1_REG 0x40
#define ASRC_ASRPM2_REG 0x44
#define ASRC_ASRPM3_REG 0x48
#define ASRC_ASRPM4_REG 0x4C
#define ASRC_ASRPM5_REG 0x50
#define ASRC_ASRTFR1 0x54
#define ASRC_ASRCCR_REG 0x5C
#define ASRC_ASRDIA_REG 0x60
#define ASRC_ASRDOA_REG 0x64
#define ASRC_ASRDIB_REG 0x68
#define ASRC_ASRDOB_REG 0x6C
#define ASRC_ASRDIC_REG 0x70
#define ASRC_ASRDOC_REG 0x74
#define ASRC_ASRIDRHA_REG 0x80
#define ASRC_ASRIDRLA_REG 0x84
#define ASRC_ASRIDRHB_REG 0x88
#define ASRC_ASRIDRLB_REG 0x8C
#define ASRC_ASRIDRHC_REG 0x90
#define ASRC_ASRIDRLC_REG 0x94
#define ASRC_ASR76K_REG 0x98
#define ASRC_ASR56K_REG 0x9C
struct dma_block {
unsigned int index;
unsigned int length;
unsigned char *dma_vaddr;
dma_addr_t dma_paddr;
struct list_head queue;
};
struct asrc_pair_params {
enum asrc_pair_index index;
struct list_head input_queue;
struct list_head input_done_queue;
struct list_head output_queue;
struct list_head output_done_queue;
wait_queue_head_t input_wait_queue;
wait_queue_head_t output_wait_queue;
unsigned int input_counter;
unsigned int output_counter;
unsigned int input_queue_empty;
unsigned int output_queue_empty;
unsigned int input_dma_channel;
unsigned int output_dma_channel;
unsigned int input_buffer_size;
unsigned int output_buffer_size;
unsigned int buffer_num;
unsigned int pair_hold;
unsigned int asrc_active;
struct dma_block input_dma[ASRC_DMA_BUFFER_NUM];
struct dma_block output_dma[ASRC_DMA_BUFFER_NUM];
struct semaphore busy_lock;
};
struct asrc_data {
struct asrc_pair asrc_pair[3];
};
extern int asrc_req_pair(int chn_num, enum asrc_pair_index *index);
extern void asrc_release_pair(enum asrc_pair_index index);
extern int asrc_config_pair(struct asrc_config *config);
extern void asrc_get_status(struct asrc_status_flags *flags);
extern void asrc_start_conv(enum asrc_pair_index index);
extern void asrc_stop_conv(enum asrc_pair_index index);
#endif /* __kERNEL__ */
#endif /* __MXC_ASRC_H__ */

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/*
* mxc_mlb.h
*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef _MXC_MLB_H
#define _MXC_MLB_H
/* define IOCTL command */
#define MLB_SET_FPS _IOW('S', 0x10, unsigned int)
#define MLB_GET_VER _IOR('S', 0x11, unsigned long)
#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char)
/*!
* set channel address for each logical channel
* the MSB 16bits is for tx channel, the left LSB is for rx channel
*/
#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int)
#define MLB_CHAN_STARTUP _IO('S', 0x14)
#define MLB_CHAN_SHUTDOWN _IO('S', 0x15)
#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long)
/*!
* MLB event define
*/
enum {
MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0,
MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1,
MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8,
MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9,
MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16,
MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17,
MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24,
MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25,
};
#ifdef __KERNEL__
extern void gpio_mlb_active(void);
extern void gpio_mlb_inactive(void);
#endif
#endif /* _MXC_MLB_H */

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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU Lesser General
* Public License. You may obtain a copy of the GNU Lesser General
* Public License Version 2.1 or later at the following locations:
*
* http://www.opensource.org/licenses/lgpl-license.html
* http://www.gnu.org/copyleft/lgpl.html
*/
/*!
* @defgroup MXC_PF MPEG4/H.264 Post Filter Driver
*/
/*!
* @file arch-mxc/mxc_pf.h
*
* @brief MXC IPU MPEG4/H.264 Post-filtering driver
*
* User-level API for IPU Hardware MPEG4/H.264 Post-filtering.
*
* @ingroup MXC_PF
*/
#ifndef __INCLUDED_MXC_PF_H__
#define __INCLUDED_MXC_PF_H__
#define PF_MAX_BUFFER_CNT 17
#define PF_WAIT_Y 0x0001
#define PF_WAIT_U 0x0002
#define PF_WAIT_V 0x0004
#define PF_WAIT_ALL (PF_WAIT_Y|PF_WAIT_U|PF_WAIT_V)
/*!
* Structure for Post Filter initialization parameters.
*/
typedef struct {
uint16_t pf_mode; /*!< Post filter operation mode */
uint16_t width; /*!< Width of frame in pixels */
uint16_t height; /*!< Height of frame in pixels */
uint16_t stride; /*!< Stride of Y plane in pixels. Stride for U and V planes is half Y stride */
uint32_t qp_size;
unsigned long qp_paddr;
} pf_init_params;
/*!
* Structure for Post Filter buffer request parameters.
*/
typedef struct {
int count; /*!< Number of buffers requested */
__u32 req_size;
} pf_reqbufs_params;
/*!
* Structure for Post Filter buffer request parameters.
*/
typedef struct {
int index;
int size; /*!< Size of buffer allocated */
__u32 offset; /*!< Buffer offset in driver memory. Set by QUERYBUF */
__u32 y_offset; /*!< Optional starting relative offset of Y data
from beginning of buffer. Set to 0 to use default
calculated based on height and stride */
__u32 u_offset; /*!< Optional starting relative offset of U data
from beginning of buffer. Set to 0 to use default
calculated based on height and stride */
__u32 v_offset; /*!< Optional starting relative offset of V data
from beginning of buffer. Set to 0 to use default
calculated based on height and stride */
} pf_buf;
/*!
* Structure for Post Filter start parameters.
*/
typedef struct {
pf_buf in; /*!< Input buffer address and offsets */
pf_buf out; /*!< Output buffer address and offsets */
int qp_buf;
int wait;
uint32_t h264_pause_row; /*!< Row to pause at for H.264 mode. 0 to disable pause */
} pf_start_params;
/*! @name User Client Ioctl Interface */
/*! @{ */
/*!
* IOCTL to Initialize the Post Filter.
*/
#define PF_IOCTL_INIT _IOW('F',0x0, pf_init_params)
/*!
* IOCTL to Uninitialize the Post Filter.
*/
#define PF_IOCTL_UNINIT _IO('F',0x1)
/*!
* IOCTL to set the buffer mode and allocate buffers if driver allocated.
*/
#define PF_IOCTL_REQBUFS _IOWR('F',0x2, pf_reqbufs_params)
/*!
* IOCTL to set the buffer mode and allocate buffers if driver allocated.
*/
#define PF_IOCTL_QUERYBUF _IOR('F',0x2, pf_buf)
/*!
* IOCTL to start post filtering on a frame of data. This ioctl may block until
* processing is done or return immediately.
*/
#define PF_IOCTL_START _IOWR('F',0x3, pf_start_params)
/*!
* IOCTL to resume post-filtering after an intra frame pause in H.264 mode.
*/
#define PF_IOCTL_RESUME _IOW('F',0x4, int)
/*!
* IOCTL to wait for post-filtering to complete.
*/
#define PF_IOCTL_WAIT _IOW('F',0x5, int)
/*! @} */
#endif /* __INCLUDED_MXC_PF_H__ */

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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef SCC_DRIVER_H
#define SCC_DRIVER_H
/*
* NAMING CONVENTIONS
* ==================
* (A note to maintainers and other interested parties)
*
* Use scc_ or SCC_ prefix for 'high-level' interface routines and the types
* passed to those routines. Try to avoid #defines in these interfaces.
*
* Use SMN_ or SCM_ prefix for the #defines used with scc_read_register() and
* scc_write_register, or values passed/retrieved from those routines.
*/
/*! @file mxc_scc2_driver.h
*
* @brief (Header file to use the SCC2 driver.)
*
* The SCC2 driver is available to other kernel modules directly. Secure
* Partition functionality is extended to users through the SHW API. Other
* functionality of the SCC2 is limited to kernel-space users.
*
* With the exception of #scc_monitor_security_failure(), all routines are
* 'synchronous', i.e. they will not return to their caller until the requested
* action is complete, or fails to complete. Some of these functions could
* take quite a while to perform, depending upon the request.
*
* Routines are provided to:
* @li trigger a security-violation alarm - #scc_set_sw_alarm()
* @li get configuration and version information - #scc_get_configuration()
* @li zeroize memory - #scc_zeroize_memories()
* @li Work with secure partitions: #scc_allocate_partition()
* #scc_engage_partition() #scc_diminish_permissions()
* #scc_release_partition()
* @li Encrypt or decrypt regions of data: #scc_encrypt_region()
* #scc_decrypt_region()
* @li monitor the Security Failure alarm - #scc_monitor_security_failure()
* @li stop monitoring Security Failure alarm -
* #scc_stop_monitoring_security_failure()
* @li write registers of the SCC - #scc_write_register()
* @li read registers of the SCC - #scc_read_register()
*
* The SCC2 encrypts and decrypts using Triple DES with an internally stored
* key. When the SCC2 is in Secure mode, it uses its secret, unique-per-chip
* key. When it is in Non-Secure mode, it uses a default key. This ensures
* that secrets stay secret if the SCC2 is not in Secure mode.
*
* Not all functions that could be provided in a 'high level' manner have been
* implemented. Among the missing are interfaces to the ASC/AIC components and
* the timer functions. These and other features must be accessed through
* #scc_read_register() and #scc_write_register(), using the @c \#define values
* provided.
*
* Here is a glossary of acronyms used in the SCC2 driver documentation:
* - CBC - Cipher Block Chaining. A method of performing a block cipher.
* Each block is encrypted using some part of the result of the previous
* block's encryption. It needs an 'initialization vector' to seed the
* operation.
* - ECB - Electronic Code Book. A method of performing a block cipher.
* With a given key, a given block will always encrypt to the same value.
* - DES - Data Encryption Standard. (8-byte) Block cipher algorithm which
* uses 56-bit keys. In SCC2, this key is constant and unique to the device.
* SCC uses the "triple DES" form of this algorithm.
* - AIC - Algorithm Integrity Checker.
* - ASC - Algorithm Sequence Checker.
* - SMN - Security Monitor. The part of the SCC2 responsible for monitoring
* for security problems and notifying the CPU and other PISA components.
* - SCM - Secure Memory. The part of the SCC2 which handles the cryptography.
* - SCC - Security Controller. Central security mechanism for PISA.
* - PISA - Platform-Independent Security Architecture.
*/
/* Temporarily define compile-time flags to make Doxygen happy. */
#ifdef DOXYGEN_HACK
/** @defgroup scccompileflags SCC Driver compile-time flags
*
* These preprocessor flags should be set, if desired, in a makefile so
* that they show up on the compiler command line.
*/
/** @addtogroup scccompileflags */
/** @{ */
/**
* Compile-time flag to change @ref smnregs and @ref scmregs
* offset values for the SCC's implementation on the MX.21 board.
*
* This must also be set properly for any code which calls the
* scc_read_register() or scc_write_register() functions or references the
* register offsets.
*/
#define TAHITI
/** @} */
#undef TAHITI
#endif /* DOXYGEN_HACK */
/*! Major Version of the driver. Used for
scc_configuration->driver_major_version */
#define SCC_DRIVER_MAJOR_VERSION 2
/*! Old Minor Version of the driver. */
#define SCC_DRIVER_MINOR_VERSION_0 0
/*! Minor Version of the driver. Used for
scc_configuration->driver_minor_version */
#define SCC_DRIVER_MINOR_VERSION_2 2
/*!
* Interrupt line number of SCM interrupt.
*/
#define INT_SCC_SCM MXC_INT_SCC_SCM
/*!
* Interrupt line number of the SMN interrupt.
*/
#define INT_SCC_SMN MXC_INT_SCC_SMN
/**
* @typedef scc_return_t
*/
/** Common status return values from SCC driver functions. */
typedef enum scc_return_t {
SCC_RET_OK = 0, /**< Function succeeded */
SCC_RET_FAIL, /**< Non-specific failure */
SCC_RET_VERIFICATION_FAILED,
/**< Decrypt validation failed */
SCC_RET_TOO_MANY_FUNCTIONS,
/**< At maximum registered functions */
SCC_RET_BUSY, /**< SCC is busy and cannot handle request */
/**< Encryption or decryption failed because@c count_out_bytes
says that @c data_out is too small to hold the value. */
SCC_RET_INSUFFICIENT_SPACE,
} scc_return_t;
/**
* @typedef scc_partition_status_t
*/
/** Partition status information. */
typedef enum scc_partition_status_t {
SCC_PART_S_UNUSABLE,
/**< Partition not implemented */
SCC_PART_S_UNAVAILABLE,
/**< Partition owned by other host */
SCC_PART_S_AVAILABLE,
/**< Partition available */
SCC_PART_S_ALLOCATED,
/**< Partition owned by host but not engaged*/
SCC_PART_S_ENGAGED,
/**< Partition owned by host and engaged */
} scc_partition_status_t;
/**
* Configuration information about SCC and the driver.
*
* This struct/typedef contains information from the SCC and the driver to
* allow the user of the driver to determine the size of the SCC's memories and
* the version of the SCC and the driver.
*/
typedef struct scc_config_t {
int driver_major_version;
/**< Major version of the SCC driver code */
int driver_minor_version;
/**< Minor version of the SCC driver code */
int scm_version; /**< Version from SCM Configuration register */
int smn_version; /**< Version from SMN Status register */
/**< Number of bytes per block of RAM; also
block size of the crypto algorithm. */
int block_size_bytes;
int partition_size_bytes;
/**< Number of bytes in each partition */
int partition_count;
/**< Number of partitions on this platform */
} scc_config_t;
/**
* @typedef scc_enc_dec_t
*/
/**
* Determine whether SCC will run its cryptographic
* function as an encryption or decryption.
*/
typedef enum scc_enc_dec_t {
SCC_ENCRYPT, /**< Encrypt (from Red to Black) */
SCC_DECRYPT /**< Decrypt (from Black to Red) */
} scc_enc_dec_t;
/**
* @typedef scc_verify_t
*/
/**
* Tell the driver whether it is responsible for verifying the integrity of a
* secret. During an encryption, using other than #SCC_VERIFY_MODE_NONE will
* cause a check value to be generated and appended to the plaintext before
* encryption. During decryption, the check value will be verified after
* decryption, and then stripped from the message.
*/
typedef enum scc_verify_t {
/** No verification value added or checked. Input plaintext data must be
* be a multiple of the blocksize (#scc_get_configuration()). */
SCC_VERIFY_MODE_NONE,
/** Driver will generate/validate a 2-byte CCITT CRC. Input plaintext
will be padded to a multiple of the blocksize, adding 3-10 bytes
to the resulting output ciphertext. Upon decryption, this padding
will be stripped, and the CRC will be verified. */
SCC_VERIFY_MODE_CCITT_CRC
} scc_verify_t;
/**
* @typedef scc_cypher_mode_t
*/
/**
* Select the cypher mode to use for partition cover/uncover operations.
*/
typedef enum scc_cypher_mode_t {
SCC_CYPHER_MODE_ECB = 1,
/**< ECB mode */
SCC_CYPHER_MODE_CBC = 2,
/**< CBC mode */
} scc_cypher_mode_t;
/**
* Allocate a partition of secure memory
*
* @param smid_value Value to use for the SMID register. Must be 0 for
* kernel mode ownership.
* @param[out] part_no (If successful) Assigned partition number.
* @param[out] part_base Kernel virtual address of the partition.
* @param[out] part_phys Physical address of the partition.
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t
scc_allocate_partition(uint32_t smid_value,
int *part_no,
void **part_base, uint32_t *part_phys);
/* Note: This function has to be run in the same context (userspace or kernel
* mode) as the process that will be using the partition. Because the SCC2 API
* is not accessible in user mode, this function is also provided as a macro in
* in fsl_shw.h. Kernel-mode users that include this file are able to use this
* version of the function without having to include the whole SHW API. If the
* macro definition was defined before we got here, un-define it so this
* version will be used instead.
*/
#ifdef scc_engage_partition
#undef scc_engage_partition
#endif
/**
* Engage partition of secure memory
*
* @param part_base (kernel) Virtual
* @param UMID NULL, or 16-byte UMID for partition security
* @param permissions ORed values of the type SCM_PERM_* which will be used as
* initial partition permissions. SHW API users should use
* the FSL_PERM_* definitions instead.
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t
scc_engage_partition(void *part_base,
const uint8_t *UMID, uint32_t permissions);
/**
* Release a partition of secure memory
*
* @param part_base Kernel virtual address of the partition to be released.
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t scc_release_partition(void *part_base);
/**
* Diminish the permissions on a partition of secure memory
*
* @param part_base Kernel virtual address of the partition.
*
* @param permissions ORed values of the type SCM_PERM_* which will be used as
* initial partition permissions. SHW API users should use
* the FSL_PERM_* definitions instead.
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t
scc_diminish_permissions(void *part_base, uint32_t permissions);
/**
* Query the status of a partition of secure memory
*
* @param part_base Kernel virtual address of the partition.
*
* @return SCC_RET_OK if successful.
*/
extern scc_partition_status_t scc_partition_status(void *part_base);
/**
* Calculate the physical address from the kernel virtual address.
*/
extern uint32_t scc_virt_to_phys(void *address);
/*scc_return_t
scc_verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len);*/
/**
* Encrypt a region of secure memory.
*
* @param part_base Kernel virtual address of the partition.
* @param offset_bytes Offset from the start of the partition to the plaintext
* data.
* @param byte_count Length of the region (octets).
* @param black_data Physical location to store the encrypted data.
* @param IV Value to use for the Initialization Vector.
* @param cypher_mode Cyphering mode to use, specified by type
* #scc_cypher_mode_t
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t
scc_encrypt_region(uint32_t part_base, uint32_t offset_bytes,
uint32_t byte_count, uint8_t *black_data,
uint32_t *IV, scc_cypher_mode_t cypher_mode);
/**
* Decrypt a region into secure memory
*
* @param part_base Kernel virtual address of the partition.
* @param offset_bytes Offset from the start of the partition to store the
* plaintext data.
* @param byte_count Length of the region (octets).
* @param black_data Physical location of the encrypted data.
* @param IV Value to use for the Initialization Vector.
* @param cypher_mode Cyphering mode to use, specified by type
* #scc_cypher_mode_t
*
* @return SCC_RET_OK if successful.
*/
extern scc_return_t
scc_decrypt_region(uint32_t part_base, uint32_t offset_bytes,
uint32_t byte_count, uint8_t *black_data,
uint32_t *IV, scc_cypher_mode_t cypher_mode);
/**
* Retrieve configuration information from the SCC.
*
* This function always succeeds.
*
* @return A pointer to the configuration information. This is a pointer to
* static memory and must not be freed. The values never change, and
* the return value will never be null.
*/
extern scc_config_t *scc_get_configuration(void);
/**
* Zeroize Red and Black memories of the SCC. This will start the Zeroizing
* process. The routine will return when the memories have zeroized or failed
* to do so. The driver will poll waiting for this to occur, so this
* routine must not be called from interrupt level. Some future version of
* driver may elect instead to sleep.
*
* @return 0 or error if initialization fails.
*/
extern scc_return_t scc_zeroize_memories(void);
/**
* Signal a software alarm to the SCC. This will take the SCC and other PISA
* parts out of Secure mode and into Security Failure mode. The SCC will stay
* in failed mode until a reboot.
*
* @internal
* If the SCC is not already in fail state, simply write the
* #SMN_COMMAND_SET_SOFTWARE_ALARM bit in #SMN_COMMAND_REG. Since there is no
* reason to wait for the interrupt to bounce back, simply act as though
* one did.
*/
extern void scc_set_sw_alarm(void);
/**
* This routine will register a function to be called should a Security Failure
* be signalled by the SCC (Security Monitor).
*
* The callback function may be called from interrupt level, it may be called
* from some process' task. It should therefore not take a long time to
* perform its operation, and it may not sleep.
*
* @param callback_func Function pointer to routine which will receive
* notification of the security failure.
* @return 0 if function was successfully registered, non-zero on
* failure. See #scc_return_t.
*
* @internal
* There is a fixed global static array which keeps track of the requests to
* monitor the failure.
*
* Add @c callback_func to the first empty slot in #scc_callbacks[]. If there
* is no room, return #SCC_RET_TOO_MANY_FUNCTIONS.
*/
extern scc_return_t scc_monitor_security_failure(void
callback_func(void));
/**
* This routine will deregister a function previously registered with
* #scc_monitor_security_failure().
*
* @param callback_func Function pointer to routine previously registered with
* #scc_stop_monitoring_security_failure().
*/
extern void scc_stop_monitoring_security_failure(void
callback_func(void));
/**
* Read value from an SCC register.
* The offset will be checked for validity (range) as well as whether it is
* accessible (e.g. not busy, not in failed state) at the time of the call.
*
* @param[in] register_offset The (byte) offset within the SCC block
* of the register to be queried. See
* @ref scmregs and @ref smnregs.
* @param[out] value Pointer to where value from the register
* should be placed.
* @return 0 if OK, non-zero on error. See #scc_return_t.
*
* @internal
* Verify that the register_offset is a) valid, b) refers to a readable
* register, and c) the SCC is in a state which would allow a read of this
* register.
*/
extern scc_return_t scc_read_register(int register_offset,
uint32_t * value);
/**
* Write a new value into an SCC register.
* The offset will be checked for validity (range) as well as whether it is
* accessible (e.g. not busy, not in failed state) at the time of the call.
*
* @param[in] register_offset The (byte) offset within the SCC block
* of the register to be modified. See
* @ref scmregs and @ref smnregs
* @param[in] value The value to store into the register.
* @return 0 if OK, non-zero on error. See #scc_return_t.
*
* @internal
* Verify that the register_offset is a) valid, b) refers to a writeable
* register, and c) the SCC is in a state which would allow a write to this
* register.
*/
extern scc_return_t scc_write_register(int register_offset,
uint32_t value);
/**
* @defgroup scmregs SCM Registers
*
* These values are offsets into the SCC for the Secure Memory
* (SCM) registers. They are used in the @c register_offset parameter of
* #scc_read_register() and #scc_write_register().
*/
/** @addtogroup scmregs */
/** @{ */
/** Offset of SCM Version ID Register */
#define SCM_VERSION_REG 0x000
/** Offset of SCM Interrupt Control Register */
#define SCM_INT_CTL_REG 0x008
/** Offset of SCM Status Register */
#define SCM_STATUS_REG 0x00c
/** Offset of SCM Error Status Register */
#define SCM_ERR_STATUS_REG 0x010
/** Offset of SCM Fault Address Register */
#define SCM_FAULT_ADR_REG 0x014
/** Offset of SCM Partition Owners Register */
#define SCM_PART_OWNERS_REG 0x018
/** Offset of SCM Partitions Engaged Register */
#define SCM_PART_ENGAGED_REG 0x01c
/** Offset of SCM Unique Number 0 Register */
#define SCM_UNIQUE_ID0_REG 0x020
/** Offset of SCM Unique Number 1 Register */
#define SCM_UNIQUE_ID1_REG 0x024
/** Offset of SCM Unique Number 2 Register */
#define SCM_UNIQUE_ID2_REG 0x028
/** Offset of SCM Unique Number 3 Register */
#define SCM_UNIQUE_ID3_REG 0x02c
/** Offset of SCM Zeroize Command Register */
#define SCM_ZCMD_REG 0x050
/** Offset of SCM Cipher Command Register */
#define SCM_CCMD_REG 0x054
/** Offset of SCM Cipher Black RAM Start Address Register */
#define SCM_C_BLACK_ST_REG 0x058
/** Offset of SCM Internal Debug Register */
#define SCM_DBG_STATUS_REG 0x05c
/** Offset of SCM Cipher IV 0 Register */
#define SCM_AES_CBC_IV0_REG 0x060
/** Offset of SCM Cipher IV 1 Register */
#define SCM_AES_CBC_IV1_REG 0x064
/** Offset of SCM Cipher IV 2 Register */
#define SCM_AES_CBC_IV2_REG 0x068
/** Offset of SCM Cipher IV 3 Register */
#define SCM_AES_CBC_IV3_REG 0x06c
/** Offset of SCM SMID Partition 0 Register */
#define SCM_SMID0_REG 0x080
/** Offset of SCM Partition 0 Access Permissions Register */
#define SCM_ACC0_REG 0x084
/** Offset of SCM SMID Partition 1 Register */
#define SCM_SMID1_REG 0x088
/** Offset of SCM Partition 1 Access Permissions Register */
#define SCM_ACC1_REG 0x08c
/** Offset of SCM SMID Partition 2 Register */
#define SCM_SMID2_REG 0x090
/** Offset of SCM Partition 2 Access Permissions Register */
#define SCM_ACC2_REG 0x094
/** Offset of SCM SMID Partition 3 Register */
#define SCM_SMID3_REG 0x098
/** Offset of SCM Partition 3 Access Permissions Register */
#define SCM_ACC3_REG 0x09c
/** Offset of SCM SMID Partition 4 Register */
#define SCM_SMID4_REG 0x0a0
/** Offset of SCM Partition 4 Access Permissions Register */
#define SCM_ACC4_REG 0x0a4
/** Offset of SCM SMID Partition 5 Register */
#define SCM_SMID5_REG 0x0a8
/** Offset of SCM Partition 5 Access Permissions Register */
#define SCM_ACC5_REG 0x0ac
/** Offset of SCM SMID Partition 6 Register */
#define SCM_SMID6_REG 0x0b0
/** Offset of SCM Partition 6 Access Permissions Register */
#define SCM_ACC6_REG 0x0b4
/** Offset of SCM SMID Partition 7 Register */
#define SCM_SMID7_REG 0x0b8
/** Offset of SCM Partition 7 Access Permissions Register */
#define SCM_ACC7_REG 0x0bc
/** Offset of SCM SMID Partition 8 Register */
#define SCM_SMID8_REG 0x0c0
/** Offset of SCM Partition 8 Access Permissions Register */
#define SCM_ACC8_REG 0x0c4
/** Offset of SCM SMID Partition 9 Register */
#define SCM_SMID9_REG 0x0c8
/** Offset of SCM Partition 9 Access Permissions Register */
#define SCM_ACC9_REG 0x0cc
/** Offset of SCM SMID Partition 10 Register */
#define SCM_SMID10_REG 0x0d0
/** Offset of SCM Partition 10 Access Permissions Register */
#define SCM_ACC10_REG 0x0d4
/** Offset of SCM SMID Partition 11 Register */
#define SCM_SMID11_REG 0x0d8
/** Offset of SCM Partition 11 Access Permissions Register */
#define SCM_ACC11_REG 0x0dc
/** Offset of SCM SMID Partition 12 Register */
#define SCM_SMID12_REG 0x0e0
/** Offset of SCM Partition 12 Access Permissions Register */
#define SCM_ACC12_REG 0x0e4
/** Offset of SCM SMID Partition 13 Register */
#define SCM_SMID13_REG 0x0e8
/** Offset of SCM Partition 13 Access Permissions Register */
#define SCM_ACC13_REG 0x0ec
/** Offset of SCM SMID Partition 14 Register */
#define SCM_SMID14_REG 0x0f0
/** Offset of SCM Partition 14 Access Permissions Register */
#define SCM_ACC14_REG 0x0f4
/** Offset of SCM SMID Partition 15 Register */
#define SCM_SMID15_REG 0x0f8
/** Offset of SCM Partition 15 Access Permissions Register */
#define SCM_ACC15_REG 0x0fc
/** @} */
/** Number of bytes of register space for the SCM. */
#define SCM_REG_BANK_SIZE 0x100
/** Number of bytes of register space for the SCM. */
#define SCM_REG_BANK_SIZE 0x100
/** Offset of the SMN registers */
#define SMN_ADDR_OFFSET 0x100
/**
* @defgroup smnregs SMN Registers
*
* These values are offsets into the SCC for the Security Monitor
* (SMN) registers. They are used in the @c register_offset parameter of the
* #scc_read_register() and #scc_write_register().
*/
/** @addtogroup smnregs */
/** @{ */
/** Offset of SMN Status Register */
#define SMN_STATUS_REG (SMN_ADDR_OFFSET+0x00000000)
/** Offset of SMH Command Register */
#define SMN_COMMAND_REG (SMN_ADDR_OFFSET+0x00000004)
/** Offset of SMH Sequence Start Register */
#define SMN_SEQ_START_REG (SMN_ADDR_OFFSET+0x00000008)
/** Offset of SMH Sequence End Register */
#define SMN_SEQ_END_REG (SMN_ADDR_OFFSET+0x0000000c)
/** Offset of SMH Sequence Check Register */
#define SMN_SEQ_CHECK_REG (SMN_ADDR_OFFSET+0x00000010)
/** Offset of SMH BitBank Count Register */
#define SMN_BB_CNT_REG (SMN_ADDR_OFFSET+0x00000014)
/** Offset of SMH BitBank Increment Register */
#define SMN_BB_INC_REG (SMN_ADDR_OFFSET+0x00000018)
/** Offset of SMH BitBank Decrement Register */
#define SMN_BB_DEC_REG (SMN_ADDR_OFFSET+0x0000001c)
/** Offset of SMH Compare Register */
#define SMN_COMPARE_REG (SMN_ADDR_OFFSET+0x00000020)
/** Offset of SMH Plaintext Check Register */
#define SMN_PT_CHK_REG (SMN_ADDR_OFFSET+0x00000024)
/** Offset of SMH Ciphertext Check Register */
#define SMN_CT_CHK_REG (SMN_ADDR_OFFSET+0x00000028)
/** Offset of SMH Timer Initial Value Register */
#define SMN_TIMER_IV_REG (SMN_ADDR_OFFSET+0x0000002c)
/** Offset of SMH Timer Control Register */
#define SMN_TIMER_CTL_REG (SMN_ADDR_OFFSET+0x00000030)
/** Offset of SMH Security Violation Register */
#define SMN_SEC_VIO_REG (SMN_ADDR_OFFSET+0x00000034)
/** Offset of SMH Timer Register */
#define SMN_TIMER_REG (SMN_ADDR_OFFSET+0x00000038)
/** Offset of SMH High-Assurance Control Register */
#define SMN_HAC_REG (SMN_ADDR_OFFSET+0x0000003c)
/** Number of bytes allocated to the SMN registers */
#define SMN_REG_BANK_SIZE 0x40
/** @} */
/** Number of bytes of total register space for the SCC. */
#define SCC_ADDRESS_RANGE (SMN_ADDR_OFFSET + SMN_REG_BANK_SIZE)
/**
* @defgroup smnstatusregdefs SMN Status Register definitions (SMN_STATUS)
*/
/** @addtogroup smnstatusregdefs */
/** @{ */
/** SMN version id. */
#define SMN_STATUS_VERSION_ID_MASK 0xfc000000
/** number of bits to shift #SMN_STATUS_VERSION_ID_MASK to get it to LSB */
#define SMN_STATUS_VERSION_ID_SHIFT 28
/** Illegal bus master access attempted. */
#define SMN_STATUS_ILLEGAL_MASTER 0x01000000
/** Scan mode entered/exited since last reset. */
#define SMN_STATUS_SCAN_EXIT 0x00800000
/** Some security peripheral is initializing */
#define SMN_STATUS_PERIP_INIT 0x00010000
/** Internal error detected in SMN. */
#define SMN_STATUS_SMN_ERROR 0x00004000
/** SMN has an outstanding interrupt. */
#define SMN_STATUS_SMN_STATUS_IRQ 0x00004000
/** Software Alarm was triggered. */
#define SMN_STATUS_SOFTWARE_ALARM 0x00002000
/** Timer has expired. */
#define SMN_STATUS_TIMER_ERROR 0x00001000
/** Plaintext/Ciphertext compare failed. */
#define SMN_STATUS_PC_ERROR 0x00000800
/** Bit Bank detected overflow or underflow */
#define SMN_STATUS_BITBANK_ERROR 0x00000400
/** Algorithm Sequence Check failed. */
#define SMN_STATUS_ASC_ERROR 0x00000200
/** Security Policy Block detected error. */
#define SMN_STATUS_SECURITY_POLICY_ERROR 0x00000100
/** Security Violation Active error. */
#define SMN_STATUS_SEC_VIO_ACTIVE_ERROR 0x00000080
/** Processor booted from internal ROM. */
#define SMN_STATUS_INTERNAL_BOOT 0x00000020
/** SMN's internal state. */
#define SMN_STATUS_STATE_MASK 0x0000001F
/** Number of bits to shift #SMN_STATUS_STATE_MASK to get it to LSB. */
#define SMN_STATUS_STATE_SHIFT 0
/** @} */
/**
* @defgroup sccscmstates SMN Model Secure State Controller States (SMN_STATE_MASK)
*/
/** @addtogroup sccscmstates */
/** @{ */
/** This is the first state of the SMN after power-on reset */
#define SMN_STATE_START 0x0
/** The SMN is zeroizing its RAM during reset */
#define SMN_STATE_ZEROIZE_RAM 0x5
/** SMN has passed internal checks, and is waiting for Software check-in */
#define SMN_STATE_HEALTH_CHECK 0x6
/** Fatal Security Violation. SMN is locked, SCM is inoperative. */
#define SMN_STATE_FAIL 0x9
/** SCC is in secure state. SCM is using secret key. */
#define SMN_STATE_SECURE 0xA
/** Due to non-fatal error, device is not secure. SCM is using default key. */
#define SMN_STATE_NON_SECURE 0xC
/** @} */
/** @{ */
/** SCM Status bit: Key Status is Default Key in Use */
#define SCM_STATUS_KST_DEFAULT_KEY 0x80000000
/** SCM Status bit: Key Status is (reserved) */
#define SCM_STATUS_KST_RESERVED1 0x40000000
/** SCM Status bit: Key status is Wrong Key */
#define SCM_STATUS_KST_WRONG_KEY 0x20000000
/** SCM Status bit: Bad Key detected */
#define SCM_STATUS_KST_BAD_KEY 0x10000000
/** SCM Status bit: Error has occurred */
#define SCM_STATUS_ERR 0x00008000
/** SCM Status bit: Monitor State is Failed */
#define SCM_STATUS_MSS_FAIL 0x00004000
/** SCM Status bit: Monitor State is Secure */
#define SCM_STATUS_MSS_SEC 0x00002000
/** SCM Status bit: Secure Storage is Failed */
#define SCM_STATUS_RSS_FAIL 0x00000400
/** SCM Status bit: Secure Storage is Secure */
#define SCM_STATUS_RSS_SEC 0x00000200
/** SCM Status bit: Secure Storage is Initializing */
#define SCM_STATUS_RSS_INIT 0x00000100
/** SCM Status bit: Unique Number Valid */
#define SCM_STATUS_UNV 0x00000080
/** SCM Status bit: Big Endian mode */
#define SCM_STATUS_BIG 0x00000040
/** SCM Status bit: Using Secret Key */
#define SCM_STATUS_USK 0x00000020
/** SCM Status bit: Ram is being blocked */
#define SCM_STATUS_BAR 0x00000010
/** Bit mask of SRS */
#define SCM_STATUS_SRS_MASK 0x0000000F
/** Number of bits to shift SRS to/from MSb */
#define SCM_STATUS_SRS_SHIFT 0
/** @} */
#define SCM_STATUS_SRS_RESET 0x0 /**< Reset, Zeroise All */
#define SCM_STATUS_SRS_READY 0x1 /**< All Ready */
#define SCM_STATUS_SRS_ZBUSY 0x2 /**< Zeroize Busy (Partition Only) */
#define SCM_STATUS_SRS_CBUSY 0x3 /**< Cipher Busy */
#define SCM_STATUS_SRS_ABUSY 0x4 /**< All Busy */
#define SCM_STATUS_SRS_ZDONE 0x5 /**< Zeroize Done, Cipher Ready */
#define SCM_STATUS_SRS_CDONE 0x6 /**< Cipher Done, Zeroize Ready */
#define SCM_STATUS_SRS_ZDONE2 0x7 /**< Zeroize Done, Cipher Busy */
#define SCM_STATUS_SRS_CDONE2 0x8 /**< Cipher Done, Zeroize Busy */
#define SCM_STATUS_SRS_ADONE 0xD /**< All Done */
#define SCM_STATUS_SRS_FAIL 0xF /**< Fail State */
/* Format of the SCM VERSION ID REGISTER */
#define SCM_VER_BPP_MASK 0xFF000000 /**< Bytes Per Partition Mask */
#define SCM_VER_BPP_SHIFT 24 /**< Bytes Per Partition Shift */
#define SCM_VER_BPCB_MASK 0x001F0000 /**< Bytes Per Cipher Block Mask */
#define SCM_VER_BPCB_SHIFT 16 /**< Bytes Per Cipher Block Shift */
#define SCM_VER_NP_MASK 0x0000F000 /**< Number of Partitions Mask */
#define SCM_VER_NP_SHIFT 12 /**< Number of Partitions Shift */
#define SCM_VER_MAJ_MASK 0x00000F00 /**< Major Version Mask */
#define SCM_VER_MAJ_SHIFT 8 /**< Major Version Shift */
#define SCM_VER_MIN_MASK 0x000000FF /**< Minor Version Mask */
#define SCM_VER_MIN_SHIFT 0 /**< Minor Version Shift */
/**< SCC Hardware version supported by this driver */
#define SCM_MAJOR_VERSION_2 2
/* Format of the SCM ERROR STATUS REGISTER */
#define SCM_ERRSTAT_MID_MASK 0x00F00000 /**< Master ID Mask */
#define SCM_ERRSTAT_MID_SHIFT 20 /**< Master ID Shift */
#define SCM_ERRSTAT_ILM 0x00080000 /**< Illegal Master */
#define SCM_ERRSTAT_SUP 0x00008000 /**< Supervisor Access */
#define SCM_ERRSTAT_ERC_MASK 0x00000F00 /**< Error Code Mask */
#define SCM_ERRSTAT_ERC_SHIFT 8 /**< Error Code Shift */
#define SCM_ERRSTAT_SMS_MASK 0x000000F0 /**< Secure Monitor State Mask */
#define SCM_ERRSTAT_SMS_SHIFT 4 /**< Secure Monitor State Shift */
#define SCM_ERRSTAT_SRS_MASK 0x0000000F /**< Secure Ram State Mask */
#define SCM_ERRSTAT_SRS_SHIFT 0 /**< Secure Ram State Shift */
/* SCM ERROR STATUS REGISTER ERROR CODES */
#define SCM_ERCD_UNK_ADDR 0x1 /**< Unknown Address */
#define SCM_ERCD_UNK_CMD 0x2 /**< Unknown Command */
#define SCM_ERCD_READ_PERM 0x3 /**< Read Permission Error */
#define SCM_ERCD_WRITE_PERM 0x4 /**< Write Permission Error */
#define SCM_ERCD_DMA_ERROR 0x5 /**< DMA Error */
#define SCM_ERCD_BLK_OVFL 0x6 /**< Encryption Block Length Overflow */
#define SCM_ERCD_NO_KEY 0x7 /**< Key Not Engaged */
#define SCM_ERCD_ZRZ_OVFL 0x8 /**< Zeroize Command Queue Overflow */
#define SCM_ERCD_CPHR_OVFL 0x9 /**< Cipher Command Queue Overflow */
#define SCM_ERCD_PROC_INTR 0xA /**< Process Interrupted */
#define SCM_ERCD_WRNG_KEY 0xB /**< Wrong Key */
#define SCM_ERCD_DEVICE_BUSY 0xC /**< Device Busy */
#define SCM_ERCD_UNALGN_ADDR 0xD /**< DMA Unaligned Address */
/* Format of the CIPHER COMMAND REGISTER */
#define SCM_CCMD_LENGTH_MASK 0xFFF00000 /**< Cipher Length Mask */
#define SCM_CCMD_LENGTH_SHIFT 20 /**< Cipher Length Shift */
#define SCM_CCMD_OFFSET_MASK 0x000FFF00 /**< Block Offset Mask */
#define SCM_CCMD_OFFSET_SHIFT 8 /**< Block Offset Shift */
#define SCM_CCMD_PART_MASK 0x000000F0 /**< Partition Number Mask */
#define SCM_CCMD_PART_SHIFT 4 /**< Partition Number Shift */
#define SCM_CCMD_CCMD_MASK 0x0000000F /**< Cipher Command Mask */
#define SCM_CCMD_CCMD_SHIFT 0 /**< Cipher Command Shift */
/* Values for SCM_CCMD_CCMD field */
#define SCM_CCMD_AES_DEC_ECB 1 /**< Decrypt without Chaining (ECB) */
#define SCM_CCMD_AES_ENC_ECB 3 /**< Encrypt without Chaining (ECB) */
#define SCM_CCMD_AES_DEC_CBC 5 /**< Decrypt with Chaining (CBC) */
#define SCM_CCMD_AES_ENC_CBC 7 /**< Encrypt with Chaining (CBC) */
#define SCM_CCMD_AES 1 /**< Use AES Mode */
#define SCM_CCMD_DEC 0 /**< Decrypt */
#define SCM_CCMD_ENC 2 /**< Encrypt */
#define SCM_CCMD_ECB 0 /**< Perform operation without chaining (ECB) */
#define SCM_CCMD_CBC 4 /**< Perform operation with chaining (CBC) */
/* Format of the ZEROIZE COMMAND REGISTER */
#define SCM_ZCMD_PART_MASK 0x000000F0 /**< Target Partition Mask */
#define SCM_ZCMD_PART_SHIFT 4 /**< Target Partition Shift */
#define SCM_ZCMD_CCMD_MASK 0x0000000F /**< Zeroize Command Mask */
#define SCM_ZCMD_CCMD_SHIFT 0 /**< Zeroize Command Shift */
/* MASTER ACCESS PERMISSIONS REGISTER */
/* Note that API users should use the FSL_PERM_ defines instead of these */
/** SCM Access Permission: Do not zeroize/deallocate partition
on SMN Fail state */
#define SCM_PERM_NO_ZEROIZE 0x10000000
/** SCM Access Permission: Ignore Supervisor/User mode
in permission determination */
#define SCM_PERM_HD_SUP_DISABLE 0x00000800
/** SCM Access Permission: Allow Read Access to Host Domain */
#define SCM_PERM_HD_READ 0x00000400
/** SCM Access Permission: Allow Write Access to Host Domain */
#define SCM_PERM_HD_WRITE 0x00000200
/** SCM Access Permission: Allow Execute Access to Host Domain */
#define SCM_PERM_HD_EXECUTE 0x00000100
/** SCM Access Permission: Allow Read Access to Trusted Host Domain */
#define SCM_PERM_TH_READ 0x00000040
/** SCM Access Permission: Allow Write Access to Trusted Host Domain */
#define SCM_PERM_TH_WRITE 0x00000020
/** SCM Access Permission: Allow Read Access to Other/World Domain */
#define SCM_PERM_OT_READ 0x00000004
/** SCM Access Permission: Allow Write Access to Other/World Domain */
#define SCM_PERM_OT_WRITE 0x00000002
/** SCM Access Permission: Allow Execute Access to Other/World Domain */
#define SCM_PERM_OT_EXECUTE 0x00000001
/**< Valid bits that can be set in the Permissions register */
#define SCM_PERM_MASK 0xC0000F67
/* Zeroize Command register definitions */
#define ZCMD_DEALLOC_PART 3 /**< Deallocate Partition */
#define Z_INT_EN 0x00000002 /**< Zero Interrupt Enable */
/**
* @defgroup scmpartitionownersregdefs SCM Partition Owners Register
*/
/** @addtogroup scmpartitionownersregdefs */
/** @{ */
/** Number of bits to shift partition number to get to its field. */
#define SCM_POWN_SHIFT 2
/** Mask for a field once the register has been shifted. */
#define SCM_POWN_MASK 3
/** Partition is free */
#define SCM_POWN_PART_FREE 0
/** Partition is unable to be allocated */
#define SCM_POWN_PART_UNUSABLE 1
/** Partition is owned by another master */
#define SCM_POWN_PART_OTHER 2
/** Partition is owned by this master */
#define SCM_POWN_PART_OWNED 3
/** @} */
/**
* @defgroup smnpartitionsengagedregdefs SCM Partitions Engaged Register
*/
/** @addtogroup smnpartitionsengagedregdefs */
/** @{ */
/** Number of bits to shift partition number to get to its field. */
#define SCM_PENG_SHIFT 1
/** Engaged value for a field once the register has been shifted. */
#define SCM_PENG_ENGAGED 1
/** @} */
/** Number of bytes between each subsequent SMID register */
#define SCM_SMID_WIDTH 8
/**
* @defgroup smncommandregdefs SMN Command Register Definitions (SMN_COMMAND_REG)
*/
/** @addtogroup smncommandregdefs */
/** @{ */
/** These bits are unimplemented or reserved */
#define SMN_COMMAND_ZEROS_MASK 0xfffffff0
#define SMN_COMMAND_CLEAR_INTERRUPT 0x8 /**< Clear SMN Interrupt */
#define SMN_COMMAND_CLEAR_BIT_BANK 0x4 /**< Clear SMN Bit Bank */
#define SMN_COMMAND_ENABLE_INTERRUPT 0x2 /**< Enable SMN Interrupts */
#define SMN_COMMAND_SET_SOFTWARE_ALARM 0x1 /**< Set Software Alarm */
/** @} */
/**
* @defgroup smntimercontroldefs SMN Timer Control Register definitions (SMN_TIMER_CONTROL)
*/
/** @addtogroup smntimercontroldefs */
/** @{ */
/** These bits are reserved or zero */
#define SMN_TIMER_CTRL_ZEROS_MASK 0xfffffffc
/** Load the timer from #SMN_TIMER_IV_REG */
#define SMN_TIMER_LOAD_TIMER 0x2
/** Setting to zero stops the Timer */
#define SMN_TIMER_STOP_MASK 0x1
/** Setting this value starts the timer */
#define SMN_TIMER_START_TIMER 0x1
/** @} */
/**
* @defgroup scmchainmodedefs SCM_CHAINING_MODE_MASK - Bit definitions
*/
/** @addtogroup scmchainmodedefs */
/** @{ */
#define SCM_CBC_MODE 0x2 /**< Cipher block chaining */
#define SCM_ECB_MODE 0x0 /**< Electronic codebook. */
/** @} */
/* Bit definitions in the SCM_CIPHER_MODE_MASK */
/**
* @defgroup scmciphermodedefs SCM_CIPHER_MODE_MASK - Bit definitions
*/
/** @addtogroup scmciphermodedefs */
/** @{ */
#define SCM_DECRYPT_MODE 0x1 /**< decrypt from black to red memory */
#define SCM_ENCRYPT_MODE 0x0 /**< encrypt from red to black memory */
/** @} */
/**
* @defgroup smndbgdetdefs SMN Debug Detector Status Register (SCM_DEBUG_DETECT_STAT)
*/
/** @addtogroup smndbgdetdefs */
/** @{ */
#define SMN_DBG_ZEROS_MASK 0xfffff000 /**< These bits are zero or reserved */
#define SMN_DBG_D12 0x0800 /**< Error detected on Debug Port D12 */
#define SMN_DBG_D11 0x0400 /**< Error detected on Debug Port D11 */
#define SMN_DBG_D10 0x0200 /**< Error detected on Debug Port D10 */
#define SMN_DBG_D9 0x0100 /**< Error detected on Debug Port D9 */
#define SMN_DBG_D8 0x0080 /**< Error detected on Debug Port D8 */
#define SMN_DBG_D7 0x0040 /**< Error detected on Debug Port D7 */
#define SMN_DBG_D6 0x0020 /**< Error detected on Debug Port D6 */
#define SMN_DBG_D5 0x0010 /**< Error detected on Debug Port D5 */
#define SMN_DBG_D4 0x0008 /**< Error detected on Debug Port D4 */
#define SMN_DBG_D3 0x0004 /**< Error detected on Debug Port D3 */
#define SMN_DBG_D2 0x0002 /**< Error detected on Debug Port D2 */
#define SMN_DBG_D1 0x0001 /**< Error detected on Debug Port D1 */
/** @} */
/** Mask for the usable bits of the Sequence Start Register
(#SMN_SEQ_START_REG) */
#define SMN_SEQUENCE_START_MASK 0x0000ffff
/** Mask for the usable bits of the Sequence End Register
(#SMN_SEQ_END_REG) */
#define SMN_SEQUENCE_END_MASK 0x0000ffff
/** Mask for the usable bits of the Sequence Check Register
(#SMN_SEQ_CHECK_REG) */
#define SMN_SEQUENCE_CHECK_MASK 0x0000ffff
/** Mask for the usable bits of the Bit Counter Register
(#SMN_BB_CNT_REG) */
#define SMN_BIT_COUNT_MASK 0x000007ff
/** Mask for the usable bits of the Bit Bank Increment Size Register
(#SMN_BB_INC_REG) */
#define SMN_BITBANK_INC_SIZE_MASK 0x000007ff
/** Mask for the usable bits of the Bit Bank Decrement Register
(#SMN_BB_DEC_REG) */
#define SMN_BITBANK_DECREMENT_MASK 0x000007ff
/** Mask for the usable bits of the Compare Size Register
(#SMN_COMPARE_REG) */
#define SMN_COMPARE_SIZE_MASK 0x0000003f
/*! @} */
#endif /* SCC_DRIVER_H */

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/*
* linux/drivers/char/mxc_si4702.h
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @defgroup Character device driver for SI4702 FM radio
*/
/*
* @file mxc_si4702.h
*
* @brief SI4702 Radio FM driver
*
* @ingroup Character
*/
#ifndef _MXC_SI4702_FM_H
#define _MXC_SI4702_FM_H
/* define IOCTL command */
#define SI4702_GETVOLUME _IOR('S', 0x10, unsigned int)
#define SI4702_SETVOLUME _IOW('S', 0x11, unsigned int)
#define SI4702_MUTEON _IO('S', 0x12)
#define SI4702_MUTEOFF _IO('S', 0x13)
#define SI4702_SELECT _IOW('S', 0x14, unsigned int)
#define SI4702_SEEK _IOWR('S', 0x15, unsigned int)
#endif /* _MXC_SI4702_FM_H */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mxc_sim_interface.h
*
* @brief Driver for Freescale IMX SIM interface
*
*/
#ifndef MXC_SIM_INTERFACE_H
#define MXC_SIM_INTERFACE_H
#define SIM_ATR_LENGTH_MAX 32
/* Raw ATR SIM_IOCTL_GET_ATR */
typedef struct {
uint32_t size; /* length of ATR received */
uint8_t t[SIM_ATR_LENGTH_MAX]; /* raw ATR string received */
} sim_atr_t;
/* Communication parameters for SIM_IOCTL_[GET|SET]_PARAM */
typedef struct {
uint8_t convention; /* direct = 0, indirect = 1 */
uint8_t FI, DI; /* frequency multiplier and devider indices */
uint8_t PI1, II; /* programming voltage and current indices */
uint8_t N; /* extra guard time */
uint8_t T; /* protocol type: T0 = 0, T1 = 1 */
uint8_t PI2; /* programming voltage 2 value */
uint8_t WWT; /* working wait time */
} sim_param_t;
/* ISO7816-3 protocols */
#define SIM_PROTOCOL_T0 0
#define SIM_PROTOCOL_T1 1
/* Transfer data for SIM_IOCTL_XFER */
typedef struct {
uint8_t *xmt_buffer; /* transmit buffer pointer */
int32_t xmt_length; /* transmit buffer length */
uint8_t *rcv_buffer; /* receive buffer pointer */
int32_t rcv_length; /* receive buffer length */
int type; /* transfer type: TPDU = 0, PTS = 1 */
int timeout; /* transfer timeout in milliseconds */
uint8_t sw1; /* status word 1 */
uint8_t sw2; /* status word 2 */
} sim_xfer_t;
/* Transfer types for SIM_IOCTL_XFER */
#define SIM_XFER_TYPE_TPDU 0
#define SIM_XFER_TYPE_PTS 1
/* Interface power states */
#define SIM_POWER_OFF 0
#define SIM_POWER_ON 1
/* Return values for SIM_IOCTL_GET_PRESENSE */
#define SIM_PRESENT_REMOVED 0
#define SIM_PRESENT_DETECTED 1
#define SIM_PRESENT_OPERATIONAL 2
/* Return values for SIM_IOCTL_GET_ERROR */
#define SIM_OK 0
#define SIM_E_ACCESS 1
#define SIM_E_TPDUSHORT 2
#define SIM_E_PTSEMPTY 3
#define SIM_E_INVALIDXFERTYPE 4
#define SIM_E_INVALIDXMTLENGTH 5
#define SIM_E_INVALIDRCVLENGTH 6
#define SIM_E_NACK 7
#define SIM_E_TIMEOUT 8
#define SIM_E_NOCARD 9
#define SIM_E_PARAM_FI_INVALID 10
#define SIM_E_PARAM_DI_INVALID 11
#define SIM_E_PARAM_FBYD_WITHFRACTION 12
#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 13
#define SIM_E_PARAM_DIVISOR_RANGE 14
#define SIM_E_MALLOC 15
#define SIM_E_IRQ 16
#define SIM_E_POWERED_ON 17
#define SIM_E_POWERED_OFF 18
/* ioctl encodings */
#define SIM_IOCTL_BASE 0xc0
#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int)
#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t)
#define SIM_IOCTL_GET_PARAM_ATR _IOR(SIM_IOCTL_BASE, 3, sim_param_t)
#define SIM_IOCTL_GET_PARAM _IOR(SIM_IOCTL_BASE, 4, sim_param_t)
#define SIM_IOCTL_SET_PARAM _IOW(SIM_IOCTL_BASE, 5, sim_param_t)
#define SIM_IOCTL_XFER _IOR(SIM_IOCTL_BASE, 6, sim_xfer_t)
#define SIM_IOCTL_POWER_ON _IO(SIM_IOCTL_BASE, 7)
#define SIM_IOCTL_POWER_OFF _IO(SIM_IOCTL_BASE, 8)
#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 9)
#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 10)
#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 11)
#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 12)
#endif

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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU Lesser General
* Public License. You may obtain a copy of the GNU Lesser General
* Public License Version 2.1 or later at the following locations:
*
* http://www.opensource.org/licenses/lgpl-license.html
* http://www.gnu.org/copyleft/lgpl.html
*/
/*!
* @file arch-mxc/mxc_v4l2.h
*
* @brief mxc V4L2 private structures
*
* @ingroup MXC_V4L2_CAPTURE
*/
#ifndef __ASM_ARCH_MXC_V4L2_H__
#define __ASM_ARCH_MXC_V4L2_H__
/*
* For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID.
* And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3.
*/
#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0)
#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1)
#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2)
#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3)
#define V4L2_MXC_ROTATE_NONE 0
#define V4L2_MXC_ROTATE_VERT_FLIP 1
#define V4L2_MXC_ROTATE_HORIZ_FLIP 2
#define V4L2_MXC_ROTATE_180 3
#define V4L2_MXC_ROTATE_90_RIGHT 4
#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5
#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6
#define V4L2_MXC_ROTATE_90_LEFT 7
struct v4l2_mxc_offset {
uint32_t u_offset;
uint32_t v_offset;
};
#endif

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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU Lesser General
* Public License. You may obtain a copy of the GNU Lesser General
* Public License Version 2.1 or later at the following locations:
*
* http://www.opensource.org/licenses/lgpl-license.html
* http://www.gnu.org/copyleft/lgpl.html
*/
/*
* @file arch-mxc/ mxcfb.h
*
* @brief Global header file for the MXC Frame buffer
*
* @ingroup Framebuffer
*/
#ifndef __ASM_ARCH_MXCFB_H__
#define __ASM_ARCH_MXCFB_H__
#include <linux/fb.h>
#define FB_SYNC_OE_LOW_ACT 0x80000000
#define FB_SYNC_CLK_LAT_FALL 0x40000000
#define FB_SYNC_DATA_INVERT 0x20000000
#define FB_SYNC_CLK_IDLE_EN 0x10000000
#define FB_SYNC_SHARP_MODE 0x08000000
#define FB_SYNC_SWAP_RGB 0x04000000
struct mxcfb_gbl_alpha {
int enable;
int alpha;
};
struct mxcfb_loc_alpha {
int enable;
int alpha_in_pixel;
unsigned long alpha_phy_addr0;
unsigned long alpha_phy_addr1;
};
struct mxcfb_color_key {
int enable;
__u32 color_key;
};
struct mxcfb_pos {
__u16 x;
__u16 y;
};
struct mxcfb_gamma {
int enable;
int constk[16];
int slopek[16];
};
#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos)
#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t)
#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha)
#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long)
#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma)
#ifdef __KERNEL__
extern struct fb_videomode mxcfb_modedb[];
extern int mxcfb_modedb_sz;
enum {
MXCFB_REFRESH_OFF,
MXCFB_REFRESH_AUTO,
MXCFB_REFRESH_PARTIAL,
};
struct mxcfb_rect {
u32 top;
u32 left;
u32 width;
u32 height;
};
int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
struct mxcfb_rect *update_region);
#endif /* __KERNEL__ */
#endif