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be0524d38f
This is i.MX BSP 5.0.0 release ported to 2.6.31 Signed-off-by: Rob Herring <r.herring@freescale.com> Signed-off-by: Alan Tull <r80115@freescale.com> Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/*
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* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/**
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* @file sah_hardware_interface.h
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*
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* @brief Provides an interface to the SAHARA hardware registers.
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*
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*/
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#ifndef SAH_HARDWARE_INTERFACE_H
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#define SAH_HARDWARE_INTERFACE_H
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#include <sah_driver_common.h>
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#include <sah_status_manager.h>
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/* These values can be used with sah_HW_Write_Control(). */
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#ifdef SAHARA1
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/** Define platform as Little-Endian */
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#define CTRL_LITTLE_END 0x00000002
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/** Bit to cause endian change in transfers */
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#define CTRL_INT_EN 0x00000004
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/** Set High Assurance mode */
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#define CTRL_HA 0x00000008
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#else
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/** Bit to cause byte swapping in (data?) transfers */
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#define CTRL_BYTE_SWAP 0x00000001
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/** Bit to cause halfword swapping in (data?) transfers */
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#define CTRL_HALFWORD_SWAP 0x00000002
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/** Bit to cause endian change in (data?) transfers */
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#define CTRL_INT_EN 0x00000010
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/** Set High Assurance mode */
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#define CTRL_HA 0x00000020
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/** Disable High Assurance */
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#define CTRL_HA_DISABLE 0x00000040
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/** Reseed the RNG CHA */
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#define CTRL_RNG_RESEED 0x00000080
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#endif
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/* These values can be used with sah_HW_Write_Command(). */
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/** Reset the Sahara */
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#define CMD_RESET 0x00000001
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/** Set Sahara into Batch mode. */
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#define CMD_BATCH 0x00010000
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/** Clear the Sahara interrupt */
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#define CMD_CLR_INT_BIT 0x00000100
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/** Clear the Sahara error */
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#define CMD_CLR_ERROR_BIT 0x00000200
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/** error status register contains error */
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#define STATUS_ERROR 0x00000010
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/** Op status register contains op status */
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#define OP_STATUS 0x00000020
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/* High Level functions */
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int sah_HW_Reset(void);
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fsl_shw_return_t sah_HW_Set_HA(void);
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sah_Execute_Status sah_Wait_On_Sahara(void);
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/* Low Level functions */
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uint32_t sah_HW_Read_Version(void);
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uint32_t sah_HW_Read_Control(void);
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uint32_t sah_HW_Read_Status(void);
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uint32_t sah_HW_Read_Error_Status(void);
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uint32_t sah_HW_Read_Op_Status(void);
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uint32_t sah_HW_Read_DAR(void);
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uint32_t sah_HW_Read_CDAR(void);
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uint32_t sah_HW_Read_IDAR(void);
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uint32_t sah_HW_Read_Fault_Address(void);
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uint32_t sah_HW_Read_MM_Status(void);
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uint32_t sah_HW_Read_Config(void);
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void sah_HW_Write_Command(uint32_t command);
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void sah_HW_Write_Control(uint32_t control);
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void sah_HW_Write_DAR(uint32_t pointer);
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void sah_HW_Write_Config(uint32_t configuration);
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#if defined DIAG_DRV_IF || defined(DO_DBG)
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void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr,
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unsigned length);
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#endif
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#endif /* SAH_HARDWARE_INTERFACE_H */
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/* End of sah_hardware_interface.c */
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