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cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags

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CPUState::singlestep_enabled contains multiple flags since
commit 60897d369f ("Debugger single step without interrupts").
Use an unsigned type and rename the field to avoid mistakes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-32-philmd@oss.qualcomm.com>
This commit is contained in:
Philippe Mathieu-Daudé
2026-06-26 14:25:28 +02:00
parent 0a8bc0f251
commit 7e28b7c897
7 changed files with 21 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
accel/kvm/kvm-all.c
View File

@@ -3815,7 +3815,7 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap)
if (cpu_single_stepping(cpu)) {
data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
if (cpu->singlestep_enabled & SSTEP_NOIRQ) {
if (cpu->singlestep_flags & SSTEP_NOIRQ) {
data.dbg.control |= KVM_GUESTDBG_BLOCKIRQ;
}
}

2
accel/tcg/cpu-exec.c
View File

@@ -828,7 +828,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
return true;
}
if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
if (unlikely(cpu->singlestep_flags & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}

2
accel/tcg/tcg-accel-ops-rr.c
View File

@@ -274,7 +274,7 @@ static void *rr_cpu_thread_fn(void *arg)
current_cpu = cpu;
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
(cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
(cpu->singlestep_flags & SSTEP_NOTIMER) == 0);
if (cpu_can_run(cpu)) {
int r;

8
cpu-target.c
View File

@@ -28,12 +28,12 @@
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)
void cpu_single_step(CPUState *cpu, unsigned flags)
{
if (cpu->singlestep_enabled != enabled) {
if (cpu->singlestep_flags != flags) {
trace_cpu_change_singlestep_flags(cpu->cpu_index,
cpu->singlestep_enabled, enabled);
cpu->singlestep_enabled = enabled;
cpu->singlestep_flags, flags);
cpu->singlestep_flags = flags;
#if !defined(CONFIG_USER_ONLY)
const AccelOpsClass *ops = cpus_get_accel();

10
include/hw/core/cpu.h
View File

@@ -440,7 +440,7 @@ struct qemu_work_item;
* @stopped: Indicates the CPU has been artificially stopped.
* @unplug: Indicates a pending CPU unplug request.
* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
* @singlestep_enabled: Flags for single-stepping.
* @singlestep_flags: Flags for single-stepping.
* @icount_extra: Instructions until next timer event.
* @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
* AddressSpaces this CPU has)
@@ -505,7 +505,7 @@ struct CPUState {
int exclusive_context_count;
uint32_t cflags_next_tb;
uint32_t interrupt_request;
int singlestep_enabled;
unsigned singlestep_flags;
int64_t icount_budget;
int64_t icount_extra;
uint64_t random_seed;
@@ -1132,11 +1132,11 @@ void qemu_init_vcpu(CPUState *cpu);
/**
* cpu_single_step:
* @cpu: CPU to the flags for.
* @enabled: Flags to enable.
* @flags: Flags to enable.
*
* Enables or disables single-stepping for @cpu.
*/
void cpu_single_step(CPUState *cpu, int enabled);
void cpu_single_step(CPUState *cpu, unsigned flags);
/**
* cpu_single_stepping:
@@ -1146,7 +1146,7 @@ void cpu_single_step(CPUState *cpu, int enabled);
*/
static inline bool cpu_single_stepping(const CPUState *cpu)
{
return cpu->singlestep_enabled;
return cpu->singlestep_flags;
}
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,

2
target/arm/hvf/hvf.c
View File

@@ -2603,7 +2603,7 @@ int hvf_arch_vcpu_exec(CPUState *cpu)
flush_cpu_state(cpu);
do {
if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) &&
if (!(cpu->singlestep_flags & SSTEP_NOIRQ) &&
hvf_inject_interrupts(cpu)) {
return EXCP_INTERRUPT;
}

16
target/ppc/translate.c
View File

@@ -198,7 +198,7 @@ struct DisasContext {
bool pmu_insn_cnt;
bool bhrb_enable;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
int singlestep_flags;
uint32_t flags;
uint64_t insns_flags;
uint64_t insns_flags2;
@@ -367,7 +367,7 @@ static void gen_debug_exception(DisasContext *ctx, bool rfi_type)
#if !defined(CONFIG_USER_ONLY)
if (ctx->flags & POWERPC_FLAG_DE) {
target_ulong dbsr = 0;
if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
if (ctx->singlestep_flags & CPU_SINGLE_STEP) {
dbsr = DBCR0_ICMP;
} else {
/* Must have been branch */
@@ -3645,7 +3645,7 @@ static void pmu_count_insns(DisasContext *ctx)
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
if (unlikely(ctx->singlestep_enabled)) {
if (unlikely(ctx->singlestep_flags)) {
return false;
}
return translator_use_goto_tb(&ctx->base, dest);
@@ -3653,7 +3653,7 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
{
if (unlikely(ctx->singlestep_enabled)) {
if (unlikely(ctx->singlestep_flags)) {
gen_debug_exception(ctx, false);
} else {
/*
@@ -6559,13 +6559,13 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1;
ctx->singlestep_enabled = 0;
ctx->singlestep_flags = 0;
if ((hflags >> HFLAGS_SE) & 1) {
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
ctx->singlestep_flags |= CPU_SINGLE_STEP;
ctx->base.max_insns = 1;
}
if ((hflags >> HFLAGS_BE) & 1) {
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
ctx->singlestep_flags |= CPU_BRANCH_STEP;
}
}
@@ -6641,7 +6641,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
}
/* Honor single stepping. */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) {
if (unlikely(ctx->singlestep_flags & CPU_SINGLE_STEP)) {
bool rfi_type = false;
switch (is_jmp) {