starred/qemu-qemu-1
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2026-07-08 17:56:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: decode Octeon CHORD and LLM COP2 selectors

Browse Source 
Add explicit decodetree entries and translator bindings for the Octeon
CHORD and sparse LLM COP2 selectors.  CHORD and LLM use their own COP2
selector window rather than the crypto engine windows covered by the
preceding decode patches.

This completes the explicit COP2 selector coverage by adding the
remaining CHORD and LLM register and operation selectors.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-19-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
This commit is contained in:
James Hilliard
2026-06-08 12:59:44 -06:00
committed by Philippe Mathieu-Daudé
parent ec931476cd
commit 8d399e3e03
2 changed files with 26 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
target/mips/tcg/octeon.decode
View File

@@ -167,6 +167,9 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 1010 &cp2
CVM_MF_GFM_RESINP1 010010 00001 rt:5 0000 0010 0101 1011 &cp2
CVM_MF_GFM_POLY 010010 00001 rt:5 0000 0010 0101 1110 &cp2
CVM_MF_CHORD 010010 00001 rt:5 0000 0100 0000 0000 &cp2
CVM_MF_LLM_DATA0 010010 00001 rt:5 0000 0100 0000 0010 &cp2
CVM_MF_LLM_DATA1 010010 00001 rt:5 0000 0100 0000 1010 &cp2
CVM_MT_HSH_DAT0 010010 00101 rt:5 0000 0000 0100 0000 &cp2
CVM_MT_HSH_DAT1 010010 00101 rt:5 0000 0000 0100 0001 &cp2
CVM_MT_HSH_DAT2 010010 00101 rt:5 0000 0000 0100 0010 &cp2
@@ -261,6 +264,16 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 1111 &cp2
CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 0000 &cp2
CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 0001 &cp2
CVM_MT_LLM_READ_ADDR0 010010 00101 rt:5 0000 0100 0000 0000 &cp2
CVM_MT_LLM_WRITE_ADDR0 010010 00101 rt:5 0000 0100 0000 0001 &cp2
CVM_MT_LLM_DATA0 010010 00101 rt:5 0000 0100 0000 0010 &cp2
CVM_MT_LLM_READ64_ADDR0 010010 00101 rt:5 0000 0100 0000 0100 &cp2
CVM_MT_LLM_WRITE64_ADDR0 010010 00101 rt:5 0000 0100 0000 0101 &cp2
CVM_MT_LLM_READ_ADDR1 010010 00101 rt:5 0000 0100 0000 1000 &cp2
CVM_MT_LLM_WRITE_ADDR1 010010 00101 rt:5 0000 0100 0000 1001 &cp2
CVM_MT_LLM_DATA1 010010 00101 rt:5 0000 0100 0000 1010 &cp2
CVM_MT_LLM_READ64_ADDR1 010010 00101 rt:5 0000 0100 0000 1100 &cp2
CVM_MT_LLM_WRITE64_ADDR1 010010 00101 rt:5 0000 0100 0000 1101 &cp2
CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 0010 &cp2
CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 0111 &cp2
CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 1000 &cp2

13
target/mips/tcg/octeon_translate.c
View File

@@ -235,6 +235,9 @@ CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]);
CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]);
CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]);
CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly);
CP2_MF_I64(CVM_MF_CHORD, chord);
CP2_MF_I64(CVM_MF_LLM_DATA0, llm_data[0]);
CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]);
CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24);
@@ -306,6 +309,8 @@ CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]);
CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]);
CP2_MT_XOR_I64(CVM_MT_GFM_XOR0, gfm_resinp[0]);
CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly);
CP2_MT_I64(CVM_MT_LLM_DATA0, llm_data[0]);
CP2_MT_I64(CVM_MT_LLM_DATA1, llm_data[1]);
CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf);
CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly);
@@ -395,6 +400,14 @@ CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512);
CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0);
CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0);
CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0);
CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0);
CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1);
CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1);
CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1);
CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1);
static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
{