target/or1k: Use XML register definitions from GDB

Import gdb-xml/or1k-fpu.xml from mainstream binutils, tag
'binutils-2_46' [*]. Register as CPUClass::gdb_core_xml_file.

[*] https://sourceware.org/git/?p=binutils-gdb.git;a=blob_plain;f=gdb/features/or1k-core.xml;h=0d13f355f5296ae426794eb3003dcc18fbbd49d5;hb=refs/tags/binutils-2_46

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260219191955.83815-23-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2026-02-17 08:19:27 +01:00
parent c91f3330cc
commit aa75a7c09b
5 changed files with 69 additions and 1 deletions

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@@ -304,6 +304,7 @@ M: Stafford Horne <shorne@gmail.com>
S: Odd Fixes
F: docs/system/or1k/cpu-features.rst
F: target/or1k/
F: gdb-xml/or1k-core.xml
F: hw/or1k/
F: include/hw/or1k/
F: tests/functional/or1k/meson.build

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@@ -2,5 +2,6 @@ TARGET_ARCH=or1k
TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat
TARGET_SYSTBL=syscall.tbl
TARGET_XML_FILES= gdb-xml/or1k-core.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y

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@@ -2,6 +2,7 @@ TARGET_ARCH=or1k
TARGET_BIG_ENDIAN=y
# needed by boot.c and all boards
TARGET_NEED_FDT=y
TARGET_XML_FILES= gdb-xml/or1k-core.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y

65
gdb-xml/or1k-core.xml Normal file
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@@ -0,0 +1,65 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2017-2026 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.or1k.group0">
<reg name="r0" bitsize="32" type="int"/>
<reg name="r1" bitsize="32" type="data_ptr"/>
<reg name="r2" bitsize="32" type="data_ptr"/>
<reg name="r3" bitsize="32" type="int"/>
<reg name="r4" bitsize="32" type="int"/>
<reg name="r5" bitsize="32" type="int"/>
<reg name="r6" bitsize="32" type="int"/>
<reg name="r7" bitsize="32" type="int"/>
<reg name="r8" bitsize="32" type="int"/>
<reg name="r9" bitsize="32" type="code_ptr"/>
<reg name="r10" bitsize="32" type="int"/>
<reg name="r11" bitsize="32" type="int"/>
<reg name="r12" bitsize="32" type="int"/>
<reg name="r13" bitsize="32" type="int"/>
<reg name="r14" bitsize="32" type="int"/>
<reg name="r15" bitsize="32" type="int"/>
<reg name="r16" bitsize="32" type="int"/>
<reg name="r17" bitsize="32" type="int"/>
<reg name="r18" bitsize="32" type="int"/>
<reg name="r19" bitsize="32" type="int"/>
<reg name="r20" bitsize="32" type="int"/>
<reg name="r21" bitsize="32" type="int"/>
<reg name="r22" bitsize="32" type="int"/>
<reg name="r23" bitsize="32" type="int"/>
<reg name="r24" bitsize="32" type="int"/>
<reg name="r25" bitsize="32" type="int"/>
<reg name="r26" bitsize="32" type="int"/>
<reg name="r27" bitsize="32" type="int"/>
<reg name="r28" bitsize="32" type="int"/>
<reg name="r29" bitsize="32" type="int"/>
<reg name="r30" bitsize="32" type="int"/>
<reg name="r31" bitsize="32" type="int"/>
<reg name="ppc" bitsize="32" type="code_ptr"/>
<reg name="npc" bitsize="32" type="code_ptr"/>
<flags id="sr_flags" size="4">
<field name="SM" start="0" end="0"/>
<field name="TEE" start="1" end="1"/>
<field name="IEE" start="2" end="2"/>
<field name="DCE" start="3" end="3"/>
<field name="ICE" start="4" end="4"/>
<field name="DME" start="5" end="5"/>
<field name="IME" start="6" end="6"/>
<field name="LEE" start="7" end="7"/>
<field name="CE" start="8" end="8"/>
<field name="F" start="9" end="9"/>
<field name="CY" start="10" end="10"/>
<field name="OV" start="11" end="11"/>
<field name="OVE" start="12" end="12"/>
<field name="DSX" start="13" end="13"/>
<field name="EPH" start="14" end="14"/>
<field name="FO" start="15" end="15"/>
<field name="SUMRA" start="16" end="16"/>
<field name="CID" start="28" end="31"/>
</flags>
<reg name="sr" bitsize="32" type="sr_flags"/>
</feature>

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@@ -288,13 +288,13 @@ static void openrisc_cpu_class_init(ObjectClass *oc, const void *data)
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->get_pc = openrisc_cpu_get_pc;
cc->gdb_core_xml_file = "or1k-core.xml";
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
cc->tcg_ops = &openrisc_tcg_ops;
}