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hw/timer/imx_epit: Replace DPRINTF with trace events
Clean up the codebase by removing the outdated DEBUG_IMX_EPIT
and DPRINTF macros, replacing them with modern QEMU trace events.
This also removes an empty and meaningless DPRINTF("\n") in the
imx_epit_realize function.
Signed-off-by: jack wang <163wangjack@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-id: 20260617161406.14705-1-163wangjack@gmail.com
[PMM: remove stray blank lines from bottom of trace-events file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
@@ -20,18 +20,7 @@
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#include "hw/misc/imx_ccm.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#ifndef DEBUG_IMX_EPIT
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#define DEBUG_IMX_EPIT 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_EPIT) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \
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__func__, ##args); \
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} \
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} while (0)
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#include "trace.h"
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static const char *imx_epit_reg_name(uint32_t reg)
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{
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@@ -80,7 +69,7 @@ static uint32_t imx_epit_get_freq(IMXEPITState *s)
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uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
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uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
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uint32_t freq = f_in / prescaler;
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DPRINTF("ptimer frequency is %u\n", freq);
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trace_imx_epit_get_freq(freq);
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return freq;
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}
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@@ -146,8 +135,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
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HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
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break;
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}
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DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value);
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trace_imx_epit_read(imx_epit_reg_name(offset >> 2), reg_value);
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return reg_value;
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}
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@@ -328,8 +316,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
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{
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IMXEPITState *s = IMX_EPIT(opaque);
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DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
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(uint32_t)value);
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trace_imx_epit_write(imx_epit_reg_name(offset >> 2), value);
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switch (offset >> 2) {
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case 0: /* CR */
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@@ -362,7 +349,7 @@ static void imx_epit_cmp(void *opaque)
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/* The cmp ptimer can't be running when the peripheral is disabled */
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assert(s->cr & CR_EN);
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DPRINTF("sr was %d\n", s->sr);
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trace_imx_epit_cmp(s->sr);
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/* Set interrupt status bit SR.OCIF and update the interrupt state */
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s->sr |= SR_OCIF;
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imx_epit_update_int(s);
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@@ -399,8 +386,6 @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
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IMXEPITState *s = IMX_EPIT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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DPRINTF("\n");
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
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0x00001000);
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@@ -122,3 +122,9 @@ hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8
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hpet_ram_write_invalid_tn_cmp(void) "invalid HPET_TN_CMP + 4 write"
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hpet_ram_write_invalid(void) "invalid hpet_ram_writel"
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hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!"
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# imx_epit.c
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imx_epit_get_freq(uint32_t freq) "ptimer frequency is %u"
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imx_epit_read(const char *name, uint32_t value) "(%s) = 0x%08x"
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imx_epit_write(const char *name, uint64_t value) "(%s, value = 0x%08" PRIx64 ")"
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imx_epit_cmp(uint32_t sr) "sr was %d"
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