docs: Be consistent about capitalization of 'Arm' (again)

The company 'Arm' went through a rebranding many years back involving a recapitalization from 'ARM' to 'Arm'. As a result our documentation is a bit inconsistent between the two forms. It's not worth trying to update everywhere in QEMU, but it's easy enough to make docs/ consistent. We last did this in commit 6fe6d6c9a in 2020, but a few new uses of the wrong capitalization have crept back in since. As before, "ARMv8" and similar architecture names, and older CPU names like "ARM926" still retain all-caps. In a few places we make minor grammar fixups as we touch the sentences we're fixing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260115150545.669444-1-peter.maydell@linaro.org
2026-02-04 02:24:51 +00:00 · 2026-01-15 15:05:45 +00:00
parent d9aa110bf1
commit d154001f5a
10 changed files with 28 additions and 28 deletions
--- a/docs/devel/testing/qgraph.rst
+++ b/docs/devel/testing/qgraph.rst
@@ -8,7 +8,7 @@ take care of booting QEMU with the right machine and devices.
 This makes each test "hardcoded" for a specific configuration, reducing
 the possible coverage that it can reach.

-For example, the sdhci device is supported on both x86_64 and ARM boards,
+For example, the sdhci device is supported on both x86_64 and Arm boards,
 therefore a generic sdhci test should test all machines and drivers that
 support that device.
 Using only libqos APIs, the test has to manually take care of
@@ -195,7 +195,7 @@ there.
 The ``arm/raspi2b`` machine node is listed as "UNAVAILABLE". Although it is
 reachable from the root via '' -> 'arm/raspi2b' the node is unavailable because
 the QEMU binary did not list it when queried by the framework. This is expected
-because we used the ``qemu-system-x86_64`` binary which does not support ARM
+because we used the ``qemu-system-x86_64`` binary which does not support Arm
 machine types.

 If a test is unexpectedly listed as "UNAVAILABLE", first check that the "ALL
@@ -214,9 +214,9 @@ Here we continue the ``sdhci`` use case, with the following scenario:

 - ``sdhci-test`` aims to test the ``read[q,w], writeq`` functions
  offered by the ``sdhci`` drivers.
- The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``ARM``
+- The current ``sdhci`` device is supported by both ``x86_64/pc`` and Arm
  (in this example we focus on the ``arm-raspi2b``) machines.
- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``ARM`` and
+- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for Arm and
  ``QSDHCI_PCI`` for ``x86_64/pc``. Both implement the
  ``read[q,w], writeq`` functions.

--- a/docs/devel/vfio-iommufd.rst
+++ b/docs/devel/vfio-iommufd.rst
@@ -122,7 +122,7 @@ container:
 Supported platform
 ==================

-Supports x86, ARM and s390x currently.
+Supports x86, Arm and s390x currently.

 Caveats
 =======
--- a/docs/specs/fsi.rst
+++ b/docs/specs/fsi.rst
@@ -40,7 +40,7 @@ for the implementation are: (see the `FSI specification`_ for more details)
   MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
   address space.

-5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
+5. An APB-to-OPB bridge enabling access to the OPB from the Arm core in the
   AST2600. Hardware limitations prevent the OPB from being directly mapped
   into APB, so all accesses are indirect through the bridge.

--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -5,7 +5,7 @@ The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
 Aspeed evaluation boards. They are based on different releases of the
 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
 AST2500 with an ARM1176JZS CPU (800MHz), the AST2600
-with dual cores ARM Cortex-A7 CPUs (1.2GHz).
+with dual cores Arm Cortex-A7 CPUs (1.2GHz).

 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
 etc.
@@ -279,7 +279,7 @@ Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``)

 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards.
 They are based on different releases of the Aspeed SoC :
-the AST2700 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz).
+the AST2700 with quad cores Arm Cortex-A35 64 bits CPUs (1.6GHz).

 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
 etc.
@@ -453,7 +453,7 @@ Aspeed MiniBMC and Platform Root of Trust processor family boards (``ast1030-evb

 The QEMU Aspeed machines model mini BMCs and Platform Root of Trust processors of various Aspeed
 evaluation boards. They are based on different releases of the Aspeed SoC : the AST1030 (MiniBMC)
-and AST1060 (Platform Root of Trust Processor), both integrating an ARM Cortex M4F CPU (200MHz).
+and AST1060 (Platform Root of Trust Processor), both integrating an Arm Cortex M4F CPU (200MHz).

 The SoC comes with SRAM, SPI, I2C, etc.

--- a/docs/system/arm/b-l475e-iot01a.rst
+++ b/docs/system/arm/b-l475e-iot01a.rst
@@ -2,7 +2,7 @@ B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)
 ============================================

 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on
-ARM Cortex-M4F core. It is part of STMicroelectronics
+an Arm Cortex-M4F core. It is part of STMicroelectronics
 :doc:`STM32 boards </system/arm/stm32>` and more specifically the STM32L4
 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and
 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board
--- a/docs/system/arm/nrf.rst
+++ b/docs/system/arm/nrf.rst
@@ -1,7 +1,7 @@
 Nordic nRF boards (``microbit``)
 ================================

-The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that
+The `Nordic nRF`_ chips are a family of Arm-based System-on-Chip that
 are designed to be used for low-power and short-range wireless solutions.

 .. _Nordic nRF: https://www.nordicsemi.com/Products
@@ -18,7 +18,7 @@ supported by QEMU.
 Supported devices
 -----------------

- * ARM Cortex-M0 (ARMv6-M)
+ * Arm Cortex-M0 (ARMv6-M)
 * Serial ports (UART)
 * Clock controller
 * Timers
--- a/docs/system/arm/stm32.rst
+++ b/docs/system/arm/stm32.rst
@@ -1,24 +1,24 @@
 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vldiscovery``)
 ===============================================================================================================

-The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
+The `STM32`_ chips are a family of 32-bit Arm-based microcontrollers by
 STMicroelectronics.

 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html

-The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
+The STM32F1 series is based on an Arm Cortex-M3 core. The following machines are
 based on this chip :

 - ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller

-The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
+The STM32F2 series is based on an Arm Cortex-M3 core. The following machines are
 based on this chip :

 - ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller

-The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
+The STM32F4 series is based on an Arm Cortex-M4F core, as well as the STM32L4
 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
-The following machines are based on this ARM Cortex-M4F chip :
+The following machines are based on this Arm Cortex-M4F chip :

 - ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
 - ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
@@ -29,7 +29,7 @@ There are many other STM32 series that are currently not supported by QEMU.
 Supported devices
 -----------------

- * ARM Cortex-M3, Cortex M4F
+ * Arm Cortex-M3, Cortex-M4F
 * Analog to Digital Converter (ADC)
 * EXTI interrupt
 * Serial ports (USART)
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/system/arm/xlnx-versal-virt.rst
@@ -27,12 +27,12 @@ Versal
 """"""
 Implemented CPU cores:

- 2 ACPUs (ARM Cortex-A72) with their GICv3 and ITS
- 2 RCPUs (ARM Cortex-R5F) with their GICv2
+- 2 ACPUs (Arm Cortex-A72) with their GICv3 and ITS
+- 2 RCPUs (Arm Cortex-R5F) with their GICv2

 Implemented devices:

- 2 UARTs (ARM PL011)
+- 2 UARTs (Arm PL011)
 - An RTC (Versal built-in)
 - 2 GEMs (Cadence MACB Ethernet MACs)
 - 8 ADMA (Xilinx zDMA) channels
@@ -51,12 +51,12 @@ Versal Gen 2
 """"""""""""
 Implemented CPU cores:

- 8 ACPUs (ARM Cortex-A78AE) with their GICv3 and ITS
- 10 RCPUs (ARM Cortex-R52) with their GICv3 (one per cluster)
+- 8 ACPUs (Arm Cortex-A78AE) with their GICv3 and ITS
+- 10 RCPUs (Arm Cortex-R52) with their GICv3 (one per cluster)

 Implemented devices:

- 2 UARTs (ARM PL011)
+- 2 UARTs (Arm PL011)
 - An RTC (Versal built-in)
 - 3 GEMs (Cadence MACB Ethernet MACs)
 - 8 ADMA (Xilinx zDMA) channels
@@ -134,7 +134,7 @@ Direct Linux boot of PetaLinux 2019.2:
      -device virtio-rng-device,bus=virtio-mmio-bus.0,rng=rng0 \
      -object rng-random,filename=/dev/urandom,id=rng0

-Boot PetaLinux 2019.2 via ARM Trusted Firmware (2018.3 because the 2019.2
+Boot PetaLinux 2019.2 via Arm Trusted Firmware (2018.3 because the 2019.2
 version of ATF tries to configure the CCI which we don't model) and U-boot:

 .. code-block:: bash
@@ -188,7 +188,7 @@ Run the following at the U-Boot prompt:
  fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
  booti 30000000 - 20000000

-Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot:
+Boot Linux as Dom0 on Xen via Arm Trusted Firmware and U-Boot:

 .. code-block:: bash

--- a/docs/system/guest-loader.rst
+++ b/docs/system/guest-loader.rst
@@ -32,7 +32,7 @@ size. Additional information can be passed with by using additional
 arguments.

 Currently the only supported machines which use FDT data to boot are
-the ARM and RiscV ``virt`` machines.
+the Arm and RiscV ``virt`` machines.

 Arguments
 ^^^^^^^^^
--- a/docs/system/replay.rst
+++ b/docs/system/replay.rst
@@ -23,7 +23,7 @@ Deterministic replay has the following features:
   the memory, state of the hardware devices, clocks, and screen of the VM.
 * Writes execution log into the file for later replaying for multiple times
   on different machines.
- * Supports i386, x86_64, ARM, AArch64, Risc-V, MIPS, MIPS64, S390X, Alpha,
+ * Supports i386, x86_64, Arm, AArch64, Risc-V, MIPS, MIPS64, S390X, Alpha,
   PowerPC, PowerPC64, M68000, Microblaze, OpenRISC, SPARC,
   and Xtensa hardware platforms.
 * Performs deterministic replay of all operations with keyboard and mouse