target/riscv: Introduce externally facing CSR access functions

Convert riscv_csr_[read|write]() into target_ulong angnostic CSR access
functions that can be safely used from outside of target/ without
knowledge of the target register size.  Replace the 4 existing CSR
accesses in hw/ and linux-user/.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260520125406.28693-25-anjo@rev.ng>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anton Johansson
2026-05-20 14:54:02 +02:00
committed by Alistair Francis
parent cfc1d1ade1
commit e59bd5cdb7
5 changed files with 27 additions and 20 deletions

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@@ -67,12 +67,11 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
CPURISCVState *env = &cpu->env;
int ret = RISCV_EXCP_NONE;
RISCVException ret = RISCV_EXCP_NONE;
if (strcmp(cmd, "get_csr") == 0) {
ret = riscv_csrr(env, csrno, (target_ulong *)val);
ret = riscv_csr_read_i64(env, csrno, val);
} else if (strcmp(cmd, "set_csr") == 0) {
ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
ret = riscv_csr_write_i64(env, csrno, *val);
}
g_assert(ret == RISCV_EXCP_NONE);

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@@ -90,7 +90,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
uint64_t fcsr;
riscv_csr_read_i64(env, CSR_FCSR, &fcsr);
__put_user(fcsr, &sc->fcsr);
}
@@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
riscv_csr_write(env, CSR_FCSR, fcsr);
riscv_csr_write_i64(env, CSR_FCSR, fcsr);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)

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@@ -905,7 +905,12 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
#include "target/riscv/csr.h"
/*
* Externally facing CSR access functions, wrappers around riscv_csr*().
*/
RISCVException riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val);
RISCVException riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res);
/*
* The event id are encoded based on the encoding specified in the

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@@ -5751,6 +5751,21 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, ra);
}
RISCVException riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val)
{
return riscv_csrrw(env, csrno, NULL, val,
MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
}
RISCVException riscv_csr_read_i64(CPURISCVState *env, int csrno, uint64_t *res)
{
RISCVException ret;
target_ulong val = 0;
ret = riscv_csrr(env, csrno, &val);
*res = val;
return ret;
}
static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
Int128 *ret_value,
Int128 new_value,

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@@ -26,19 +26,6 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
target_ulong new_value,
target_ulong write_mask);
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
}
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrr(env, csrno, &val);
return val;
}
typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
int csrno);
typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,