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hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic

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Change send_dummy_bits() to send_dummy_bytes() as the FIU register
fields are programmed from spi_mem_op.dummy.nbytes, so they already
describe byte transfers.

Verified the changes by booting OpenBMC image on `gbs` machine all
the way to the Linux login shell:

$ qemu-system-arm -machine quanta-gbs-bmc -nographic \
      -drive file=image.mtd,if=mtd,bus=0,unit=0,format=raw

Fixes: b821242c7b ("hw/ssi: NPCM7xx Flash Interface Unit device model")
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Message-ID: <20260707083431.219671-6-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
This commit is contained in:
Bin Meng
2026-07-07 16:34:24 +08:00
committed by Philippe Mathieu-Daudé
parent 4957f668c4
commit f641d3bed2
1 changed files with 8 additions and 17 deletions
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25
hw/ssi/npcm7xx_fiu.c
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@@ -150,7 +150,7 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
NPCM7xxFIUState *fiu = f->fiu;
uint64_t value = 0;
uint32_t drd_cfg;
int dummy_cycles;
int dummy_bytes;
int i;
if (fiu->active_cs != -1) {
@@ -180,10 +180,8 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
break;
}
/* Flash chip model expects one transfer per dummy bit, not byte */
dummy_cycles =
(FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
for (i = 0; i < dummy_cycles; i++) {
dummy_bytes = FIU_DRD_CFG_DBW(drd_cfg);
for (i = 0; i < dummy_bytes; i++) {
ssi_transfer(fiu->spi, 0);
}
@@ -305,20 +303,13 @@ static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
}
}
/* Send the number of dummy bits specified in the UMA config register. */
static void send_dummy_bits(SSIBus *spi, uint32_t uma_cfg, uint32_t uma_cmd)
/* Send the number of dummy bytes specified in the UMA config register */
static void send_dummy_bytes(SSIBus *spi, uint32_t uma_cfg)
{
unsigned int bits_per_clock = 1U << FIU_UMA_CFG_DBPCK(uma_cfg);
unsigned int i;
for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) {
/* Use bytes 0 and 1 first, then keep repeating byte 2 */
unsigned int field = (i < 2) ? ((i + 1) * 8) : 24;
unsigned int j;
for (j = 0; j < 8; j += bits_per_clock) {
ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock));
}
ssi_transfer(spi, 0);
}
}
@@ -354,8 +345,8 @@ static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
ssi_transfer(s->spi, extract32(s->regs[reg], field, 8));
}
/* Send dummy bits, if present. */
send_dummy_bits(s->spi, uma_cfg, s->regs[NPCM7XX_FIU_UMA_CMD]);
/* Send dummy bytes, if present */
send_dummy_bytes(s->spi, uma_cfg);
/* Read data, if present. */
for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) {