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target/riscv: Inline cpu_ld[lq]_code() calls

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In preparation of removing the cpu_ldl_code() and cpu_ldq_code()
wrappers, inline them.

Since RISC-V instructions are always stored in little-endian order
(see "Volume I: RISC-V Unprivileged ISA" document, chapter
'Instruction Encoding Spaces and Prefixes': "instruction fetch
in RISC-V is little-endian"), replace MO_TE -> MO_LE.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260202214317.99090-1-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-11-20 20:47:20 +01:00
parent b9789d2993
commit f7f4cd501c
2 changed files with 8 additions and 3 deletions
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3
target/riscv/translate.c
View File

@@ -1181,8 +1181,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUState *cpu = ctx->cs;
CPURISCVState *env = cpu_env(cpu);
MemOpIdx oi = make_memop_idx(MO_LEUL, cpu_mmu_index(cpu, true));
return cpu_ldl_code(env, pc);
return cpu_ldl_code_mmu(env, pc, oi, 0);
}
#define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)

8
target/riscv/zce_helper.c
View File

@@ -23,6 +23,8 @@
target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
{
unsigned mmu_index = cpu_mmu_index(env_cpu(env), true);
MemOpIdx oi;
#if !defined(CONFIG_USER_ONLY)
RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
@@ -43,11 +45,13 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
}
if (xlen == 32) {
oi = make_memop_idx(MO_LEUL, mmu_index);
t0 = base + (index << 2);
target = cpu_ldl_code(env, t0);
target = cpu_ldl_code_mmu(env, t0, oi, 0);
} else {
oi = make_memop_idx(MO_LEUQ, mmu_index);
t0 = base + (index << 3);
target = cpu_ldq_code(env, t0);
target = cpu_ldq_code_mmu(env, t0, oi, 0);
}
return target & ~0x1;