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i386/cpu: Cache EGPRs in CPUX86State

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Expend general registers array "regs" of CPUX86State to cache entended
GPRs.

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20251211070942.3612547-4-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Zide Chen
2025-12-11 15:09:36 +08:00
committed by Paolo Bonzini
parent bb9f99e9ba
commit 1b1cf88937
2 changed files with 21 additions and 2 deletions
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7
target/i386/cpu.h
View File

@@ -1664,12 +1664,15 @@ typedef struct {
uint64_t mask;
} MTRRVar;
#define CPU_NB_EREGS64 32
#define CPU_NB_REGS64 16
#define CPU_NB_REGS32 8
#ifdef TARGET_X86_64
#define CPU_NB_EREGS CPU_NB_EREGS64
#define CPU_NB_REGS CPU_NB_REGS64
#else
#define CPU_NB_EREGS CPU_NB_REGS32
#define CPU_NB_REGS CPU_NB_REGS32
#endif
@@ -1901,7 +1904,7 @@ typedef struct CPUCaches {
typedef struct CPUArchState {
/* standard registers */
target_ulong regs[CPU_NB_REGS];
target_ulong regs[CPU_NB_EREGS];
target_ulong eip;
target_ulong eflags; /* eflags register. During CPU emulation, CC
flags and DF are set to zero because they are
@@ -1958,7 +1961,7 @@ typedef struct CPUArchState {
float_status mmx_status; /* for 3DNow! float ops */
float_status sse_status;
uint32_t mxcsr;
ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
ZMMReg xmm_regs[CPU_NB_EREGS] QEMU_ALIGNED(16);
ZMMReg xmm_t0 QEMU_ALIGNED(16);
MMXReg mmx_t0;

16
target/i386/xsave_helper.c
View File

@@ -140,6 +140,14 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen)
memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata));
}
e = &x86_ext_save_areas[XSTATE_APX_BIT];
if (e->size && e->offset && buflen) {
XSaveAPX *apx = buf + e->offset;
memcpy(apx, &env->regs[CPU_NB_REGS],
sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REGS));
}
#endif
}
@@ -275,5 +283,13 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen)
memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata));
}
e = &x86_ext_save_areas[XSTATE_APX_BIT];
if (e->size && e->offset) {
const XSaveAPX *apx = buf + e->offset;
memcpy(&env->regs[CPU_NB_REGS], apx,
sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REGS));
}
#endif
}