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Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles"

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This reverts commit f95c4bffdc.

The m25p80 model now accounts for fast-read dummy bytes in its
command decoder. In ASPEED SMC model user mode, guest software
already sends the complete byte stream, including any dummy
bytes needed by the flash. Hence the model should just forward
exactly the bytes supplied by the guest without the need of
decoding guest-supplied flash op codes to inject extra dummy
transfers.

Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Message-ID: <20260707083431.219671-10-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
This commit is contained in:
Bin Meng
2026-07-07 16:34:28 +08:00
committed by Philippe Mathieu-Daudé
parent a0688f3f80
commit 27961a043c
3 changed files with 2 additions and 115 deletions
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114
hw/ssi/aspeed_smc.c
View File

@@ -197,9 +197,6 @@
/* Flash opcodes. */
#define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SNOOP_OFF 0xFF
#define SNOOP_START 0x0
/*
* Default segments mapping addresses and size for each peripheral per
* controller. These can be changed when board is initialized with the
@@ -537,104 +534,6 @@ static MemTxResult aspeed_smc_flash_read(void *opaque, hwaddr addr,
return MEMTX_OK;
}
/*
* TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
* common include header.
*/
typedef enum {
READ = 0x3, READ_4 = 0x13,
FAST_READ = 0xb, FAST_READ_4 = 0x0c,
DOR = 0x3b, DOR_4 = 0x3c,
QOR = 0x6b, QOR_4 = 0x6c,
DIOR = 0xbb, DIOR_4 = 0xbc,
QIOR = 0xeb, QIOR_4 = 0xec,
PP = 0x2, PP_4 = 0x12,
DPP = 0xa2,
QPP = 0x32, QPP_4 = 0x34,
} FlashCMD;
static int aspeed_smc_num_dummies(uint8_t command)
{
switch (command) { /* check for dummies */
case READ: /* no dummy bytes/cycles */
case PP:
case DPP:
case QPP:
case READ_4:
case PP_4:
case QPP_4:
return 0;
case FAST_READ:
case DOR:
case QOR:
case DOR_4:
case QOR_4:
return 1;
case DIOR:
case FAST_READ_4:
case DIOR_4:
return 2;
case QIOR:
case QIOR_4:
return 4;
default:
return -1;
}
}
static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
unsigned size)
{
AspeedSMCState *s = fl->controller;
uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
(uint8_t) data & 0xff);
if (s->snoop_index == SNOOP_OFF) {
return false; /* Do nothing */
} else if (s->snoop_index == SNOOP_START) {
uint8_t cmd = data & 0xff;
int ndummies = aspeed_smc_num_dummies(cmd);
/*
* No dummy cycles are expected with the current command. Turn
* off snooping and let the transfer proceed normally.
*/
if (ndummies <= 0) {
s->snoop_index = SNOOP_OFF;
return false;
}
s->snoop_dummies = ndummies * 8;
} else if (s->snoop_index >= addr_width + 1) {
/* The SPI transfer has reached the dummy cycles sequence */
for (; s->snoop_dummies; s->snoop_dummies--) {
ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
}
/* If no more dummy cycles are expected, turn off snooping */
if (!s->snoop_dummies) {
s->snoop_index = SNOOP_OFF;
} else {
s->snoop_index += size;
}
/*
* Dummy cycles have been faked already. Ignore the current
* SPI transfer
*/
return true;
}
s->snoop_index += size;
return false;
}
static MemTxResult aspeed_smc_flash_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size, MemTxAttrs attrs)
{
@@ -652,10 +551,6 @@ static MemTxResult aspeed_smc_flash_write(void *opaque, hwaddr addr,
switch (aspeed_smc_flash_mode(fl)) {
case CTRL_USERMODE:
if (aspeed_smc_do_snoop(fl, data, size)) {
break;
}
for (i = 0; i < size; i++) {
ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
}
@@ -717,7 +612,6 @@ static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
s->regs[s->r_ctrl0 + fl->cs] = value;
if (unselect != s->unselect) {
s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
aspeed_smc_flash_do_select(fl, unselect);
}
}
@@ -763,9 +657,6 @@ static void aspeed_smc_reset_hold(Object *obj, ResetType type)
aspeed_smc_flash_set_segment_region(s, i,
asc->segment_to_reg(s, &asc->segments[i]));
}
s->snoop_index = SNOOP_OFF;
s->snoop_dummies = 0;
}
static MemTxResult aspeed_smc_read(void *opaque, hwaddr addr, uint64_t *data,
@@ -1293,11 +1184,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_aspeed_smc = {
.name = "aspeed.smc",
.version_id = 3,
.minimum_version_id = 2,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
VMSTATE_UINT8(snoop_index, AspeedSMCState),
VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
VMSTATE_UNUSED_V(2, 2), /* was snoop_index/snoop_dummies */
VMSTATE_BOOL_V(unselect, AspeedSMCState, 3),
VMSTATE_END_OF_LIST()
}

1
hw/ssi/trace-events
View File

@@ -2,7 +2,6 @@
aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"

2
include/hw/ssi/aspeed_smc.h
View File

@@ -80,8 +80,6 @@ struct AspeedSMCState {
AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX];
uint8_t snoop_index;
uint8_t snoop_dummies;
bool unselect;
};