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hw/pci: Factor out common PASID capability initialization

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Refactor PCIe PASID capability initialization by moving the common
register init into a new helper, pcie_pasid_common_init().

Subsequent patch to synthesize a vPASID will make use of this
helper.

No functional change intended.

Cc: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-id: 20260126104342.253965-36-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Shameer Kolothum
2026-01-29 13:32:05 +00:00
committed by Peter Maydell
parent 49a2bed19b
commit 7d59fa2059
2 changed files with 14 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
hw/pci/pcie.c
View File

@@ -1284,18 +1284,13 @@ void pcie_acs_reset(PCIDevice *dev)
}
}
/* PASID */
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod)
void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset,
uint8_t pasid_width, bool exec_perm, bool priv_mod)
{
static const uint16_t control_reg_rw_mask = 0x07;
uint16_t capability_reg;
assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH);
pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
PCI_EXT_CAP_PASID_SIZEOF);
capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT;
capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0;
capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0;
@@ -1307,6 +1302,16 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask);
dev->exp.pasid_cap = offset;
}
/* PASID */
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
PCI_EXT_CAP_PASID_SIZEOF);
pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod);
}
/* PRI */

2
include/hw/pci/pcie.h
View File

@@ -155,6 +155,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp);
void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset,
uint8_t pasid_width, bool exec_perm, bool priv_mod);
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod);
void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap,