starred/qemu-qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2026-07-08 17:46:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

disas: diassemble RISC-V xlrbr (crc32) instructions

Browse Source 
Placed in a separate file as a vendor extension.

Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260320134254.217123-4-james.wainwright@lowrisc.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Emmanuel Blot
2026-03-20 13:42:54 +00:00
committed by Alistair Francis
parent 32bbab666e
commit af58a69046
5 changed files with 103 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@@ -4135,7 +4135,7 @@ R: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv64/
F: disas/riscv.[ch]
F: disas/riscv*.[ch]
S390 TCG target
M: Richard Henderson <richard.henderson@linaro.org>

3
disas/meson.build
View File

@@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
'riscv.c',
'riscv-xthead.c',
'riscv-xventana.c'
'riscv-xventana.c',
'riscv-xlrbr.c'
))
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))

79
disas/riscv-xlrbr.c Normal file
View File

@@ -0,0 +1,79 @@
/*
* QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
* bitmanip extension v0.93.
*
* Copyright (c) 2023 Rivos Inc
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "disas/riscv.h"
#include "disas/riscv-xlrbr.h"
typedef enum {
/* 0 is reserved for rv_op_illegal. */
rv_op_crc32_b = 1,
rv_op_crc32_h = 2,
rv_op_crc32_w = 3,
rv_op_crc32_d = 4,
rv_op_crc32c_b = 5,
rv_op_crc32c_h = 6,
rv_op_crc32c_w = 7,
rv_op_crc32c_d = 8,
} rv_xlrbr_op;
const rv_opcode_data rv_xlrbr_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
};
void decode_xlrbr(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
switch ((inst >> 0) & 0b1111111) {
case 0b0010011:
switch ((inst >> 12) & 0b111) {
case 0b001:
switch ((inst >> 20 & 0b111111111111)) {
case 0b011000010000:
op = rv_op_crc32_b;
break;
case 0b011000010001:
op = rv_op_crc32_h;
break;
case 0b011000010010:
op = rv_op_crc32_w;
break;
case 0b011000010011:
op = rv_op_crc32_d;
break;
case 0b011000011000:
op = rv_op_crc32c_b;
break;
case 0b011000011001:
op = rv_op_crc32c_h;
break;
case 0b011000011010:
op = rv_op_crc32c_w;
break;
case 0b011000011011:
op = rv_op_crc32c_d;
break;
}
break;
}
break;
}
dec->op = op;
}

19
disas/riscv-xlrbr.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
* bitmanip extension v0.93.
*
* Copyright (c) 2023 Rivos Inc
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef DISAS_RISCV_XLRBR_H
#define DISAS_RISCV_XLRBR_H
#include "disas/riscv.h"
extern const rv_opcode_data rv_xlrbr_opcode_data[];
void decode_xlrbr(rv_decode *, rv_isa);
#endif /* DISAS_RISCV_XLRBR_H */

2
disas/riscv.c
View File

@@ -26,6 +26,7 @@
/* Vendor extensions */
#include "disas/riscv-xthead.h"
#include "disas/riscv-xventana.h"
#include "disas/riscv-xlrbr.h"
typedef enum {
/* 0 is reserved for rv_op_illegal. */
@@ -5434,6 +5435,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
{ has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
{ has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
{ has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
{ has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
};
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {