Files
qemu-qemu/disas/hexagon.c
Taylor Simpson 6a71b3b5ec Hexagon (target/hexagon) Disassembly of invalid packets
We pass the Hexagon CPU definition to disassemble_hexagon.  This allows
decode_packet to know if the opcodes are supported.

Note that we print valid instructions in a packet when one or more is
invalid.  Rather than this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		<invalid>
0x00021294:  0x1e03edf0		<invalid> }

We print this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		V4.w = vadd(V12.w,V3.w)
0x00021294:  0x1e03edf0		V16 = V13 }

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
2026-04-23 14:49:38 -07:00

2.1 KiB