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docs: Add hexagon sysemu docs
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This commit is contained in:
Brian Cain
Brian Cain
@@ -258,6 +258,9 @@ F: disas/hexagon.c
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F: configs/targets/hexagon-linux-user.mak
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F: tests/docker/dockerfiles/debian-hexagon-cross.docker
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F: gdbstub/gdb-xml/hexagon*.xml
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F: docs/system/target-hexagon.rst
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F: docs/system/hexagon/
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F: docs/devel/hexagon-sys.rst
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T: git https://github.com/qualcomm/qemu.git hex-next
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Hexagon idef-parser
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112
docs/devel/hexagon-sys.rst
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112
docs/devel/hexagon-sys.rst
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@@ -0,0 +1,112 @@
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.. SPDX-License-Identifier: GPL-2.0-or-later
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.. _Hexagon-System-arch:
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Hexagon System Architecture
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===========================
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The hexagon architecture has some unique elements which are described here.
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Interrupts
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----------
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When interrupts arrive at a Hexagon DSP core, they are priority-steered to
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be handled by an eligible hardware thread with the lowest priority.
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Memory
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------
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Each hardware thread has an ``SSR.ASID`` field that contains its Address
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Space Identifier. This value is catenated with a 32-bit virtual address -
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the MMU can then resolve this extended virtual address to a physical address.
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TLBs
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----
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The format of a TLB entry is shown below.
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.. note::
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The Small Core DSPs have a different TLB format which is not yet
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supported.
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.. admonition:: Diagram
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.. code:: text
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6 5 4 3
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|v|g|x|A|A| | |
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|a|l|P|1|0| ASID | Virtual Page |
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|l|b| | | | | |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1 0
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| | | | | | | |
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|x|w|r|u|Cacheab| Physical Page |S|
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* ASID: the address-space identifier
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* A1, A0: the behavior of these cache line attributes are not modeled by QEMU.
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* xP: the extra-physical bit is the most significant physical address bit.
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* S: the S bit and the LSBs of the physical page indicate the page size
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* val: this is the 'valid' bit, when set it indicates that page matching
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should consider this entry.
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.. list-table:: Page sizes
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:widths: 25 25 50
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:header-rows: 1
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* - S-bit
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- Phys page LSBs
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- Page size
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* - 1
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- N/A
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- 4kb
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* - 0
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- 0b1
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- 16kb
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* - 0
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- 0b10
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- 64kb
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* - 0
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- 0b100
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- 256kb
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* - 0
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- 0b1000
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- 1MB
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* - 0
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- 0b10000
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- 4MB
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* - 0
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- 0b100000
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- 16MB
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* glb: if the global bit is set, the ASID is not considered when matching
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TLBs.
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* Cacheab: the cacheability attributes of TLBs are not modeled, these bits
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are ignored.
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* RWX: read-, write-, execute-, enable bits. Indicates if user programs
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are permitted to read/write/execute the given page.
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* U: indicates if user programs can access this page.
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Scheduler
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---------
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The Hexagon system architecture has a feature to assist the guest OS
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task scheduler. The guest OS can enable this feature by setting
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``SCHEDCFG.EN``. The ``BESTWAIT`` register is programmed by the guest OS
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to indicate the priority of the highest priority task waiting to run on a
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hardware thread. The reschedule interrupt is triggered when any hardware
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thread's priority in ``STID.PRIO`` is worse than the ``BESTWAIT``. When
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it is triggered, the ``BESTWAIT.PRIO`` value is reset to 0x1ff.
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HVX Coprocessor
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---------------
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The Supervisor Status Register field ``SSR.XA`` binds a DSP hardware thread
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to one of the eight possible HVX contexts. The guest OS is responsible for
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managing this resource.
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.. seealso::
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``target/hexagon/README`` in the QEMU source tree for more info about Hexagon.
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@@ -14,6 +14,7 @@ Details about QEMU's various subsystems including how to add features to them.
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block-coroutine-wrapper
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clocks
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ebpf_rss
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hexagon-sys
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migration/index
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multi-process
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reset
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12
docs/system/hexagon/cdsp.rst
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12
docs/system/hexagon/cdsp.rst
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@@ -0,0 +1,12 @@
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.. SPDX-License-Identifier: GPL-2.0-or-later
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Compute DSP
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===========
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A Hexagon CDSP is designed as a computation offload device for an SoC. The
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``V66G_1024`` machine contains:
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* L2VIC interrupt controller
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* QTimer timer device
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This machine will support any Hexagon CPU, but will default to ``v66``.
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101
docs/system/target-hexagon.rst
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101
docs/system/target-hexagon.rst
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@@ -0,0 +1,101 @@
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.. SPDX-License-Identifier: GPL-2.0-or-later
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.. _Hexagon-System-emulator:
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Hexagon System emulator
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-----------------------
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Use the ``qemu-system-hexagon`` executable to simulate a 32-bit Hexagon
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machine.
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Hexagon Machines
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================
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Hexagon DSPs are suited to various functions and generally appear in a
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"DSP subsystem" of a larger system-on-chip (SoC).
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Hexagon DSPs are often included in a subsystem that looks like the diagram
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below. Instructions are loaded into DDR before the DSP is brought out of
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reset and the first instructions are fetched from DDR via the EVB/reset vector.
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In a real system, a TBU/SMMU would normally arbitrate AXI accesses but
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we don't have a need to model that for QEMU.
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Hexagon DSP cores use simultaneous multithreading (SMT) with as many as 8
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hardware threads.
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.. admonition:: Diagram
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.. code:: text
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AHB (local) bus AXI (global) bus
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│ │
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│ │
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┌─────────┐ │ ┌─────────────────┐ │
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│ L2VIC ├──┤ │ │ │
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│ ├──┼───────► ├───────┤
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└─────▲───┘ │ │ Hexagon DSP │ │
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│ │ │ │ │ ┌─────┐
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│ │ │ N threads │ │ │ DDR │
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│ ├───────┤ │ │ │ │
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┌────┴──┐ │ │ │ ├────────┤ │
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│QTimer ├───┤ │ │ │ │ │
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│ │ │ │ │ │ │ │
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└───────┘ │ │ ┌─────────┐ │ │ │ │
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│ │ ┌─────────┐│ │ │ │ │
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┌───────┐ │ │ │ HVX xM ││ │ │ │ │
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│QDSP6SS├───┤ │ │ │┘ │ │ │ │
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└───────┘ │ │ └─────────┘ │ │ └─────┘
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│ │ │ │
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┌───────┐ │ └─────────────────┘ │
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│ CSR ├───┤
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└───────┘ │ ┌──────┐ ┌───────────┐
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│ │ TCM │ │ VTCM │
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│ │ │ │
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└──────┘ │ │
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│ │
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│ │
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│ │
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└───────────┘
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Components
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----------
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Other than l2vic and HVX, the components below are not implemented in QEMU.
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* L2VIC: the L2 vectored interrupt controller. Supports 1024 input
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interrupts, edge- or level-triggered. The core ISA has system registers
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``VID``, ``VID1`` which read through to the L2VIC device.
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* QTimer: ARMSSE-based programmable timer device. Its interrupts are
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wired to the L2VIC. System registers ``TIMER``, ``UTIMER`` read
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through to the QTimer device.
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* QDSP6SS: DSP subsystem features, accessible to the entire SoC, including
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DSP NMI, watchdog, reset, etc.
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* CSR: Configuration/Status Registers.
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* TCM: DSP-exclusive tightly-coupled memory. This memory can be used for
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DSPs when isolated from DDR and in some bootstrapping modes.
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* VTCM: DSP-exclusive vector tightly-coupled memory. This memory is accessed
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by some HVX instructions.
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* HVX: the vector coprocessor supports 64 and 128-byte vector registers.
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64-byte mode is not implemented in QEMU.
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Bootstrapping
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-------------
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Hexagon systems do not generally have access to a block device. So, for
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QEMU the typical use case involves loading a binary or ELF file into memory
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and executing from the indicated start address::
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$ qemu-system-hexagon -kernel ./prog -append 'arg1 arg2'
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Semihosting
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-----------
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Hexagon supports a semihosting interface similar to other architectures'.
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The ``trap0`` instruction can activate these semihosting calls so that the
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guest software can access the host console and filesystem. Semihosting
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is not yet implemented in QEMU hexagon.
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Hexagon Features
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================
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.. toctree::
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hexagon/cdsp
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@@ -30,3 +30,4 @@ Contents:
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target-sparc64
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target-i386
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target-xtensa
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target-hexagon
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