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target/arm: Implement FEAT_FAMINMAX for SME

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Since there is no bfloat16 variant of FAMINMAX,
check for missing function pointer in do_z2z_nn_fpst.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2026-05-22 15:02:05 -07:00
committed by Peter Maydell
parent dbbcf746c2
commit 1de033cf3e
3 changed files with 31 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
target/arm/cpu-features.h
View File

@@ -1593,6 +1593,11 @@ static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id)
return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id);
}
static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)
{
return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);
}
static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
{
return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);

5
target/arm/tcg/sme.decode
View File

@@ -286,6 +286,11 @@ URSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 1 @z2z_4x4
SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_2x2
SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_4x4
FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_2x2
FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4
FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2
FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4
### SME2 Multi-vector Multiple and Single Array Vectors
&azz_n n off rv zn zm

23
target/arm/tcg/translate-sme.c
View File

@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "helper-a64.h"
#include "helper-sme.h"
#include "helper-sve.h"
#include "translate.h"
@@ -742,9 +743,12 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,
gen_helper_gvec_3_ptr * const fns[4])
{
int esz = a->esz, n, dn, dm, vsz;
gen_helper_gvec_3_ptr *fn;
gen_helper_gvec_3_ptr *fn = fns[esz];
TCGv_ptr fpst;
if (fn == NULL) {
return false;
}
if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
return false;
}
@@ -753,7 +757,6 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,
}
fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
fn = fns[esz];
n = a->n;
dn = a->zdn;
dm = a->zm;
@@ -812,6 +815,22 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] = {
TRANS_FEAT(FMINNM_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fminnm)
TRANS_FEAT(FMINNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fminnm)
static gen_helper_gvec_3_ptr * const f_vector_famax[4] = {
NULL,
gen_helper_gvec_famax_h,
gen_helper_gvec_famax_s,
gen_helper_gvec_famax_d,
};
TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famax)
static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {
NULL,
gen_helper_gvec_famin_h,
gen_helper_gvec_famin_s,
gen_helper_gvec_famin_d,
};
TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)
/* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */
static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,
GVecGen3FnVar *fn)