starred/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2026-07-08 17:46:10 +00:00
Code Issues 380 Packages Projects Releases Wiki Activity

target/arm: Implement ID_AA64FPFR0

Browse Source 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2026-05-22 15:02:20 -07:00
committed by Peter Maydell
parent 2430d49a17
commit 2bdfbfe7f8
4 changed files with 22 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
target/arm/cpu-features.h
View File

@@ -410,6 +410,15 @@ FIELD(ID_AA64SMFR0, I16I64, 52, 4)
FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
FIELD(ID_AA64SMFR0, FA64, 63, 1)
FIELD(ID_AA64FPFR0, F8E5M2, 0, 1)
FIELD(ID_AA64FPFR0, F8E4M3, 1, 1)
FIELD(ID_AA64FPFR0, F8MM4, 26, 1)
FIELD(ID_AA64FPFR0, F8MM8, 27, 1)
FIELD(ID_AA64FPFR0, F8DP2, 28, 1)
FIELD(ID_AA64FPFR0, F8DP4, 29, 1)
FIELD(ID_AA64FPFR0, F8FMA, 30, 1)
FIELD(ID_AA64FPFR0, F8CVT, 31, 1)
FIELD(ID_DFR0, COPDBG, 0, 4)
FIELD(ID_DFR0, COPSDBG, 4, 4)
FIELD(ID_DFR0, MMAPDBG, 8, 4)

1
target/arm/cpu-sysregs.h.inc
View File

@@ -3,6 +3,7 @@ DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)

1
target/arm/cpu.c
View File

@@ -1768,6 +1768,7 @@ static void arm_clear_aarch64_idregs(ARMCPU *cpu)
SET_IDREG(&cpu->isar, ID_AA64AFR1, 0);
SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);
SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);
SET_IDREG(&cpu->isar, ID_AA64FPFR0, 0);
}
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

13
target/arm/helper.c
View File

@@ -6477,11 +6477,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_tid3,
.resetvalue = 0 },
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
{ .name = "ID_AA64FPFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_tid3,
.resetvalue = 0 },
.resetvalue = GET_IDREG(isar, ID_AA64FPFR0) },
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -6712,6 +6712,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
R_ID_AA64SMFR0_I16I64_MASK |
R_ID_AA64SMFR0_SMEVER_MASK |
R_ID_AA64SMFR0_FA64_MASK },
{ .name = "ID_AA64FPFR0_EL1",
.exported_bits = R_ID_AA64FPFR0_F8E5M2_MASK |
R_ID_AA64FPFR0_F8E4M3_MASK |
R_ID_AA64FPFR0_F8MM4_MASK |
R_ID_AA64FPFR0_F8MM8_MASK |
R_ID_AA64FPFR0_F8DP2_MASK |
R_ID_AA64FPFR0_F8DP4_MASK |
R_ID_AA64FPFR0_F8FMA_MASK |
R_ID_AA64FPFR0_F8CVT_MASK },
{ .name = "ID_AA64MMFR0_EL1",
.exported_bits = R_ID_AA64MMFR0_ECV_MASK,
.fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |