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hw/riscv: Add macros and globals for simplifying machine definitions

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Adds macros and global interfaces for defining machines available only
in qemu-system-riscv32, qemu-system-riscv64, or both.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-3-d1123ea63d9c@rev.ng>
[PMD: Constify InterfaceInfo]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Anton Johansson
2025-04-30 13:44:17 +02:00
committed by Philippe Mathieu-Daudé
parent a045f6a8e8
commit 40838c8251
2 changed files with 44 additions and 1 deletions
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26
include/hw/riscv/machines-qom.h
View File

@@ -17,4 +17,30 @@
#define TYPE_TARGET_RISCV64_MACHINE \
"target-info-riscv64-machine"
/*
* Interfaces specifying whether a given QOM object is available in
* qemu-system-riscv32, qemu-system-riscv64, or both.
*/
extern const InterfaceInfo riscv32_machine_interfaces[];
extern const InterfaceInfo riscv64_machine_interfaces[];
extern const InterfaceInfo riscv32_64_machine_interfaces[];
/*
* Helper macros for defining machines available in qemu-system-riscv32,
* qemu-system-riscv64, or both.
*/
#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
riscv32_machine_interfaces)
#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
riscv64_machine_interfaces)
#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
riscv32_64_machine_interfaces)
#endif

19
target/riscv/machine.c
View File

@@ -22,7 +22,8 @@
#include "system/kvm.h"
#include "migration/cpu.h"
#include "exec/icount.h"
#include "debug.h"
#include "target/riscv/debug.h"
#include "hw/riscv/machines-qom.h"
static bool pmp_needed(void *opaque)
{
@@ -522,3 +523,19 @@ const VMStateDescription vmstate_riscv_cpu = {
NULL
}
};
const InterfaceInfo riscv32_machine_interfaces[] = {
{ TYPE_TARGET_RISCV32_MACHINE },
{ }
};
const InterfaceInfo riscv64_machine_interfaces[] = {
{ TYPE_TARGET_RISCV64_MACHINE },
{ }
};
const InterfaceInfo riscv32_64_machine_interfaces[] = {
{ TYPE_TARGET_RISCV32_MACHINE },
{ TYPE_TARGET_RISCV64_MACHINE },
{ }
};