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target/riscv: Update MISA.X for non-standard extensions

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MISA.X is set if there are any non-standard extensions.
We should set MISA.X when any of the vendor extensions is enabled.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260424050509.3935180-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
2026-04-24 13:05:09 +08:00
committed by Alistair Francis
parent f0433a8bc4
commit 613bb1949f
2 changed files with 16 additions and 0 deletions
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1
target/riscv/cpu.h
View File

@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;
#define RVH RV('H')
#define RVG RV('G')
#define RVB RV('B')
#define RVX RV('X')
extern const uint32_t misa_bits[];
const char *riscv_get_misa_ext_name(uint32_t bit);

15
target/riscv/tcg/tcg-cpu.c
View File

@@ -1201,6 +1201,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
}
}
/* MISA.X is set when any of the non-standard extensions is enabled. */
static void riscv_cpu_update_misa_x(RISCVCPU *cpu)
{
CPURISCVState *env = &cpu->env;
const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
for (int i = 0; arr[i].name != NULL; i++) {
if (isa_ext_is_enabled(cpu, arr[i].offset)) {
riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);
break;
}
}
}
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
@@ -1209,6 +1223,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
riscv_cpu_init_implied_exts_rules();
riscv_cpu_enable_implied_rules(cpu);
riscv_cpu_update_misa_c(cpu);
riscv_cpu_update_misa_x(cpu);
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {