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target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

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Having the callee add 1 to shift amount is misleading (see the
NM_LSA case in decode_nanomips_32_48_opc() where we have to
manually substract 1). Rather have the callers pass a modified
$sa.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241112172022.88348-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2024-11-12 16:19:18 +01:00
parent 23ecff81ac
commit 65a67f0fe5
5 changed files with 8 additions and 13 deletions
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2
target/mips/tcg/micromips_translate.c.inc
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@@ -1795,7 +1795,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);

4
target/mips/tcg/msa_translate.c
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@@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}

7
target/mips/tcg/nanomips_translate.c.inc
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@@ -3626,12 +3626,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_p_lsx(ctx, rd, rs, rt);
break;
case NM_LSA:
/*
* In nanoMIPS, the shift field directly encodes the shift
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));

4
target/mips/tcg/rel6_translate.c
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@@ -23,7 +23,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -31,7 +31,7 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a)

4
target/mips/tcg/translate_addr_const.c
View File

@@ -26,7 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
return true;
@@ -47,7 +47,7 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
return true;
}