target/arm: Enable FEAT_FAMINMAX for -cpu max

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2026-05-22 15:02:07 -07:00
committed by Peter Maydell
parent 9972384eb3
commit 697910f67f
3 changed files with 6 additions and 0 deletions

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@@ -68,6 +68,7 @@ the following architecture extensions:
- FEAT_EVT (Enhanced Virtualization Traps)
- FEAT_F32MM (Single-precision Matrix Multiplication)
- FEAT_F64MM (Double-precision Matrix Multiplication)
- FEAT_FAMINMAX (Floating-point maximum and minimum absolute value instructions)
- FEAT_FCMA (Floating-point complex number instructions)
- FEAT_FGT (Fine-Grained Traps)
- FEAT_FHM (Floating-point half-precision multiplication instructions)

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@@ -218,6 +218,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
GET_FEATURE_ID(aa64_sve_b16b16, ARM_HWCAP2_A64_SVE_B16B16);
GET_FEATURE_ID(aa64_cssc, ARM_HWCAP2_A64_CSSC);
GET_FEATURE_ID(aa64_lse128, ARM_HWCAP2_A64_LSE128);
GET_FEATURE_ID(aa64_faminmax, ARM_HWCAP2_A64_FAMINMAX);
return hwcaps;
}

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@@ -1266,6 +1266,10 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */
SET_IDREG(isar, ID_AA64ISAR2, t);
t = GET_IDREG(isar, ID_AA64ISAR3);
t = FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* FEAT_FAMINMAX */
SET_IDREG(isar, ID_AA64ISAR3, t);
t = GET_IDREG(isar, ID_AA64PFR0);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */